Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com> --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 01da065710..ed042f7bb9 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -739,7 +739,7 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <= sizeof(target_ulong)) && + ((1 << s->sew) <= (get_olen(s) / 8)) && ((1 << s->sew) >= 4)); } -- 2.25.1