> On Oct 21, 2021, at 11:11 PM, Cédric Le Goater wrote:
>
>>> And the FMC registers are just an alias to write
>>> to these watchdog 2 registers?
>> If this is the same watchdog mapped into the FMC, I would say yes
>> and the logic generate load/stores transactions on the AHB bus.
>> Adding an
k.git tags/q800-pull-request
for you to fetch changes up to a56c12fb760a57c1419df4a34e930160f1d8d428:
q800: drop 8-bit graphic_depth check for Apple 21 inch display (2021-10-20
16:25:04 +0200)
Pull request Q800 20211022
GLUE update
From: Mark Cave-Ayland
Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating
whether the hardware is configured for A/UX mode.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Message-Id: <20211020134131.4392-5-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: L
From: Mark Cave-Ayland
According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to
configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't
particularly descriptive, the patch leaves this to ensure that the constants
in mac_via.c remain in sync with Linux's ma
From: Mark Cave-Ayland
In order to allow dynamic routing of IRQs to different IRQ levels on the CPU
depending upon port B bit 6, use GLUE IRQ numbers and map them to the the
corresponding CPU IRQ level accordingly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Message-Id: <202110
From: Mark Cave-Ayland
Explicitly wire up the remaining IRQs in classic mode to enable the use of
g_assert_not_reached() in the default case to detect any unexpected IRQs.
Add a comment explaining the IRQ routing differences in A/UX mode based
upon the comments in NetBSD (also noting that at lea
From: Mark Cave-Ayland
This enables the GLUE logic to change its CPU level IRQ routing depending upon
whether the hardware has been configured for A/UX mode.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
Message-Id: <20211020134131.4392-6-mark.cave-ayl...@ilande.co.uk>
Signed-off
From: Mark Cave-Ayland
This allows the programmer's switch to be triggered via the monitor for
debugging
purposes. Since the CPU level 7 interrupt is level-triggered, use a timer to
hold
the NMI active for 100ms before releasing it again.
Signed-off-by: Mark Cave-Ayland
Reviewied-by: Laurent
From: Mark Cave-Ayland
On a Quadra 800 machine Linux sets via_alt_mapping to 1 and clears port B bit 6
to
ensure that the VIA1 IRQ is delivered at level 6 rather than level 1. Even
though
QEMU doesn't yet emulate this behaviour, Linux still installs the VIA1 level 1
IRQ
handler regardless of t
From: Mark Cave-Ayland
When the hardware is operating in classic mode the SONIC on-board Ethernet IRQ
is
routed to nubus IRQ 9 instead of directly to the CPU at level 3. This does not
affect the framebuffer which although it exists in slot 9, has its own
dedicated IRQ on the Quadra 800 hardware.
From: Mark Cave-Ayland
The graphic_depth check is no longer required since commit df8abbbadf ("macfb:
add common monitor modes supported by the MacOS toolbox ROM") which introduced
code in macfb_common_realize() to only allow the resolutions/depths provided in
macfb_mode_table to be specified for
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Message-Id: <20211018132609.160008-6-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/sd/aspeed_sdhci.c | 5 +
hw/sd/trace-events | 4
2 files changed, 9 insertions(+)
diff --git
Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225
("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use
alias") introduced an alias for the flash mmio region.
Using a container is cleaner.
Cc: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
Reviewed-by: Ph
The following changes since commit afc9fcde55296b83f659de9da3cdf044812a6eeb:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2021-10-20 06:10:51 -0700)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspeed-20211022
From: John Wang
The fp5280g2-bmc is supported by OpenBMC, It's
based on the following device tree
https://github.com/openbmc/linux/blob/dev-5.10/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
Signed-off-by: John Wang
Reviewed-by: Cédric Le Goater
Message-Id: <20211014064548.934799-1-wangzhi
Hi Richard,
I am implementing the UXL based on this patch set and have a question
about how to process the PC register.
As the specification said, "PC bits above XLEN are ignored, and when
the PC is written, it is sign-extended to fill the widest supported XLEN."
We still need special process o
On Thu, Oct 21, 2021 at 05:08:09PM -0700, Richard Henderson wrote:
> On 10/21/21 8:09 AM, Ruinland Chuan-Tzu Tsai wrote:
> > riscv_csrrw() will be called by CSR handling helpers, which is the
> > most suitable place for checking wheter a custom CSR is being accessed.
> >
> > If we're touching a cu
On Fri, Oct 22, 2021 at 08:43:08AM +1000, Alistair Francis wrote:
> On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai
> wrote:
> >
> > riscv_csrrw() will be called by CSR handling helpers, which is the
> > most suitable place for checking wheter a custom CSR is being accessed.
> >
> > If we'
On Fri, Oct 22, 2021 at 08:44:56AM +1000, Alistair Francis wrote:
> On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai
> wrote:
> >
> > Add CSR bits definitions, CSR table and handler functions for Andes
> > AX25 and A25 CPUs. Also, enable the logic in a(x)25_cpu_init().
> >
> > Signed-off-by
On Thu, Oct 21, 2021 at 09:11:44AM -0700, Richard Henderson wrote:
> On 10/21/21 8:11 AM, Ruinland Chuan-Tzu Tsai wrote:
> > -static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t
> > opcode)
> > +/* Custom insn related definitions/prototypes */
> > +extern __thread bool cpu_has_c
On Fri, Oct 22, 2021 at 10:33:15AM +0800, Peter Xu wrote:
> Hi, Michael,
>
> On Thu, Oct 21, 2021 at 06:54:59AM -0400, Michael S. Tsirkin wrote:
> > > +typedef struct {
> > > +pci_bus_dev_fn fn;
> > > +void *opaque;
> > > +} pci_bus_dev_args;
> >
> > code style violation. CamelCase for st
On Thu, Oct 21, 2021 at 12:17:47PM -0700, Richard Henderson wrote:
> On 10/21/21 8:11 AM, Ruinland Chuan-Tzu Tsai wrote:
> > In this patch, we demonstrate how Andes Performance Extension(c) insn :
> > bfos and bfoz could be used with Andes CoDense : exec.it.
> >
> > By doing so, an Andes vendor de
Aaron Lindsay writes:
> On Oct 21 13:28, Alex Bennée wrote:
>> It's a bit clearer if you use the contrib/execlog plugin:
>>
>> ./qemu-aarch64 -plugin contrib/plugins/libexeclog.so -d plugin
>> ./tests/tcg/aarch64-linux-user/stxp
>>
>> 0, 0x400910, 0xf9800011, "prfm pstl1strm, [x0]
>>
Include linux/falloc.h if CONFIG_FALLOCATE_ZERO_RANGE is defined to fix
https://gitlab.com/qemu-project/qemu/-/commit/50482fda98bd62e072c30b7ea73c985c4e9d9bbb
and avoid the following build failure on musl:
../block/export/fuse.c: In function 'fuse_fallocate':
../block/export/fuse.c:643:21: error:
Hi Eric,
On 2021/10/22 0:15, Eric Auger wrote:
Hi Kunkun,
On 9/14/21 3:53 AM, Kunkun Jiang wrote:
We expand MemoryRegions of vfio-pci sub-page MMIO BARs to
vfio_pci_write_config to improve IO performance.
s/to vfio_pci_write_config/ in vfio_pci_write_config()
Thank you for your review. I wil
Hi Eric,
On 2021/10/22 1:02, Eric Auger wrote:
Hi Kunkun,
On 9/14/21 3:53 AM, Kunkun Jiang wrote:
The MSI-X structures of some devices and other non-MSI-X structures
are in the same BAR. They may share one host page, especially in the
may be in the same bar?
You are right. So embarrassing.😅
Currently we make the assumption that the guest frontend loads all
op code bytes sequentially. This mostly holds up for regular fixed
encodings but some architectures like s390x like to re-read the
instruction which causes weirdness to occur. Rather than changing the
frontends make the plugin API a
On Fri, 15 Oct 2021, Eric DeVolder wrote:
> This change exposes ACPI ERST support for x86 guests.
>
> Signed-off-by: Eric DeVolder
> ---
> hw/i386/acpi-build.c | 9 +
> hw/i386/acpi-microvm.c | 9 +
> include/hw/acpi/erst.h | 5 +
> 3 files changed, 23 insertions(+)
>
>
On Fri, 15 Oct 2021, Eric DeVolder wrote:
> This change introduces the public defintions for ACPI ERST.
>
> Signed-off-by: Eric DeVolder
Reviewed-by: Ani Sinha
> ---
> include/hw/acpi/erst.h | 19 +++
> 1 file changed, 19 insertions(+)
> create mode 100644 include/hw/acpi/
The basic SGX patches were merged into Qemu release, the left NUMA
function for SGX should be enabled. The patch1 implemented the SGX NUMA
ACPI to enable NUMA in the SGX guest. Since Libvirt need detailed host
SGX EPC sections info to decide how to allocate EPC sections for SGX NUMA
guest, the SGXE
Add the SGX numa reference command and how to check if
SGX numa is support or not with multiple EPC sections.
Signed-off-by: Yang Zhong
---
docs/system/i386/sgx.rst | 31 +++
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/docs/system/i386/sgx.rst b/doc
Add the MEMORY_DEVICE_INFO_KIND_SGX_EPC case for SGX numa info
with 'info numa' command in the monitor.
Signed-off-by: Yang Zhong
---
hw/core/numa.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 510d096a88..1aa05dcf42 100644
--- a/hw/core/numa.c
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180
Add the SGXEPCSection list into SGXInfo to show the multiple
SGX EPC sections detailed info, not the total size like before.
This patch can enable numa support for 'info sgx' command and
QMP interfaces. The new interfaces show each EPC section info
in one numa node. Libvirt can use QMP interface to
For bare-metal SGX on real hardware, the hardware provides guarantees
SGX state at reboot. For instance, all pages start out uninitialized.
The vepc driver provides a similar guarantee today for freshly-opened
vepc instances, but guests such as Windows expect all pages to be in
uninitialized state
On Apple hosts we can read AppleSMC OSK key directly from host's
SMC and forward this value to QEMU Guest.
Usage:
`-device isa-applesmc,hostosk=on`
Apple licence allows use and run up to two additional copies
or instances of macOS operating within virtual operating system
environments on each App
On 10/22/21 08:01, Alistair Francis wrote:
> From: Alistair Francis
>
> Using a macro for the PLIC configuration doesn't make the code any
> easier to read. Instead it makes it harder to figure out what is going
> on, so let's remove it.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Bin Me
On 10/22/21 12:38, Vladislav Yaroshchuk wrote:
> On Apple hosts we can read AppleSMC OSK key directly from host's
> SMC and forward this value to QEMU Guest.
>
> Usage:
> `-device isa-applesmc,hostosk=on`
>
> Apple licence allows use and run up to two additional copies
> or instances of macOS ope
On Apple hosts we can read AppleSMC OSK key directly from host's
SMC and forward this value to QEMU Guest.
Usage:
`-device isa-applesmc,hostosk=on`
Apple licence allows use and run up to two additional copies
or instances of macOS operating within virtual operating system
environments on each App
On 21/10/2021 23:06, Richard Henderson wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 10/21/21 12:45 PM, matheus.fe...@eldorado.org
Am I using --extra-cflags and --extra-ldflags wrong in the configure call?
I'd like to source build several pre-reqs specific to supporting the qemu
source
build. I'd specifically not like to install neither the qemu or re-req
builds
at the system level. Normally I'd expect the --extra-cflags an
Le 22/10/2021 à 13:10, Vladislav Yaroshchuk a écrit :
On Apple hosts we can read AppleSMC OSK key directly from host's
SMC and forward this value to QEMU Guest.
Usage:
`-device isa-applesmc,hostosk=on`
Apple licence allows use and run up to two additional copies
or instances of macOS operating
Ruinland ChuanTzu Tsai writes:
> On Thu, Oct 21, 2021 at 12:17:47PM -0700, Richard Henderson wrote:
>> On 10/21/21 8:11 AM, Ruinland Chuan-Tzu Tsai wrote:
>> > In this patch, we demonstrate how Andes Performance Extension(c) insn :
>> > bfos and bfoz could be used with Andes CoDense : exec.it.
The following changes since commit 4c127fdbe81d66e7cafed90908d0fd1f6f2a6cd0:
Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into
staging (2021-10-21 09:53:27 -0700)
are available in the Git repository at:
git://git.kraxel.org/qemu tags/seabios-20211022-pull-re
A new seabios release is planned for november.
Update to a master branch snapshot, to
(a) increase test coverage of the changes.
(b) make the delta smaller when updating to the final
release during the qemu 6.2 freeze.
Most noteworthy this fixes the nvme boot regression caused
by adding
Hi Paolo,
On Wed, Oct 13, 2021 at 05:06:06PM +0100, Jean-Philippe Brucker wrote:
> The machine option "default_bus_bypass_iommu" is broken since commit
> d8fb7d0969d5 ("vl: switch -M parsing to keyval"). Fix both machines that
> implement it.
Please could you take a look at these fixes? Another
On 10/13/21 18:06, Jean-Philippe Brucker wrote:
> The machine option "default_bus_bypass_iommu" is broken since commit
> d8fb7d0969d5 ("vl: switch -M parsing to keyval"). Fix both machines that
> implement it.
>
> Resending with Review and Tested tags, no other change since last
> posting:
> https
On Wed, Oct 20, 2021 at 6:23 AM Michael S. Tsirkin wrote:
>
> From: Igor Mammedov
>
> Currently it is not possible to create tests that have KVM as a hard
> requirement on a host that doesn't support KVM for tested target
> binary (modulo going through the trouble of compiling out
> the offending
u.git tags/pull-riscv-to-apply-20211022-2
for you to fetch changes up to 11ec06f9eaedc801ded34c79861367b76ab2b731:
hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
(2021-10-22 23:35:47 +1000)
Fourth RISC-V P
From: Frank Chang
oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-id: 20211007081803.1705
From: Travis Geiselbrecht
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht
Reviewed-by: Alistair Francis
Message-id: 20211009055019.545153-1-trav...@gmail.com
Signed-off-by: Alistair
From: Philipp Tomsich
The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).
This changes the algorithm to:
1. Mask out the high-bit of each bytes
From: Mingwang Li
If default main_mem is used to be registered as the system memory,
other memory cannot be initialized. Therefore, the system memory
should be initialized to the machine->ram, which consists of the
default main_mem and other possible memory required by applications,
such as share
From: Richard Henderson
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-6-richar
From: Richard Henderson
Move the function to cpu_helper.c, as it is large and growing.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-2-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/cpu
From: Alistair Francis
Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.
Signed-off-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Bin Meng
Message-id:
b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.fran
From: Frank Chang
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Al
From: Richard Henderson
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu s
From: Richard Henderson
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-7-richard.hender...@linaro.org
Signed-off-by: A
From: Richard Henderson
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-3-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 8 +---
From: Alistair Francis
Since commit 1a9540d1f1a
("target/riscv: Drop support for ISA spec version 1.09.1")
these definitions are unused, remove them.
Signed-off-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
Message-id:
f4d8a7a035f39c
From: Richard Henderson
In preparation for RV128, consider more than just "w" for
operand size modification. This will be used for the "d"
insns from RV128 as well.
Rename oper_len to get_olen to better match get_xlen.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Rich
From: Richard Henderson
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Messa
From: Richard Henderson
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469
From: Bin Meng
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev s
From: Richard Henderson
In preparation for RV128, replace a simple predicate
with a more versatile test.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-9-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
From: Richard Henderson
The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-11-richard.hender...@linaro.org
Signed-o
From: Richard Henderson
Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-14-richard.hender...@linaro.org
Signed-off-by: Alist
From: Richard Henderson
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Acked-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-12-richard.hender
From: Alistair Francis
The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and
instead use the SiFive PLIC.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.fran...@wdc.com
---
hw/intc/ibex_plic.c |
From: Richard Henderson
Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-15-richard.hender...@linaro.org
From: Bin Meng
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev s
From: Richard Henderson
The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-13-richard.hender...@linaro.org
Signed-off-by:
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.fran...@wdc.com
---
hw/intc/sifive_plic.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --gi
From: Richard Henderson
The position of this read-only field is dependent on the current xlen.
Rather than having to compute that difference in many places, compute
it only on read.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20211020031709.359469-16-richard.hend
From: Bin Meng
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev s
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.fran...@wdc.com
---
hw/intc/sifive_plic.c | 45 +++
1 file changed, 24 insertions(+), 21 deletions(
From: Bin Meng
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev s
From: Bin Meng
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev s
From: Alistair Francis
Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.fran...@wdc.com
---
include/hw/riscv/opentitan.h | 6 +++---
From: Bin Meng
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev s
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.fran...@wdc.com
---
hw/intc/sifive_plic.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/intc/sifive_pli
On Fri, Oct 22, 2021 at 6:38 PM Philippe Mathieu-Daudé wrote:
>
> On 10/22/21 08:01, Alistair Francis wrote:
> > From: Alistair Francis
> >
> > Using a macro for the PLIC configuration doesn't make the code any
> > easier to read. Instead it makes it harder to figure out what is going
> > on, so
On 10/21/21 23:05, Richard Henderson wrote:
> Add two additional helpers, fold_add2_i32 and fold_sub2_i32
> which will not be simple wrappers forever.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 70 +++---
> 1 file changed, 44 inserti
On Fri, Oct 22, 2021 at 2:01 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Add a generic function that can create the PLIC strings.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/riscv/boot.h | 2 ++
> hw/riscv/boot.c | 25 +
> 2 files change
On 10/21/21 23:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 56 --
> 1 file changed, 31 insertions(+), 25 deletions(-)
> +static bool fold_movcond(OptContext *ctx, TCGOp *op)
> +{
> +TCGOpcode opc = o
On 10/21/21 23:05, Richard Henderson wrote:
> Return -1 instead of 2 for failure.
> This us to use comparisons against 0 for all cases.
Typo "This is to use ..."?
>
> Reviewed-by: Luis Pires
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 145 +-
On 10/21/21 23:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 37 +
> 1 file changed, 21 insertions(+), 16 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/21/21 23:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 39 ++-
> 1 file changed, 22 insertions(+), 17 deletions(-)
> +static bool fold_extract2(OptContext *ctx, TCGOp *op)
> +{
> +if (arg_is_const(op->args[1
On 10/21/21 23:05, Richard Henderson wrote:
> This puts the separate mb optimization into the same framework
> as the others. While fold_qemu_{ld,st} are currently identical,
> that won't last as more code gets moved.
>
> Reviewed-by: Luis Pires
> Signed-off-by: Richard Henderson
> ---
> tcg/o
On 10/21/21 23:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 48 ++--
> 1 file changed, 30 insertions(+), 18 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/21/21 23:05, Richard Henderson wrote:
> Reviewed-by: Luis Pires
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 33 +++--
> 1 file changed, 19 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/21/21 23:05, Richard Henderson wrote:
> Rename to fold_multiply2, and handle muls2_i32, mulu2_i64,
> and muls2_i64.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 44 +++-
> 1 file changed, 35 insertions(+), 9 deletions(-)
Reviewed-by
On 10/21/21 23:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 32 ++--
> 1 file changed, 18 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/21/21 23:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 53 +-
> 1 file changed, 31 insertions(+), 22 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/21/21 23:05, Richard Henderson wrote:
> Reviewed-by: Luis Pires
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 23 ++-
> 1 file changed, 14 insertions(+), 9 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/21/21 23:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 25 +++--
> 1 file changed, 15 insertions(+), 10 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Wed, Oct 13, 2021 at 05:06:08PM +0100, Jean-Philippe Brucker wrote:
> Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine
> parameter definitions cannot use underscores, because keyval_dashify()
> transforms them to dashes and the parser doesn't find the parameter.
>
> This a
On 10/21/21 23:04, Richard Henderson wrote:
> Provide what will become a larger context for splitting
> the very large tcg_optimize function.
>
> Reviewed-by: Alex Bennée
> Reviewed-by: Luis Pires
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 77 ++
On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/riscv/microchip_pfsoc.h | 1 -
> hw/riscv/microchip_pfsoc.c | 14 +-
> 2 files changed, 1 insertion(+), 14 deletions(-)
>
Reviewed-by:
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