On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Some architectures publish AT_HWCAP2 as well as AT_HWCAP. Those
> architectures will define ELF_HWCAP2 in their target_arch_elf.h files
> for the value for this process. If it is defined, then publish it.
>
> Signed-off-by: Warner Losh
> Revie
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> To avoid a name clash with FreeBSD's sigqueue data structure in
> signalvar.h, rename sigqueue to qemu_sigqueue. This sturcture
s/sturcture/structure/
> is currently defined, but unused.
>
> Signed-off-by: Warner Losh
> Reviewed-by: Richard
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Similar to the same function in linux-user: this stops all the current tasks.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user/main.c | 9 +
> bsd-user/qemu.h | 1 +
> 2 files changed, 10 insertions(+)
>
>
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> The 'used' field in TaskState is write only. Remove it from TaskState.
>
> Signed-off-by: Warner Losh
> Reviewed-by: Richard Henderson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> bsd-user/main.c | 1 -
> bsd-user/qemu.h | 1 -
> 2 files c
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Add the missing glue to pull in do_freebsd_sysarch to call
> do_freebsd_arch_sysarch. Put it in os-sys.c, which will be used for
> sysctl and sysarch system calls because they are mostly arch specific.
>
> Signed-off-by: Stacey Son
> Signed-of
On Fri, Oct 8, 2021 at 4:25 PM Warner Losh wrote:
>
> Convert DEBUG_MMAP to qemu_log CPU_LOG_PAGE.
>
> Signed-off-by: Warner Losh
> ---
> bsd-user/mmap.c | 53 +
> 1 file changed, 23 insertions(+), 30 deletions(-)
>
> diff --git a/bsd-user/mmap.c b
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> To increase flexibility, only descend into *-user when that is
> configured. This allows *-user to selectively include directories based
> on the host OS which may not exist on all hosts. Adopt Paolo's
> suggestion of checking the configuration
From: Alistair Francis
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..3aa2512d13 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -427
On 10/16/2021 4:22 AM, Eduardo Habkost wrote:
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
added the support of Intel PT by making CPUID[14] of PT as fixed feature
set (from ICX) for any CPU model on any host.
On Sun, Oct 17, 2021 at 3:29 AM Richard Henderson
wrote:
>
> The count zeros instructions require a separate implementation
> for RV32 when TARGET_LONG_BITS == 64.
>
> Reviewed-by: LIU Zhiwei
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/tran
On Mon, Oct 18, 2021 at 8:18 AM Alistair Francis
wrote:
> On Sun, Oct 17, 2021 at 4:59 PM Frank Chang
> wrote:
> >
> > On Sun, Oct 17, 2021 at 8:55 AM Frank Chang
> wrote:
> >>
> >> On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson <
> richard.hender...@linaro.org> wrote:
> >>>
> >>> On 10/16/2
On Sun, Oct 17, 2021 at 3:28 AM Richard Henderson
wrote:
>
> Most shift instructions require a separate implementation
> for RV32 when TARGET_LONG_BITS == 64.
>
> Reviewed-by: LIU Zhiwei
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate
On Fri, Oct 8, 2021 at 4:29 PM Warner Losh wrote:
>
> From: Guy Yur
>
> Switch checks for !(flags & MAP_ANONYMOUS) with checks for fd != -1.
> MAP_STACK and MAP_GUARD both require fd == -1 and don't require mapping
> the fd either. Add analysis from Guy Yur detailing the different cases
> for MAP
On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote:
> On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
> >
> > To increase flexibility, only descend into *-user when that is
> > configured. This allows *-user to selectively include directories based
> > on the host OS which may not exist on all h
From: Alistair Francis
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e..837bea3272 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -
On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson
wrote:
>
> The position of this read-only field is dependent on the
> current cpu width. Rather than having to compute that
> difference in many places, compute it only on read.
>
> Signed-off-by: Richard Henderson
This means that the value repo
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Create dummy signal queueing function so we can start to integrate other
> architectures (at the cost of signals remaining broken) to tame the
> dependency graph a bit and to bring in signals in a more controlled
> fashion. Log unimplemented ev
On Sun, Oct 17, 2021 at 10:29 PM Warner Losh wrote:
>
>
> On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote:
>
>> On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>> >
>> > To increase flexibility, only descend into *-user when that is
>> > configured. This allows *-user to selectively include
On Mon, Oct 18, 2021 at 12:15 PM Frank Chang wrote:
>
> On Mon, Oct 18, 2021 at 8:03 AM Alistair Francis wrote:
>>
>> On Sat, Oct 16, 2021 at 7:08 PM wrote:
>> >
>> > From: Kito Cheng
>> >
>> > Signed-off-by: Kito Cheng
>> > Signed-off-by: Chih-Min Chao
>> > Signed-off-by: Frank Chang
>> > R
On Sun, Oct 17, 2021 at 3:27 AM Richard Henderson
wrote:
>
> The multiply high-part instructions require a separate
> implementation for RV32 when TARGET_LONG_BITS == 64.
>
> Reviewed-by: LIU Zhiwei
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/ris
On Sun, Oct 17, 2021 at 04:58:37PM +0200, Philippe Mathieu-Daudé wrote:
> On 10/16/21 09:27, Paolo Bonzini wrote:
> > On 16/10/21 04:04, Richard Henderson wrote:
> >> I've seen a lot of failures on this job recently, and they're all
> >> timeouts cloning the git submodules. Would it be better to m
On Mon, Oct 18, 2021 at 12:02 AM Warner Losh wrote:
>
>
>
> On Sun, Oct 17, 2021 at 10:29 PM Warner Losh wrote:
>>
>>
>>
>> On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote:
>>>
>>> On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>>> >
>>> > To increase flexibility, only descend into *-user w
On 10/17/21 9:52 PM, Alistair Francis wrote:
On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson
wrote:
The position of this read-only field is dependent on the
current cpu width. Rather than having to compute that
difference in many places, compute it only on read.
Signed-off-by: Richard Hend
On 10/18/2021 11:46 AM, Xiaoyao Li wrote:
On 10/16/2021 4:22 AM, Eduardo Habkost wrote:
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
added the support of Intel PT by making CPUID[14] of PT as fixed feature
se
On 10/17/21 3:55 PM, Alistair Francis wrote:
On Fri, Oct 15, 2021 at 5:50 PM wrote:
From: Frank Chang
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv
On Mon, Oct 18, 2021 at 3:31 PM Richard Henderson
wrote:
>
> On 10/17/21 9:52 PM, Alistair Francis wrote:
> > On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson
> > wrote:
> >>
> >> The position of this read-only field is dependent on the
> >> current cpu width. Rather than having to compute that
On Fri, Oct 15, 2021 at 6:04 PM wrote:
>
> From: Frank Chang
>
> Vector AMOs are removed from standard vector extensions. Will be added
> later as separate Zvamo extension, but will need a different encoding
> from earlier proposal.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
On Fri, Oct 15, 2021 at 6:22 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/helper.h | 2 +-
> target/riscv/insn32.decode | 2 +-
> target/riscv/insn_
On Fri, Oct 15, 2021 at 6:03 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/helper.h | 2 +-
> target/riscv/insn32.decode | 2 +-
> target/riscv/insn_
On Fri, Oct 15, 2021 at 6:25 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 10 --
> 2 files
On 10/17/21 4:59 PM, Alistair Francis wrote:
+#if defined(TARGET_RISCV64)
+/* 16 bits -> 64 bits */
+tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]);
+#else
+/* 16 bits -> 32 bits */
+tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
+tcg_gen_ext16s_tl(dest, dest);
+#endif
Can we use is
On Fri, Oct 15, 2021 at 6:06 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 6 +++---
> target/riscv/insn_trans/trans_rvv.c.inc | 5 -
> target/risc
On Fri, Oct 15, 2021 at 6:08 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn3
On Fri, Oct 15, 2021 at 5:48 PM wrote:
>
> From: Frank Chang
>
> This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>
> RVV v1.0 spec is now fronzen for public review:
> https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
>
> The port is available here:
> https://github.co
On Fri, Oct 15, 2021 at 5:50 PM wrote:
>
> From: Frank Chang
>
> TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> not shift as well so these bits may overlap with each other when
> rvv is enabled.
>
> Signed-off-by: Fran
On 10/17/21 10:38 PM, Alistair Francis wrote:
Do we get much of an advantage from this though? To me it seems
confusing that the mstatus register doesn't actually contain the
latest value (for example when debugging QEMU and adding my own
printf's).
(1) We have at least 3 places that need to ch
On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis
wrote:
> On Fri, Oct 15, 2021 at 5:48 PM wrote:
> >
> > From: Frank Chang
> >
> > This patchset implements the vector extension v1.0 for RISC-V on QEMU.
> >
> > RVV v1.0 spec is now fronzen for public review:
> > https://github.com/riscv/riscv-v-
On Sat, Oct 16, 2021 at 7:09 PM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/fpu_helper.c | 67 +
> targ
On Mon, Oct 18, 2021 at 4:09 PM Frank Chang wrote:
>
> On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis wrote:
>>
>> On Fri, Oct 15, 2021 at 5:48 PM wrote:
>> >
>> > From: Frank Chang
>> >
>> > This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>> >
>> > RVV v1.0 spec is now
On Mon, Oct 18, 2021 at 2:12 PM Alistair Francis
wrote:
> On Mon, Oct 18, 2021 at 4:09 PM Frank Chang
> wrote:
> >
> > On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis
> wrote:
> >>
> >> On Fri, Oct 15, 2021 at 5:48 PM wrote:
> >> >
> >> > From: Frank Chang
> >> >
> >> > This patchset impleme
Hi,
> > I can do that but waiting for a decision on how to proceed. Will Gerd
> > take my first series this is based on as is then this should be a
> > separate series doing the clean up using pci_get_function_0 or should
> > these two series be merged? I'd also squash setting user_creatable =
>
On 17/10/2021 00.56, Brad Smith wrote:
tests/vm: update openbsd to release 7.0
Signed-off-by: Brad Smith
---
tests/vm/openbsd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/vm/openbsd b/tests/vm/openbsd
index c4c78a80f1..abf510e117 100755
--- a/tests/vm/openbsd
On 10/18/2021 2:28 AM, Thomas Huth wrote:
On 17/10/2021 00.56, Brad Smith wrote:
tests/vm: update openbsd to release 7.0
Signed-off-by: Brad Smith
---
tests/vm/openbsd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/vm/openbsd b/tests/vm/openbsd
index c4c78a80f
On Mon, 18 Oct 2021 10:17:45 +0800
Bin Meng wrote:
> Hi Igor,
>
> On Fri, Oct 15, 2021 at 8:59 PM Igor Mammedov wrote:
> >
> > On Fri, 15 Oct 2021 17:25:01 +0800
> > Bin Meng wrote:
> >
> > > On Fri, Oct 15, 2021 at 4:52 PM limingwang (A)
> > > wrote:
> > > >
> > > >
> > > > On Wed, Oct
On 30/01/2021 14.16, P J P wrote:
From: Prasad J Pandit
While activating device in vmxnet3_acticate_device(), it does not
validate guest supplied configuration values against predefined
minimum - maximum limits. This may lead to integer overflow or
OOB access issues. Add checks to avoid it.
Fi
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