On Fri, Oct 15, 2021 at 6:06 PM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 6 +++---
> target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++-
> target/riscv/vector_helper.c | 4 ----
> 3 files changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 4df2aa9cddc..d139c0aade7 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -629,9 +629,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
> vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
> vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
> vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
> -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
> -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
> -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
> +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
> +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
> +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
> viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
> vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
> vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5376adca60c..538a32a605a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2730,7 +2730,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
> #define GEN_M_TRANS(NAME) \
> static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> { \
> - if (vext_check_isa_ill(s)) { \
> + if (require_rvv(s) && \
> + vext_check_isa_ill(s) && \
> + require_vm(a->vm, a->rd) && \
> + (a->rd != a->rs2)) { \
> uint32_t data = 0; \
> gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
> TCGLabel *over = gen_new_label(); \
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index f97783acf05..b0dc971a860 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4260,7 +4260,6 @@ enum set_mask_type {
> static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
> uint32_t desc, enum set_mask_type type)
> {
> - uint32_t vlmax = env_archcpu(env)->cfg.vlen;
> uint32_t vm = vext_vm(desc);
> uint32_t vl = env->vl;
> int i;
> @@ -4290,9 +4289,6 @@ static void vmsetm(void *vd, void *v0, void *vs2,
> CPURISCVState *env,
> }
> }
> }
> - for (; i < vlmax; i++) {
> - vext_set_elem_mask(vd, i, 0);
> - }
> }
>
> void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
> --
> 2.25.1
>
>
