[PATCH 1/2] hw/misc/bcm2835_property: Fix framebuffer with recent RPi kernels

The framebuffer driver fails to initialize with recent Raspberry Pi kernels, such as the ones shipped in the current RaspiOS images (with the out of tree bcm2708_fb.c driver) The reason is that this driver uses a new firmware call to query the number of displays, and the fallback when this call fa

[PATCH 2/2] hw/misc/bcm2835_property: Add dummy Get/Set GPIO virt buf messages

Without these the RaspiOS kernel tries to ioremap some bogus address and dumps a backtrace in the console at boot. These work around it. The virt-gpio driver still fails to initialize but much more cleanly Signed-off-by: Benjamin Herrenschmidt --- hw/misc/bcm2835_property.c | 7 +++ 1 file

Re: [RFC PATCH 2/5] target/i386: Introduce FeatureWordInfo for Intel PT CPUID leaf 0xD

On 10/16/2021 12:04 AM, Eduardo Habkost wrote: Hi, Apologies for the delay. Comments below: On Thu, Sep 09, 2021 at 10:41:47PM +0800, Xiaoyao Li wrote: CPUID leaf 0x14 subleaf 0x0 and 0x1 enumerate the resource and capability of Intel PT. Introduce FeatureWord FEAT_14_0_EBX, FEAT_14_1_EAX an

Re: [PATCH 3/8] q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs

On 15/10/2021 07:31, Laurent Vivier wrote: Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : In order to allow dynamic routing of IRQs to different IRQ levels on the CPU depending upon port B bit 6, use GLUE IRQ numbers and map them to the the corresponding CPU IRQ level accordingly. Signed-of

Re: [PATCH 8/8] q800: add NMI handler

On 16/10/2021 18:09, Laurent Vivier wrote: Le 15/10/2021 à 22:12, Mark Cave-Ayland a écrit : On 15/10/2021 09:40, Laurent Vivier wrote: Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : This allows the programmer's switch to be triggered via the monitor for debugging purposes. Since the CPU

Re: [PATCH 6/8] q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode

On 16/10/2021 19:08, Laurent Vivier wrote: Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : When the hardware is operating in classic mode the SONIC on-board Ethernet IRQ is routed to nubus IRQ 9 instead of directly to the CPU at level 3. This does not affect the framebuffer which although it

Re: [RFC PATCH 3/5] target/i386: Enable host pass through of Intel PT

On 10/16/2021 4:22 AM, Eduardo Habkost wrote: On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote: commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support") added the support of Intel PT by making CPUID[14] of PT as fixed feature set (from ICX) for any CPU model on any host.

Re: [PATCH 3/8] q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs

Le 17/10/2021 à 11:40, Mark Cave-Ayland a écrit : > On 15/10/2021 07:31, Laurent Vivier wrote: > >> Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit : >>> In order to allow dynamic routing of IRQs to different IRQ levels on the CPU >>> depending upon port B bit 6, use GLUE IRQ numbers and map them

Re: gitlab build-edk2 failures

On 10/16/21 09:27, Paolo Bonzini wrote: > On 16/10/21 04:04, Richard Henderson wrote: >> I've seen a lot of failures on this job recently, and they're all >> timeouts cloning the git submodules.  Would it be better to mirror >> these to gitlab? >> > > They're not timeouts, they're issues with edk2

Re: [PATCH 1/2] hw/misc/bcm2835_property: Fix framebuffer with recent RPi kernels

Hi Benjamin, On 10/17/21 09:48, Benjamin Herrenschmidt wrote: > The framebuffer driver fails to initialize with recent Raspberry Pi > kernels, such as the ones shipped in the current RaspiOS images > (with the out of tree bcm2708_fb.c driver) Which particular version? > > The reason is that thi

Re: [PATCH] via-ide: Set user_creatable to false

On 10/15/21 11:16, BALATON Zoltan wrote: > This model only works as a function of the via superio chip not as a > standalone PCI device. > > Signed-off-by: BALATON Zoltan > --- > This should be before the last patch changing via-ide or squshed into > it. And similar to usb part but there I need t

Re: [PATCH 2/4] vt82c686: Add a method to VIA_ISA to raise ISA interrupts

On 10/15/21 03:06, BALATON Zoltan wrote: > Other functions in the VT82xx chips need to raise ISA interrupts. Keep > a reference to them in the device state and add via_isa_set_irq() to > allow setting their state. > > Signed-off-by: BALATON Zoltan > --- > hw/isa/vt82c686.c | 10 +

Re: [PATCH 1/4] vt82c686: Move common code to via_isa_realize

On 10/15/21 03:06, BALATON Zoltan wrote: > The vt82c686b_realize and vt8231_realize methods are almost identical, > factor out the common parts to a via_isa_realize function to avoid > code duplication. > > Signed-off-by: BALATON Zoltan > --- > hw/isa/vt82c686.c | 67

Re: [PATCH 3/4] hw/usb/vt82c686-uhci-pci: Avoid using isa_get_irq()

On 10/15/21 03:06, BALATON Zoltan wrote: > Use via_isa_set_irq() which better encapsulates irq handling in the > vt82xx model and avoids using isa_get_irq() that has a comment saying > it should not be used. > > Signed-off-by: BALATON Zoltan > --- > hw/usb/vt82c686-uhci-pci.c | 3 ++- > 1 file c

Re: [PATCH 4/4] via-ide: Avoid using isa_get_irq()

On 10/15/21 03:06, BALATON Zoltan wrote: > Use via_isa_set_irq() which better encapsulates irq handling in the > vt82xx model and avoids using isa_get_irq() that has a comment saying > it should not be used. > > Signed-off-by: BALATON Zoltan > --- > hw/ide/via.c | 4 ++-- > 1 file changed, 2 ins

Re: [PATCH V5] block/rbd: implement bdrv_co_block_status

On Tue, Oct 12, 2021 at 5:22 PM Peter Lieven wrote: > > the qemu rbd driver currently lacks support for bdrv_co_block_status. > This results mainly in incorrect progress during block operations (e.g. > qemu-img convert with an rbd image as source). > > This patch utilizes the rbd_diff_iterate2 cal

Re: [PATCH 8/8] q800: add NMI handler

Le 17/10/2021 à 12:00, Mark Cave-Ayland a écrit : ... > I've just tried this on Linux, and it seems to work okay although I get > several copies of the > register dump on the console for a single invocation of "info nmi" e.g. > > [    4.61] Non-Maskable Interrupt > [    4.61] Modules link

Re: [PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

Hi Richard, Thanks for the review. >Merge error. fixed >You might as well place the function correctly in the previous patch. >Drop the silly alignment of parameters. fixed > int priv = flags & TB_FLAGS_PRIV_MMU_MASK; fixed >priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; fixed сб, 16 окт. 2021 г.

Re: [PATCH v13 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Hi, Sorry, my bad, got it wrong. Fixed now. Thanks! сб, 16 окт. 2021 г. в 02:49, Richard Henderson : > On 10/15/21 12:29 PM, Alexey Baturo wrote: > > Signed-off-by: Alexey Baturo > > Reviewed-by: Richard Henderson > > Reviewed-by: Alistair Francis > > --- > > target/riscv/insn_trans/trans_

[PATCH v14 1/8] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..3f28dc5f3a 100644 --- a/target/riscv/cpu.h +++

[PATCH v14 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..1a3767804a 100644 --- a/target/riscv/cpu_bits.

[PATCH v14 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 75e8b8ca83..7f9dde70b7 100644 --- a/target/riscv/cpu.c ++

[PATCH v14 0/8] RISC-V Pointer Masking implementation

v13: Rebased QEMU and addressed Richard's comment. v12: Updated function for adjusting address with pointer masking to allocate and use temp register. v11: Addressed a few style issues Alistair mentioned in the previous review. If this patch series would be accepted, I think my further attentio

[PATCH v14 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/r

[PATCH v14 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 285 + 3 files changed, 298 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..75e8b8ca83 100644 --- a/targ

[PATCH v14 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 20 target/riscv/translate.c | 39 +-- 2 files changed, 57 insertions(+), 2 deletio

[PATCH v14 8/8] [RISCV_PM] Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7f9dde70b7..fb08c0ffb8 100644 --- a/target/riscv/cpu.c ++

[PATCH v14 4/8] [RISCV_PM] Add J extension state description

Signed-off-by: Alexey Baturo --- target/riscv/machine.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 16a08302da..4d99880797 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -84,6 +84,14 @@

Re: [PATCH 4/4] via-ide: Avoid using isa_get_irq()

On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/15/21 03:06, BALATON Zoltan wrote: Use via_isa_set_irq() which better encapsulates irq handling in the vt82xx model and avoids using isa_get_irq() that has a comment saying it should not be used. Signed-off-by: BALATON Zoltan --- hw/ide

Re: [PATCH 4/4] via-ide: Avoid using isa_get_irq()

On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/15/21 03:06, BALATON Zoltan wrote: Use via_isa_set_irq() which better encapsulates irq handling in the vt82xx model and avoids using isa_get_irq() that has a comment saying it should not be used. Signed-off-by: BALATON Zoltan --- hw/ide

Re: [PATCH 4/4] via-ide: Avoid using isa_get_irq()

On 10/17/21 21:39, BALATON Zoltan wrote: > On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote: >> On 10/15/21 03:06, BALATON Zoltan wrote: >>> Use via_isa_set_irq() which better encapsulates irq handling in the >>> vt82xx model and avoids using isa_get_irq() that has a comment saying >>> it should n

Re: [PATCH 4/4] via-ide: Avoid using isa_get_irq()

On 10/17/21 20:44, BALATON Zoltan wrote: > On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote: >> On 10/15/21 03:06, BALATON Zoltan wrote: >>> Use via_isa_set_irq() which better encapsulates irq handling in the >>> vt82xx model and avoids using isa_get_irq() that has a comment saying >>> it should n

Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS

Hello Zhiwei and Alistair, I noticed this patch did not make it upstream, contrarily to a couple other patches I submitted around the same time. Is there something else needed from my side to push this forward? Best, José On Wed, 2 Jun 2021 at 20:14, Jose Martins wrote: > > Hello Zhiwei and Ali

Re: [PATCH 4/4] via-ide: Avoid using isa_get_irq()

On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/17/21 21:39, BALATON Zoltan wrote: On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/15/21 03:06, BALATON Zoltan wrote: Use via_isa_set_irq() which better encapsulates irq handling in the vt82xx model and avoids using isa_get_irq(

Re: [PATCH 4/4] via-ide: Avoid using isa_get_irq()

On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/17/21 20:44, BALATON Zoltan wrote: On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/15/21 03:06, BALATON Zoltan wrote: Use via_isa_set_irq() which better encapsulates irq handling in the vt82xx model and avoids using isa_get_irq(

[PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6

Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04, MULT and MULTU opcodes: The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS32 architecture. In Release 6 of the MIPS Architecture, accumulato

[PULL 03/17] hw/mips/boston: Allow loading elf kernel and dtb

From: Jiaxun Yang ELF kernel allows us debugging much easier with DWARF symbols. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé [PMD: Fix coding style] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211002184539.169-3-jiaxun.y...@flygoat.com> --- hw/mips/boston.c | 36 +

[PULL 02/17] hw/mips/boston: Massage memory map information

From: Jiaxun Yang Use memmap array to uinfy address of memory map. That would allow us reuse address information for FDT generation. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé [PMD: Use local 'regaddr' in gen_firmware(), fix coding style] Signed-off-by: Philippe Mathieu-Dau

[PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df()

Data Format is a 2-bit constant value. Avoid using a TCG temporary by moving it to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211003175743.3738710-3-f4...@amsat.org> --- target/mips/tcg/msa_translate.c | 3 +-- 1 file changed, 1 insert

[PULL 00/17] MIPS patches for 2021-10-18

The following changes since commit c148a0572130ff485cd2249fbdd1a3260d5e10a4: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211016' into staging (2021-10-16 11:16:28 -0700) are available in the Git repository at: https://github.com/philmd/qemu.git tags/mips-20211018 for you to f

[PULL 04/17] hw/mips/boston: Add FDT generator

From: Jiaxun Yang Generate FDT on our own if no dtb argument supplied. Avoid introducing unused device in FDT with user supplied dtb. Signed-off-by: Jiaxun Yang [PMD: Fix coding style] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211002184539.169-4-jiaxun.y...@flygoat.com> --- hw/mips

[PULL 05/17] target/mips: Remove unused register from MSA 2R/2RF instruction format

Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions") and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added the MSA 2R/2RF instructions. However these instructions don't use any target vector register, so remove the unused TCG temporaries. Reviewed-by: Richard He

[PULL 11/17] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()

The offset is constant and read-only: move it to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211003175743.3738710-9-f4...@amsat.org> --- target/mips/tcg/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/

[PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5()

We already use sextract32(), use extract32() for completeness instead of open-coding it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211003175743.3738710-7-f4...@amsat.org> --- target/mips/tcg/msa_translate.c | 11 --- 1 file changed, 4 insertions

[PULL 07/17] target/mips: Use tcg_constant_i32() in gen_msa_2rf()

Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211003175743.3738710-4-f4...@amsat.org> --- target/mips/tcg/msa_translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff -

[PULL 13/17] target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()

Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions"), the 'v2_t' TCG temporary has never been used. Remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211014224551.2204949-1-f4...@amsat.org>

[PULL 09/17] target/mips: Use tcg_constant_i32() in gen_msa_3rf()

Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211003175743.3738710-6-f4...@amsat.org> --- target/mips/tcg/msa_translate.c | 23 ++- 1 file changed, 14 insertions(+),

[PULL 17/17] via-ide: Avoid using isa_get_irq()

From: BALATON Zoltan Use via_isa_set_irq() which better encapsulates irq handling in the vt82xx model and avoids using isa_get_irq() that has a comment saying it should not be used. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: <26cb1848c9fc0360df7a57c2c9ba5e03

[PULL 15/17] vt82c686: Move common code to via_isa_realize

From: BALATON Zoltan The vt82c686b_realize and vt8231_realize methods are almost identical, factor out the common parts to a via_isa_realize function to avoid code duplication. Signed-off-by: BALATON Zoltan Reviewed-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Message-Id: <7cb7a16ff4d

[PULL 12/17] target/mips: Fix DEXTRV_S.H DSP opcode

While for the DEXTR_S.H opcode: "The shift argument is provided in the instruction." For the DEXTRV_S.H opcode we have: "The five least-significant bits of register rs provide the shift argument, interpreted as a five-bit unsigned integer; the remaining bits in rs are ignored." While

[PULL 08/17] target/mips: Use tcg_constant_i32() in gen_msa_2r()

Avoid using a TCG temporary by moving Data Format to the constant pool. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211003175743.3738710-5-f4...@amsat.org> --- target/mips/tcg/msa_translate.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) dif

Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh

On Fri, Oct 15, 2021 at 5:50 PM wrote: > > From: Frank Chang > > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in > commit: c445593, but other TB_FLAGS bits for rvv and rvh were > not shift as well so these bits may overlap with each other when > rvv is enabled. > > Signed-off-by: Fran

[PULL 14/17] via-ide: Set user_creatable to false

From: BALATON Zoltan This model only works as a function of the via superio chip not as a standalone PCI device. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211015092159.3e863748...@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/ide/via.c |

[PULL 16/17] vt82c686: Add a method to VIA_ISA to raise ISA interrupts

From: BALATON Zoltan Other functions in the VT82xx chips need to raise ISA interrupts. Keep a reference to them in the device state and add via_isa_set_irq() to allow setting their state. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Message-Id: <

Re: [PATCH v3] hw/riscv: virt: Use machine->ram as the system memory

On Sat, Oct 16, 2021 at 1:09 PM MingWang Li wrote: > > From: Mingwang Li > > If default main_mem is used to be registered as the system memory, > other memory cannot be initialized. Therefore, the system memory > should be initialized to the machine->ram, which consists of the > default main_mem

Re: [PATCH v3 2/6] target/riscv: zfh: half-precision computational

On Sat, Oct 16, 2021 at 7:08 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/fpu_helper.c | 86 ++

Re: [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move

On Sat, Oct 16, 2021 at 7:09 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson > --- > target/riscv/fpu_helper.c | 67 + > target/riscv/helper.h |

Re: [PATCH v3 4/6] target/riscv: zfh: half-precision floating-point compare

On Sat, Oct 16, 2021 at 7:12 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/fpu_helper.c | 21 +++

Re: [PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify

On Sat, Oct 16, 2021 at 7:11 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/fpu_helper.c | 6 ++ > t

Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store

On Sat, Oct 16, 2021 at 7:08 PM wrote: > > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > Reviewed-by: Richard Henderson > --- > target/riscv/cpu.c| 1 + > target/riscv/cpu.h| 1 +

Re: [PATCH v3 6/6] target/riscv: zfh: implement zfhmin extension

On Sat, Oct 16, 2021 at 7:13 PM wrote: > > From: Frank Chang > > Zfhmin extension is a subset of Zfh extension, consisting only of data > transfer and conversion instructions. > > If enabled, only the following instructions from Zfh extension are > included: > * flh, fsh, fmv.x.h, fmv.h.x, fcvt

Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

On Sun, Oct 17, 2021 at 4:59 PM Frank Chang wrote: > > On Sun, Oct 17, 2021 at 8:55 AM Frank Chang wrote: >> >> On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson >> wrote: >>> >>> On 10/16/21 1:52 AM, Frank Chang wrote: >>> > On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson >>> > >> >

Re: [PATCH 1/2] hw/misc/bcm2835_property: Fix framebuffer with recent RPi kernels

On Sun, 2021-10-17 at 17:08 +0200, Philippe Mathieu-Daudé wrote: > Hi Benjamin, > > On 10/17/21 09:48, Benjamin Herrenschmidt wrote: > > The framebuffer driver fails to initialize with recent Raspberry Pi > > kernels, such as the ones shipped in the current RaspiOS images > > (with the out of tree

[PATCH v4 01/15] target/ppc: add MMCR0 PMCC bits to hflags

We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+ emulation and following PowerISA v3.1. This requires several PMU related registers to be exposed to userspace (problem state). PowerISA v3.1 dictates that the PMCC bits of the MMCR0 register controls the level of access of the

[PATCH v4 04/15] target/ppc: adding user read/write functions for PMCs

Problem state needs to be able to read and write the PMU counters, otherwise it won't be aware of any sampling result that the PMU produces after a Perf run. This patch does that in a similar fashion as already done in the previous patches. PMCs 5 and 6 have a special condition, aside from the con

[PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction

This new version presents drastic design changes across all areas, most of them based on the feedback received in v3. - TCG reviewers: for people looking to review only TCG related changes, here's a summmary of where are the TCG code in the series: * Patches that have a lot of TCG/translation cha

[PATCH v4 03/15] target/ppc: add user read/write functions for MMCR2

Similar to the previous patch, let's add problem state read/write access to the MMCR2 SPR, which is also a group A PMU SPR that needs to be filtered to be read/written by userspace. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 9 +++ target/ppc/cpu_init.c

[PATCH v4 06/15] target/ppc: initialize PMUEvents on MMCR1 write

The value of MMCR1 determines the events that are going to be sampled by the programmable counters (PMCs 1-4). PMCs 5 and 6 are always counting instructions and cycles respectively and aren't affected by MMCR1. This patch adds a helper to initialize PMCs 1-4 PMUEvents when writing the MMCR1 regist

[PATCH v4 02/15] target/ppc: add user read/write functions for MMCR0

From: Gustavo Romero Userspace need access to PMU SPRs to be able to operate the PMU. One of such SPRs is MMCR0. MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU register. This class of registers has common read/write rules that are governed by MMCR0 PMCC bits. MMCR0 is also

[PATCH v4 07/15] target/ppc: PMU basic cycle count for pseries TCG

This patch adds the barebones of the PMU logic by enabling cycle counting. The overall logic goes as follows: - a helper is added to control the PMU state on each MMCR0 write. This allows for the PMU to start/stop as the frozen counter bit (MMCR0_FC) is cleared or set; - MMCR0 reg initial value i

[PATCH v4 05/15] target/ppc: introduce PMU events

This patch starts an IBM Power8+ compatible PMU implementation by adding the representation of PMU events that we are going to sample, PMUEvent. This struct represents a Perf event, determined by the PMUEventType enum, that is being sampled by a specific counter 'sprn'. PMUEvent also contains an ov

[PATCH v4 09/15] target/ppc: enable PMU instruction count

The PMU is already counting cycles by calculating time elapsed in nanoseconds. Counting instructions is a different matter and requires another approach. This patch adds the capability of counting completed instructions (Perf event PM_INST_CMPL) by counting the amount of instructions translated in

[PATCH v4 08/15] target/ppc: enable PMU counter overflow with cycle events

The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative conditions are enabled. This means that if the counter value overflows (i.e. exceeds 0x8000) a performance monitor alert will occur. This alert can trigger

[PATCH v4 10/15] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event

PM_RUN_INST_CMPL, instructions completed with the run latch set, is the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA. Implement it by checking for the CTRL RUN bit before incrementing the counter. To make this work properly we also need to force a new translation block each time SPR

[PATCH v4 12/15] target/ppc/power8-pmu.c: handle overflow bits when PMU is running

Up until this moment we were assuming that the counter negative enabled bits, PMC1CE and PMCjCE, would never be changed when the PMU is already started. Turns out that there is no such restriction in the PowerISA v3.1, and software can enable/disable overflow conditions of the counters at any time

[PATCH v4 11/15] target/ppc: PMU: handle setting of PMCs while running

The initial PMU support were made under the assumption that the counters would be set before running the PMU and read after either freezing the PMU manually or via a performance monitor alert. Turns out that some EBB powerpc kernel tests set the counters after unfreezing the counters. Setting a PM

[PATCH v4 13/15] PPC64/TCG: Implement 'rfebb' instruction

An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The followin

[PATCH v4 14/15] target/ppc: PMU Event-Based exception support

From: Gustavo Romero Following up the rfebb implementation, this patch adds the EBB exception support that are triggered by Performance Monitor alerts. This exception occurs when an enabled PMU condition or event happens and both MMCR0_EBE and BESCR_PME are set. The supported PM alerts will cons

Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS

On Mon, Oct 18, 2021 at 6:30 AM Jose Martins wrote: > > Hello Zhiwei and Alistair, > > I noticed this patch did not make it upstream, contrarily to a couple > other patches I submitted around the same time. Is there something > else needed from my side to push this forward? >From your last respon

[PATCH v4 15/15] target/ppc/excp_helper.c: EBB handling adjustments

The current logic is only considering event-based exceptions triggered by the performance monitor. This is true now, but we might want to add support for external event-based exceptions in the future. Let's make it a bit easier to do so by adding the bit logic that would happen in case we were dea

[PATCH] via-ide: Avoid expensive operations in irq handler

Cache the pointer to PCI function 0 (ISA bridge, that this IDE device has to use for IRQs) in the PCIIDEState and pass that as the opaque data for the interrupt handler to eliminate both the need to look up function 0 at every interrupt and also a QOM type cast of the opaque pointer as that's also

Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store

On Mon, Oct 18, 2021 at 8:03 AM Alistair Francis wrote: > On Sat, Oct 16, 2021 at 7:08 PM wrote: > > > > From: Kito Cheng > > > > Signed-off-by: Kito Cheng > > Signed-off-by: Chih-Min Chao > > Signed-off-by: Frank Chang > > Reviewed-by: Richard Henderson > > --- > > target/riscv/cpu.c

Re: [PATCH v2] hw/riscv: virt: bugfix the memory-backend-file command is invalid

Hi Igor, On Fri, Oct 15, 2021 at 8:59 PM Igor Mammedov wrote: > > On Fri, 15 Oct 2021 17:25:01 +0800 > Bin Meng wrote: > > > On Fri, Oct 15, 2021 at 4:52 PM limingwang (A) > > wrote: > > > > > > > > > On Wed, Oct 13, 2021 at 22:41 PM Bin Meng wrote: > > > > > > > > On Tue, Oct 12, 2021 at 9:4

[PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build

From: Alistair Francis Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis --- include/hw/riscv/opentitan.h | 6 +++--- hw/riscv/opentitan.c | 22 +- 2 files changed, 20 insertions(+), 8 deletions(-) diff -

[PATCH v1 2/9] hw/intc: Remove the Ibex PLIC

From: Alistair Francis The Ibex PLIC is now spec complient. Let's remove the Ibex PLIC and instead use the SiFive PLIC. Signed-off-by: Alistair Francis --- hw/intc/ibex_plic.c | 307 hw/intc/meson.build | 1 - 2 files changed, 308 deletions(-) de

[PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index d77a5ced23..877e76877c 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic

[PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 13 + 1 file changed, 13 insertions(+) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 877e76877c..5444368ad4 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -355,6

[PATCH v1 3/9] hw/intc: sifive_plic: Move the properties

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 9ba36dc0b3..f0e2799efc 100644 --- a/hw/intc/sifive_plic.c +++

[PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 45 +++ 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index f0e2799efc..d77a5ced23 100644 --- a/hw/intc/sifi

[PATCH v1 9/9] hw/intc: sifive_plic: Cleanup remaining functions

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 109 +- 1 file changed, 22 insertions(+), 87 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index d73503cea4..3f56223554 100644 --- a/hw/intc/sifi

[PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 82 +-- 1 file changed, 33 insertions(+), 49 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 5444368ad4..49e566a76f 100644 --- a/hw/intc/sifi

[PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function

From: Alistair Francis Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 55 +-- 1 file changed, 11 insertions(+), 44 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 49e566a76f..d73503cea4 100644 --- a/hw/intc/sifi

Re: [PATCH] target/ppc: Filter mtmsr[d] input before setting MSR

On Fri, Oct 15, 2021 at 03:19:40PM -0300, matheus.fe...@eldorado.org.br wrote: > From: Matheus Ferst > > PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or > MSR[LE]", but the current code only filters the GPR-provided value if > L=1. This behavior caused some problems in Fr

Re: [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction

On Sun, Oct 17, 2021 at 10:01:18PM -0300, Daniel Henrique Barboza wrote: > This new version presents drastic design changes across all areas, most > of them based on the feedback received in v3. > > - TCG reviewers: for people looking to review only TCG related changes, > here's a summmary of wher

Re: [PATCH v2 04/15] bsd-user: TARGET_RESET define is unused, remove it

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-user/i386/target_arch_cpu.h | 2 -- > bsd-user/x86_64/target_arch_cpu.h | 2 -- > 2 files changed, 4 deletions(-) > > diff --git

Re: [PATCH v2 05/15] bsd-user: export get_errno and is_error from syscall.c

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Make get_errno and is_error global so files other than syscall.c can use > them. > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-user/qemu.h| 4 > bsd-user/syscall.

Re: [PATCH v2 07/15] bsd-user: move TARGET_MC_GET_CLEAR_RET to target_os_signal.h

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > Move TARGET_MC_GET_CLEAR_RET to freebsd/target_os_signal.h since it's > architecture agnostic on FreeBSD. > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-user/freebsd/target_

Re: [PATCH v2 08/15] bsd-user/target_os_elf.h: Remove fallback ELF_HWCAP and reorder

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > All architectures have a ELF_HWCAP, so remove the fallback ifdef. > Place ELF_HWCAP in the same order as on native FreeBSD. > > Signed-off-by: Warner Losh > Reviewed-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé > --- > bsd-us

Re: [PATCH v2 06/15] bsd-user/errno_defs.h: Add internal error numbers

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > From: Stacey Son > > To emulate signals and interrupted system calls, we need to have the > same mechanisms we have in the kernel, including these errno values. > > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > Reviewed-by: Richar

Re: [PATCH v2 12/15] bsd-user/sysarch: Move to using do_freebsd_arch_sysarch interface

On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote: > > do_freebsd_arch_sysarch() exists in $ARCH/target_arch_sysarch.h for x86. > Call it from do_freebsd_sysarch() and remove the mostly duplicate > version in syscall.c. Future changes will move it to os-sys.c and > support other architectures. > >

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