On Sat, Oct 16, 2021 at 7:12 PM <frank.ch...@sifive.com> wrote:
>
> From: Kito Cheng <kito.ch...@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.ch...@sifive.com>
> Signed-off-by: Chih-Min Chao <chihmin.c...@sifive.com>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/fpu_helper.c | 21 +++++++++++++
> target/riscv/helper.h | 3 ++
> target/riscv/insn32.decode | 3 ++
> target/riscv/insn_trans/trans_rvzfh.c.inc | 37 +++++++++++++++++++++++
> 4 files changed, 64 insertions(+)
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index 2ed9b03193c..ec2009ee65b 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -461,6 +461,27 @@ uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1)
> return nanbox_h(float16_sqrt(frs1, &env->fp_status));
> }
>
> +target_ulong helper_fle_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> +{
> + float16 frs1 = check_nanbox_h(rs1);
> + float16 frs2 = check_nanbox_h(rs2);
> + return float16_le(frs1, frs2, &env->fp_status);
> +}
> +
> +target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> +{
> + float16 frs1 = check_nanbox_h(rs1);
> + float16 frs2 = check_nanbox_h(rs2);
> + return float16_lt(frs1, frs2, &env->fp_status);
> +}
> +
> +target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> +{
> + float16 frs1 = check_nanbox_h(rs1);
> + float16 frs2 = check_nanbox_h(rs2);
> + return float16_eq_quiet(frs1, frs2, &env->fp_status);
> +}
> +
> target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1)
> {
> float16 frs1 = check_nanbox_h(rs1);
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index b50672d1684..9c89521d4ad 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -74,6 +74,9 @@ DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64,
> i64)
> DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
> DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
> DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64)
> +DEF_HELPER_FLAGS_3(fle_h, TCG_CALL_NO_RWG, tl, env, i64, i64)
> +DEF_HELPER_FLAGS_3(flt_h, TCG_CALL_NO_RWG, tl, env, i64, i64)
> +DEF_HELPER_FLAGS_3(feq_h, TCG_CALL_NO_RWG, tl, env, i64, i64)
> DEF_HELPER_FLAGS_2(fcvt_s_h, TCG_CALL_NO_RWG, i64, env, i64)
> DEF_HELPER_FLAGS_2(fcvt_h_s, TCG_CALL_NO_RWG, i64, env, i64)
> DEF_HELPER_FLAGS_2(fcvt_d_h, TCG_CALL_NO_RWG, i64, env, i64)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index ba40f3e7f89..3906c9fb201 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -751,6 +751,9 @@ fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
> fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
> fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
> +feq_h 1010010 ..... ..... 010 ..... 1010011 @r
> +flt_h 1010010 ..... ..... 001 ..... 1010011 @r
> +fle_h 1010010 ..... ..... 000 ..... 1010011 @r
> fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
> fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
> fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc
> b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index d1250257666..8d0959a6671 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -335,6 +335,43 @@ static bool trans_fcvt_h_d(DisasContext *ctx,
> arg_fcvt_h_d *a)
> return true;
> }
>
> +static bool trans_feq_h(DisasContext *ctx, arg_feq_h *a)
> +{
> + REQUIRE_FPU;
> + REQUIRE_ZFH(ctx);
> +
> + TCGv dest = dest_gpr(ctx, a->rd);
> +
> + gen_helper_feq_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> +static bool trans_flt_h(DisasContext *ctx, arg_flt_h *a)
> +{
> + REQUIRE_FPU;
> + REQUIRE_ZFH(ctx);
> +
> + TCGv dest = dest_gpr(ctx, a->rd);
> +
> + gen_helper_flt_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(ctx, a->rd, dest);
> +
> + return true;
> +}
> +
> +static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a)
> +{
> + REQUIRE_FPU;
> + REQUIRE_ZFH(ctx);
> +
> + TCGv dest = dest_gpr(ctx, a->rd);
> +
> + gen_helper_fle_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a)
> {
> REQUIRE_FPU;
> --
> 2.25.1
>
>
