Hi Eduardo,
I have some question regrading Intel PT live migration.
Commit "e37a5c7fa459 (i386: Add Intel Processor Trace feature support)"
expose Intel PT with a fixed capabilities of CPUID 0x14 for live
migration. And the fixed capabilities are the value reported on
ICX(IceLake). However, t
On 24/08/2021 11:09, Finn Thain wrote:
Reads and writes to the TL and TC registers have no immediate effect on
a running timer, with the exception of a write to TCH. Hence these
mos6522_timer_update() calls are not needed.
Signed-off-by: Finn Thain
Perhaps better to flip this description aro
On 24/08/2021 11:09, Finn Thain wrote:
This improves readability.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 1d4a56077e..c0d6bee4cc 100644
--- a/hw/misc/mos6522.c
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
hw/remote/mpqemu-link.c:221: bad error checking ?
Status in QEMU:
Fi
** Changed in: qemu
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Title:
WFI instruction results in unhandled CPU exception
Status in QEMU:
F
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Qemu fails to start with error " There is no option group 'spice'"
Sta
** Changed in: qemu
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Title:
Abort in vmxnet3_validate_queues
Status in QEMU:
Fix Released
Bug d
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
libvixl compilation failure on Debian unstable
Status in QEMU:
Fix R
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Assertion `tx_queue_idx <= s->txq_num' failed in vmxnet3_io_bar0_write
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Assertion failure in net_tx_pkt_reset through vmxnet3
Status in QEMU:
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Status: Fix Committed => Fix Released
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Title:
UNDEFINED case for instruction BLX
Status in QEMU:
Fix Released
Bug
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
No check for unaligned data access in ARM32 instructions
Status in QEM
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
QEMU-user doesn't report HWCAP2_MTE
Status in QEMU:
Fix Released
Bu
** Changed in: qemu
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Title:
[OSS-Fuzz] Issue 29174 sb16: Abrt in audio_bug
Status in QEMU:
Fix R
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
STR in Thumb 32 decode problem
Status in QEMU:
Fix Released
Bug des
On 24/08/2021 11:09, Finn Thain wrote:
The Synertek datasheet says, "A write to T1L-H loads an 8-bit count value
into the latch. A read of T1L-H transfers the contents of the latch to
the data bus. Neither operation has an affect [sic] on the interrupt
flag."
Signed-off-by: Finn Thain
---
hw
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Abort() in mch_update_pciexbar
Status in QEMU:
Fix Released
Bug des
Felix, if you want to discuss the default behaviour, please get in touch with
the author of the patch, since he might not read this bug tracker here.
Anyway, the patch has been released with QEMU 6.1, so I'm closing this ticket
here now.
** Changed in: qemu
Status: Fix Committed => Fix Re
** Changed in: qemu
Status: Expired => Fix Released
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Title:
man page is missing suboptions for "-display"
Status in QEMU:
Fix Released
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
bios_linker_loader_add_checksum: Assertion `start_offset <
file->blob
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
borland IDEs double up cursor key presses (need timing on PS2 port
in
** Changed in: qemu
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Title:
Short files returned via FTP on Qemu with various architectures and
O
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
RISC-V Vector Instruction vssub.vv not saturating
Status in QEMU:
Fi
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
colo: pvm flush failed after svm killed
Status in QEMU:
Fix Released
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Assertion failure in net_tx_pkt_add_raw_fragment through vmxnet3
Statu
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Performance improvement when using "QEMU_FLATTEN" with softfloat type
** Changed in: qemu
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Title:
[OSS-Fuzz] Issue 27796 in oss-fuzz: qemu:qemu-fuzz-i386-target-
gener
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Missing page crossing check in use_goto_tb() for rx target
Status in Q
On 25.08.21 01:48, Viktor Prutyanov wrote:
Make 'qemu-img commit' work on Windows.
Command 'commit' requires reopening backing file in RW mode. So,
add reopen prepare/commit/abort handlers and change dwShareMode
for CreateFile call in order to allow further read/write reopening.
Resolves: https
Markus Armbruster writes:
> Did this series fall through the cracks for 6.1?
Missed 6.1. What now?
> Jean-Philippe Brucker writes:
>
>> Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine
>> parameter definitions cannot use underscores, because keyval_dashify()
>> transform
Is this still happening with the latest release?
** Changed in: nova
Status: Confirmed => Incomplete
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Title:
live migration intermittent
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
qemu user mode: rt signals not implemented for sparc guests
Status in
Add the sev_add_kernel_loader_hashes function to calculate the hashes of
the kernel/initrd/cmdline and fill a designated OVMF encrypted hash
table area. For this to work, OVMF must support an encrypted area to
place the data which is advertised via a special GUID in the OVMF reset
table.
The hash
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
multiprocess program gets incorrect results with qemu arm-linux-user
S
If SEV is enabled and a kernel is passed via -kernel, pass the hashes of
kernel/initrd/cmdline in an encrypted guest page to OVMF for SEV
measured boot.
Co-developed-by: James Bottomley
Signed-off-by: James Bottomley
Signed-off-by: Dov Murik
Reviewed-by: Connor Kuehl
---
hw/i386/x86.c | 25 ++
Hi
On Tue, Aug 24, 2021 at 7:27 PM Peter Xu wrote:
> Both dump-guest-memory and live migration caches vm state at the beginning.
> Either of them entering the other one will cause race on the vm state, and
> even
> more severe on that (please refer to the crash report in the bug link).
>
> Let's
(Resending for QEMU 6.2; no code changes since the last round.)
Currently booting with -kernel/-initrd/-append is not supported in SEV
confidential guests, because the content of these blobs is not measured
and therefore not trusted by the SEV guest.
However, in some cases the kernel, initrd, and
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/559
** Changed in: qemu
Status: In Progress => Expired
** B
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/560
** Tags added: net
** Changed in: qemu
Status: In Progr
Peter Maydell writes:
> On Tue, 24 Aug 2021 at 16:15, Markus Armbruster wrote:
>> True, except when I called it "kind of wrong", I was still talking about
>> functions with an Error **errp parameter.
>
> Oh yes, so you were. I even quoted your sentence starting
> "In functions with an Error **er
Hi all,
almost everybody is using the new Gitlab issue tracker
(https://gitlab.com/qemu-project/qemu/-/issues) already, which is really
great, but just to make it official: The QEMU Launchpad tracker
(https://bugs.launchpad.net/qemu) is now discontinued and should not be used
anymore. At l
Peter Xu writes:
> Both dump-guest-memory and live migration have vm state cached internally.
> Allowing them to happen together means the vm state can be messed up. Simply
> block live migration for dump-guest-memory.
>
> One trivial thing to mention is we should still allow dump-guest-memory e
The vf's unmasked msix vectors will be enable one by one in
migraiton resume phase, VFIO_DEVICE_SET_IRQS will be called
for each vector, it's a bit expensive if the vf has more
vectors.
We can call VFIO_DEVICE_SET_IRQS once outside the loop of set
vector notifiers to reduce the cost.
The test VM
The kvm_irqchip_commit_routes() is relatively expensive, so
provide the users a choice to commit the route immediately
or not when they add msi/msix route.
Signed-off-by: Longpeng(Mike)
---
accel/kvm/kvm-all.c| 10 +++---
accel/stubs/kvm-stub.c | 3 ++-
hw/misc/ivshmem.c | 2 +-
h
'msix_function_masked' is kept pace with the device's config,
we can use it to replace the complex conditional in
msix_set/unset_vector_notifiers.
poll_notifier should be reset to NULL in the error path in
msix_set_vector_notifiers, fix it incidentally.
Signed-off-by: Longpeng(Mike)
---
hw/pci/
The main difference of the failure path in vfio_msi_enable and
vfio_msi_disable_common is enable INTX or not.
Extend the vfio_msi_disable_common to provide a arg to decide
whether need to fallback, and then we can use this helper to
instead the redundant code in vfio_msi_enable.
Signed-off-by: Lo
In vfio migration resume phase, the cost would increase if the
vfio device has more unmasked vectors. We try to optimize it in
this series.
Patch 1 & 2 are simple code cleanups.
Patch 3 defers to set irqs to vfio core.
Patch 4 & 5 defer to commit the route to KVM core.
The test VM has 128 vcpus
In migration resume phase, all unmasked msix vectors need to be
setup when load the VF state. However, the setup operation would
takes longer if the VF has more unmasked vectors.
In our case, the VF has 65 vectors and each one spend at most 0.8ms
on setup operation the total cost of the VF is abou
Peter Xu wrote:
> An internal version that removes -only-migratable implications. It can be
> used
> for temporary migration blockers like dump-guest-memory.
>
> Signed-off-by: Peter Xu
Reviewed-by: Juan Quintela
On 24.08.21 21:52, Peter Xu wrote:
On Tue, Aug 24, 2021 at 06:24:27PM +0200, David Hildenbrand wrote:
Not so much; here's the list of priorities and the devices using it:
|+-|
| priority | devices |
|+-
Christian Schoenebeck writes:
> On Dienstag, 24. August 2021 17:24:50 CEST Christian Schoenebeck wrote:
>> On Dienstag, 24. August 2021 16:45:12 CEST Markus Armbruster wrote:
>> > Christian Schoenebeck writes:
>> > > On Dienstag, 24. August 2021 10:22:52 CEST Markus Armbruster wrote:
>> > [...]
On 24/08/2021 11:09, Finn Thain wrote:
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 19 ---
include/hw/misc/mos6522.h | 3 +++
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 8991f4..5b1657ac0d 100
On 24/08/2021 11:09, Finn Thain wrote:
The first reload of timer 1 is early by half of a clock cycle as it gets
measured from a falling edge. By contrast, the succeeding reloads are
measured from rising edge to rising edge.
Neglecting that complication, the behaviour of the counter should be th
On 24/08/2021 11:09, Finn Thain wrote:
It necessary to call mos6522_update_irq() when the interrupt flags
change and unnecessary when they haven't.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mos6522.c b/hw/mi
On 24/08/2021 11:09, Finn Thain wrote:
mos6522_read() and mos6522_write() may call various functions to determine
timer irq state, timer counter value and QEMUTimer deadline. All called
functions must use the same value for the present time.
Signed-off-by: Finn Thain
---
hw/misc/mos6522.c |
On 24/08/2021 11:09, Finn Thain wrote:
We rely on a QEMUTimer callback to set the interrupt flag, and this races
with counter register accesses, such that the guest might see the counter
reloaded but might not see the interrupt flagged.
According to the datasheet, a real 6522 device counts down
On 24/08/2021 11:09, Finn Thain wrote:
This is a patch series that I started last year. The aim was to try to
get a monotonic clocksource for Linux/m68k guests. That aim hasn't been
achieved yet (for q800 machines) but I'm submitting the patch series as
an RFC because,
- It does improve 6522
The -display sdl option is not using QAPI internally yet, and uses hand-
crafted parsing instead (see parse_display() in vl.c), which is quite
ugly, since most of the other code is using the QAPIfied DisplayOption
already. Unfortunately, the "alt_grab" and "ctrl_grab" use underscores in
their names
-display sdl uses a hand-crafted parser in vl.c, which is quite ugly
since the other parts of -display have been QAPIfied already. A straight
conversion to QAPI is not advisable since the "alt_grab" and "ctrl_grab"
parameters are not the best solution anyway. So this patch series
introduces a new "
The alt_grab and ctrl_grab parameter of the -display sdl option prevent
the QAPIfication of the "sdl" part of the -display option, so we should
eventually remove them. And since this feature is also rather niche anyway,
we should not clutter the top-level option list with these, so let's
also depre
It's not that much complicated to type "-display sdl" or "-display curses",
so we should not clutter our main option name space with such simple
wrapper options and rather present the users with a concise interface
instead. Thus let's deprecate the "-sdl" and "-curses" wrapper options now.
Acked-b
Commit cfb5387a1d 'hmp: remove "change vnc TARGET" command' claims to
remove the HMP "change vnc" command, but doesn't actually do that.
Instead if rewires it to use 'qmp_change_vnc_password', and in the
process inverts the argument detection - ignoring the first issue, this
inversion is wrong, as
Since the removal of the generic 'qmp_change' command, one can no longer replace
the 'default' VNC display listen address at runtime (AFAIK). For our users who
need to set up a secondary VNC access port, this means configuring a second VNC
display (in addition to our standard one for web-access), b
It is possible to specify more than one VNC server on the command line,
either with an explicit ID or the auto-generated ones à la "default",
"vnc2", "vnc3", ...
It is not possible to change the password on one of these extra VNC
displays though. Fix this by adding a "display" parameter to the
'se
Peter Xu writes:
> On Mon, Aug 23, 2021 at 05:56:23PM -0400, Eduardo Habkost wrote:
>> I don't have any other example, but I assume address assignment
>> based on ordering is a common pattern in device code.
>>
>> I would take a very close and careful look at the devices with
>> non-default vmsd
Commit 24f675cd3b ("sparc/sun4m: Use start-powered-off CPUState property")
changed
the sun4m CPU reset code to use the start-powered-off property and so split the
creation of the CPU into separate instantiation and realization phases to enable
the new start-powered-off property to be set.
This ac
On 8/25/21 9:56 AM, Longpeng(Mike) wrote:
> 'msix_function_masked' is kept pace with the device's config,
> we can use it to replace the complex conditional in
> msix_set/unset_vector_notifiers.
Typo 'simplfy' -> 'simplify' in this/previous patch subject.
> poll_notifier should be reset to NULL i
12.08.2021 11:41, Hanna Reitz wrote:
As we have attempted before
(https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg06451.html,
"file-posix: Cache lseek result for data regions";
https://lists.nongnu.org/archive/html/qemu-block/2021-02/msg00934.html,
"file-posix: Cache next hole"), this pa
在 2021/8/25 17:52, Philippe Mathieu-Daudé 写道:
> On 8/25/21 9:56 AM, Longpeng(Mike) wrote:
>> 'msix_function_masked' is kept pace with the device's config,
>> we can use it to replace the complex conditional in
>> msix_set/unset_vector_notifiers.
>
> Typo 'simplfy' -> 'simplify' in this/previous
On 8/25/21 9:56 AM, Longpeng(Mike) wrote:
> The vf's unmasked msix vectors will be enable one by one in
> migraiton resume phase, VFIO_DEVICE_SET_IRQS will be called
Typo "migration"
> for each vector, it's a bit expensive if the vf has more
> vectors.
>
> We can call VFIO_DEVICE_SET_IRQS once o
Cc'ing David/Juan for migration big picture (just in case).
On 8/25/21 9:56 AM, Longpeng(Mike) wrote:
> In vfio migration resume phase, the cost would increase if the
> vfio device has more unmasked vectors. We try to optimize it in
> this series.
>
> Patch 1 & 2 are simple code cleanups.
> Patch
在 2021/8/25 17:57, Philippe Mathieu-Daudé 写道:
> On 8/25/21 9:56 AM, Longpeng(Mike) wrote:
>> The vf's unmasked msix vectors will be enable one by one in
>> migraiton resume phase, VFIO_DEVICE_SET_IRQS will be called
>
> Typo "migration"
>
Ok.
>> for each vector, it's a bit expensive if the vf
在 2021/8/25 18:05, Philippe Mathieu-Daudé 写道:
> Cc'ing David/Juan for migration big picture (just in case).
>
> On 8/25/21 9:56 AM, Longpeng(Mike) wrote:
>> In vfio migration resume phase, the cost would increase if the
>> vfio device has more unmasked vectors. We try to optimize it in
>> this
On 8/25/21 11:51 AM, Mark Cave-Ayland wrote:
> Commit 24f675cd3b ("sparc/sun4m: Use start-powered-off CPUState property")
> changed
> the sun4m CPU reset code to use the start-powered-off property and so split
> the
> creation of the CPU into separate instantiation and realization phases to
> en
In the MVE helpers for the narrowing operations (DO_VSHRN and
DO_VSHRN_SAT) we were using the wrong bits of the predicate mask for
the 'top' versions of the insn. This is because the loop works over
the double-sized input elements and shifts the predicate mask by that
many bits each time, but when
Although the architecture doesn't define it as an alias, VMOVL
(vector move long) is encoded as a VSHLL with a zero shift.
Add a comment in the decode file noting that we handle VMOVL
as part of VSHLL.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/mve.decode | 2 ++
/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210825
for you to fetch changes up to 24b1a6aa43615be22c7ee66bd68ec5675f6a6a9a:
docs: Document how to use gdb with unix sockets (2021-08-25 10:48:51 +0100)
target-arm queue:
* More
Include the MVE VPR register value in the CPU dumps produced by
arm_cpu_dump_state() if we are printing FPU information. This
makes it easier to interpret debug logs when predication is
active.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 3 +++
1 file chan
In the MVE shift-and-insert insns, we special case VSLI by 0
and VSRI by . VSRI by means "don't update the destination",
which is what we've implemented. However VSLI by 0 is "set
destination to the input", so we don't want to use the same
special-casing that we do for VSRI by .
Since the generic
Implement the MVE incrementing/decrementing dup insns VIDUP, VDDUP,
VIWDUP and VDWDUP. These fill the elements of a vector with
successively incrementing values, starting at the offset specified in
a general purpose register. The final value of the offset is written
back to this register. The wr
In some situations we need a mask telling us which parts of the
vector correspond to beats that are not being executed because of
ECI, separately from the combined "which bytes are predicated away"
mask. Factor this mask calculation out of mve_element_mask() into
its own function.
Signed-off-by:
In do_sqrshl48_d() and do_uqrshl48_d() we got some of the edge
cases wrong and failed to saturate correctly:
(1) In do_sqrshl48_d() we used the same code that do_shrshl_bhs()
does to obtain the saturated most-negative and most-positive 48-bit
signed values for the large-shift-left case. This give
Implement the MVE saturating doubling multiply accumulate insns
VQDMLAH, VQRDMLAH, VQDMLASH and VQRDMLASH. These perform a multiply,
double, add the accumulator shifted by the element size, possibly
round, saturate to twice the element size, then take the high half of
the result. The *MLAH insns
We got an edge case wrong in the 48-bit SQRSHRL implementation: if
the shift is to the right, although it always makes the result
smaller than the input value it might not be within the 48-bit range
the result is supposed to be if the input had some bits in [63..48]
set and the shift didn't bring a
Implement the MVE integer vector comparison instructions that compare
each element against a scalar from a general purpose register. These
are "VCMP (vector)" encodings T4, T5 and T6 and "VPT (vector)"
encodings T4, T5 and T6.
We have to move the decodetree pattern for VPST, because it
overlaps w
For vector loads, predicated elements are zeroed, instead of
retaining their previous values (as happens for most data
processing operations). This means we need to distinguish
"beat not executed due to ECI" (don't touch destination
element) from "beat executed but predicated out" (zero
destination
A cut-and-paste error meant we handled signed VADDV like
unsigned VADDV; fix the type used.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/mve_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/mve_helper.c b/target/arm/mve_
Implement the MVE VABAV insn, which computes absolute differences
between elements of two vectors and accumulates the result into
a general purpose register.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 7 +++
target/arm/mve.decode | 6
Implement the MVE VMOV forms that move data between 2 general-purpose
registers and 2 32-bit lanes in a vector register.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-a32.h | 1 +
target/arm/mve.decode | 4 ++
target/arm/translate-mve.c | 85 +++
Implement the MVE VMULL (polynomial) insn. Unlike Neon, this comes
in two flavours: 8x8->16 and a 16x16->32. Also unlike Neon, the
inputs are in either the low or the high half of each double-width
element.
The assembler for this insn indicates the size with "P8" or "P16",
encoded into bit 28 as
In mve_element_mask(), we calculate a mask for tail predication which
should have a number of 1 bits based on the value of LR. However,
our MAKE_64BIT_MASK() macro has undefined behaviour when passed a
zero length. Special case this to give the all-zeroes mask we
require.
Signed-off-by: Peter Ma
Factor out the "generate code to update VPR.MASK01/MASK23" part of
trans_VPST(); we are going to want to reuse it for the VPT insns.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/translate-mve.c | 31 +--
1 file changed, 17 insertions(+),
Implement the MVE VPSEL insn, which sets each byte of the destination
vector Qd to the byte from either Qn or Qm depending on the value of
the corresponding bit in VPR.P0.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 2 ++
target/arm/mve.decode
Implement the MVE VPNOT insn, which inverts the bits in VPR.P0
(subject to both predication and to beatwise execution).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 1 +
target/arm/mve.decode | 1 +
target/arm/mve_helper.c| 17 +
From: Hamza Mahfooz
As per commit 5626f8c6d468 ("rcu: Add automatically released rcu_read_lock
variants"), RCU_READ_LOCK_GUARD() should be used instead of
rcu_read_{un}lock().
Signed-off-by: Hamza Mahfooz
Reviewed-by: Paolo Bonzini
Message-id: 20210727235201.11491-1-some...@effective-light.com
We were not paying attention to the ECI state when advancing the VPT
state. Architecturally, VPT state advance happens for every beat
(see the pseudocode VPTAdvance()), so on every beat the 4 bits of
VPR.P0 corresponding to the current beat are inverted if required,
and at the end of beats 1 and 3
Implement the MVE integer vector comparison instructions. These are
"VCMP (vector)" encodings T1, T2 and T3, and "VPT (vector)" encodings
T1, T2 and T3.
These insns compare corresponding elements in each vector, and update
the VPR.P0 predicate bits with the results of the comparison. VPT
also se
Implement the MVE gather-loads and scatter-stores which
form the address by adding a base value from a scalar
register to an offset in each element of a vector.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper-mve.h| 32 +
target/arm/mve.decode
Implement the MVE instructions which perform shifts by a scalar.
These are VSHL T2, VRSHL T2, VQSHL T1 and VQRSHL T2. They take the
shift amount in a general purpose register and shift every element in
the vector by that amount.
Mostly we can reuse the helper functions for shift-by-immediate; we
We're about to make a code change to the sdiv and udiv helper
functions, so first fix their indentation and coding style.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20210730151636.17254-2-peter.mayd...@linaro.org
---
target/arm/helper.c | 15 +--
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