On 24/08/2021 11:09, Finn Thain wrote:

The Synertek datasheet says, "A write to T1L-H loads an 8-bit count value
into the latch. A read of T1L-H transfers the contents of the latch to
the data bus. Neither operation has an affect [sic] on the interrupt
flag."

Signed-off-by: Finn Thain <fth...@linux-m68k.org>
---
  hw/misc/mos6522.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index c0d6bee4cc..ffff8991f4 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -313,7 +313,6 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, 
unsigned size)
          break;
      case VIA_REG_T1LH:
          s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
-        s->ifr &= ~T1_INT;
          break;
      case VIA_REG_T2CL:
          s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;

Hmmm. The reference document I used for QEMU's 6522 device is at http://archive.6502.org/datasheets/mos_6522_preliminary_nov_1977.pdf and according to page 6 and the section "Writing the Timer 1 Registers" writing to the high byte of the latch does indeed clear the T1 interrupt flag.

Side note: there is reference in Gary Davidian's excellent CHM video that 6522s obtained from different manufacturers had different behaviours, and there are also web pages mentioning that 6522s integrated as part of other silicon e.g. IOSB/CUDA also had their own bugs... :/


ATB,

Mark.

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