[PULL 2/5] i2c/smbus_eeprom: Add feature bit to SPD data

2021-07-29 Thread David Gibson
From: BALATON Zoltan Add the differential clock input feature bit to the generated SPD data. Most guests don't seem to care but pegasos2 firmware version 1.2 checks for this bit and stops with unsupported module type error if it's not present. Since this feature is likely present on real memory m

[PULL 3/5] target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32

2021-07-29 Thread David Gibson
From: Matheus Ferst In commit 8f0a4b6a9b, we started to require L=0 for ppc32 to match what The Programming Environments Manual say: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." The stricter behavior, however, broke AROS boot on sam460ex,

[PULL 5/5] kvm: ppc: Print meaningful message on KVM_CREATE_VM failure

2021-07-29 Thread David Gibson
From: Fabiano Rosas PowerPC has two KVM types (HV, PR) that translate into three kernel modules: kvm.ko - common kvm code kvm_hv.ko - kvm running with MSR_HV=1 or MSR_HV|PR=0 in a nested guest. kvm_pr.ko - kvm running in usermode MSR_PR=1. Since the two KVM types can both be running at the same

[PULL 1/5] ppc/pegasos2: Fix spurious warning with -bios

2021-07-29 Thread David Gibson
From: BALATON Zoltan The -append option is currently not compatible with -bios (as we don't yet emulate nvram so we can only put it in the environment with VOF). Therefore a warning is printed if -append is used with -bios but because the default value of kernel_cmdline seems to be an empty strin

[PULL 4/5] ppc/vof: Fix Coverity issues

2021-07-29 Thread David Gibson
From: Alexey Kardashevskiy Coverity reported issues which are caused by mixing of signed return codes from DTC and unsigned return codes of the client interface. This introduces PROM_ERROR and makes distinction between the error types. This fixes NEGATIVE_RETURNS, OVERRUN issues reported by Cov

[PULL 0/5] ppc-for-6.1 queue 20210729

2021-07-29 Thread David Gibson
pc-for-6.1-20210729 for you to fetch changes up to 380e49297c302fdcf8e5d56abdbe07868d3af8d8: kvm: ppc: Print meaningful message on KVM_CREATE_VM failure (2021-07-29 10:59:49 +1000) ppc patch queue 2021-07-29 Here's a small batch

RE: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU type

2021-07-29 Thread ishii.shuuic...@fujitsu.com
Hi, Peter. > This adds a64fx to the list of CPUs we support in the 'virt' board, but it > hasn't > changed the valid_cpus[] array in hw/arm/virt.c, so trying to actually use > -cpu > a64fx with -machine virt will fail. I'm sorry, but just to be sure, let me check. Is it correct to understand t

Re: [PATCH for-6.2 33/43] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote: > The previous placement in tcg/tcg.h was not logical. > > Signed-off-by: Richard Henderson > --- > include/exec/cpu_ldst.h | 87 +++ > include/tcg/tcg.h | 87 --- > tar

Re: [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote: > We should not have been using the helper_ret_* set of > functions, as they are supposed to be private to tcg. > Nor should we have been using the plain cpu_*_data set > of functions, as they do not handle unwinding properly. > > Cc: Philippe Mathieu-D

Re: [PATCH for-6.2 36/43] target/s390x: Use cpu_*_mmu instead of helper_*_mmu

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote: > The helper_*_mmu functions were the only thing available > when this code was written. This could have been adjusted > when we added cpu_*_mmuidx_ra, but now we can most easily > use the newest set of interfaces. > > Cc: qemu-s3...@nongnu.org > Signe

Re: [PATCH for-6.2 38/43] target/arm: Use cpu_*_mmu instead of helper_*_mmu

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote: > The helper_*_mmu functions were the only thing available > when this code was written. This could have been adjusted > when we added cpu_*_mmuidx_ra, but now we can most easily > use the newest set of interfaces. > > Cc: qemu-...@nongnu.org > Signed-

Re: [PATCH for-6.2 39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote: > These functions have been replaced by cpu_*_mmu as the > most proper interface to use from target code. > > Hide these declarations from code that should not use them. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg-ldst.h | 74 +++

Re: [PATCH 2/2] i386: Fix coding style in kvm_hyperv_expand_features()

2021-07-29 Thread Paolo Bonzini
On 16/07/21 13:58, Vitaly Kuznetsov wrote: QEMU coding style requires braces around bodies of ifs. Reported-by: Peter Maydell Signed-off-by: Vitaly Kuznetsov --- target/i386/kvm/kvm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i3

Re: [PATCH] configure: Add -Werror to avx2, avx512 tests

2021-07-29 Thread Paolo Bonzini
On 19/07/21 22:01, Richard Henderson wrote: When using clang, we get ERROR: configure test passed without -Werror but failed with -Werror. This is probably a bug in the configure script. The failing command will be at the bottom of config.log. You can run configure with -

Re: [PATCH 1/3] hw/mips/boston: Massage memory map information

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 5:39 AM, Jiaxun Yang wrote: > Use memmap array to unfiy address of memory map. > That would allow us reuse address information for FDT generation. > > Signed-off-by: Jiaxun Yang > --- > hw/mips/boston.c | 95 > 1 file changed, 71 insert

Bug in qemu-system-ppc running fedora 12 ppc guest

2021-07-29 Thread Howard Spoelstra
Hi, Qemu-system-ppc built from current master can no longer run Fedora 12 ppc as guest. (This the only ppc distro I tested.) Host is Fedora 34. Please see screen shot attached. Booting from both an installation DVD and from an installed system fail. To reproduce: compile qemu-system-ppc from curr

Re: [PATCH v2] target/i386: Added V_INTR_PRIO check to virtual interrupts

2021-07-29 Thread Paolo Bonzini
On 28/07/21 12:17, Lara Lazier wrote: v1->v2: Fixed Mask The APM2 states that The processor takes a virtual INTR interrupt if V_IRQ and V_INTR_PRIO indicate that there is a virtual interrupt pending whose priority is greater than the value in V_TPR. Signed-off-by: Lara Lazier --- target/i386

Re: [PATCH v2] target/i386: Added VGIF feature

2021-07-29 Thread Paolo Bonzini
On 28/07/21 13:37, Lara Lazier wrote: +if (virtual_gif_enabled(env, int_ctl) && likely(env->hflags & HF_GUEST_MASK)) { +x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), +int_ctl | V_GIF_MASK); +} else { I would put the HF_GUEST_MAS

Re: [PATCH v2] target/i386: Added VGIF feature

2021-07-29 Thread Paolo Bonzini
On 28/07/21 13:37, Lara Lazier wrote: +uint32_t int_ctl = x86_ldl_phys(cs, + env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); +if (virtual_gif_enabled(env, int_ctl) && likely(env->hflags & HF_GUEST_MASK)) { +x86_stl_phys(cs, env->vm_vmcb + offsetof(st

Re: [PATCH 2/3] hw/mips/boston: Allow loading elf kernel and dtb

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 5:39 AM, Jiaxun Yang wrote: > ELF kernel allows us debugging much easier with DWARF symbols. You can load the symbols using the 'loader' device: docs/system/generic-loader.rst. > Signed-off-by: Jiaxun Yang > --- > hw/mips/boston.c | 38 ++ > 1 file

Re: [PATCH for-6.2 10/43] target/s390x: Implement do_unaligned_access for user-only

2021-07-29 Thread David Hildenbrand
On 29.07.21 02:46, Richard Henderson wrote: Cc: qemu-s3...@nongnu.org Signed-off-by: Richard Henderson --- target/s390x/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 28 +++- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/s390x/c

Re: [PATCH for-6.2 30/43] target/s390x: Use MO_128 for 16 byte atomics

2021-07-29 Thread David Hildenbrand
On 29.07.21 02:46, Richard Henderson wrote: Cc: qemu-s3...@nongnu.org Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index ec88f5dbb0..3782

Re: [PATCH 2/2] libvhost-user: fix -Werror=format= warnings with __u64 fields

2021-07-29 Thread Paolo Bonzini
On 05/05/21 17:38, Stefan Hajnoczi wrote: On Wed, May 05, 2021 at 07:13:13PM +0400, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau ../subprojects/libvhost-user/libvhost-user.c:1070:12: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘__u64

Re: [PATCH RFC 03/19] vfio-user: define VFIO Proxy and communication functions

2021-07-29 Thread Stefan Hajnoczi
On Wed, Jul 28, 2021 at 06:08:26PM +, John Johnson wrote: > > > > On Jul 27, 2021, at 9:34 AM, Stefan Hajnoczi wrote: > > > > On Sun, Jul 18, 2021 at 11:27:42PM -0700, Elena Ufimtseva wrote: > >> From: John G Johnson > >> > >> Add user.c and user.h files for vfio-user with the basic > >>

Re: [PATCH v5 00/10] acpi: Error Record Serialization Table, ERST, support for QEMU

2021-07-29 Thread Igor Mammedov
On Wed, 28 Jul 2021 10:19:51 -0500 Eric DeVolder wrote: > On 7/27/21 7:55 AM, Igor Mammedov wrote: > > PS: > > If I haven't said it already, use checkpatch script before posting patches. > > > > I do run checkpatch. On occasion I allow a warning about a line too long. And > there is the MAINT

Re: aarch64 efi boot failures with qemu 6.0+

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/28/21 4:03 PM, Guenter Roeck wrote: > On 7/28/21 6:25 AM, Ard Biesheuvel wrote: >> On Wed, 28 Jul 2021 at 15:11, Michael S. Tsirkin wrote: >>> >>> On Tue, Jul 27, 2021 at 12:36:03PM +0200, Igor Mammedov wrote: >>> As others noted the original commit was kind of vague: >>> >>> 1. it said "Usi

Re: [PATCH for-6.2 16/43] target/xtensa: Implement do_unaligned_access for user-only

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote: > Cc: Max Filippov > Signed-off-by: Richard Henderson > --- > target/xtensa/cpu.c| 2 +- > target/xtensa/helper.c | 30 +++--- > 2 files changed, 16 insertions(+), 16 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 0/6] migration/ram: Optimize for virtio-mem via RamDiscardManager

2021-07-29 Thread David Hildenbrand
The thing is I still think this extra operation during sync() can be ignored by simply clear dirty log during bitmap init, then.. why not? :) I guess clearing the dirty log (especially in KVM) might be more expensive. If we send one ioctl per cb that'll be expensive for sure. I think it'll be

Re: [PATCH RFC 04/19] vfio-user: Define type vfio_user_pci_dev_info

2021-07-29 Thread Stefan Hajnoczi
On Thu, Jul 29, 2021 at 12:55:08AM +, John Johnson wrote: > > > > On Jul 28, 2021, at 3:16 AM, Stefan Hajnoczi wrote: > > > > On Sun, Jul 18, 2021 at 11:27:43PM -0700, Elena Ufimtseva wrote: > >> From: John G Johnson > >> > >> New class for vfio-user with its class and instance > >> const

[PULL 2/9] gitlab-ci: Fix 'when:' condition in acceptance_test_job_template

2021-07-29 Thread Thomas Huth
From: Philippe Mathieu-Daudé Jobs depending on another should not use the 'when: always' condition, because if a dependency failed we should not keep running jobs depending on it. The correct condition is 'when: on_success'. Fixes: f56bf4caf71 ("gitlab: Run Avocado tests manually (except mainstr

[PULL 4/9] gitlab-ci: Fix 'when:' condition in OpenSBI jobs

2021-07-29 Thread Thomas Huth
From: Philippe Mathieu-Daudé Jobs depending on another should not use the 'when: always' condition, because if a dependency failed we should not keep running jobs depending on it. The correct condition is 'when: on_success'. Fixes: c6fc0fc1a71 ("gitlab-ci.yml: Add jobs to build OpenSBI firmware

[PULL 0/9] Gitlab-CI improvements and some other fixes

2021-07-29 Thread Thomas Huth
Hi Peter! The following changes since commit 69ea12b19a15ae006521cd5cc0f627f27f738746: Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-07-27' into staging (2021-07-28 13:32:12 +0100) are available in the Git repository at: https://gitlab.com/thuth/qemu.git tags/pull-reque

[PULL 6/9] gitlab-ci.d/buildtest: Mark the aarch64 and ppc64-s390x CFI jobs as manual

2021-07-29 Thread Thomas Huth
These two jobs are currently failing very often - the linker seems to get killed due to out-of-memory problems. Since apparently nobody has currently an idea how to fix that nicely, let's mark the jobs as manual for the time being until someone comes up with a proper fix. Message-Id: <202107280751

[PULL 1/9] docs: Document GitLab custom CI/CD variables

2021-07-29 Thread Thomas Huth
From: Philippe Mathieu-Daudé We introduced the QEMU_CI_AVOCADO_TESTING variable in commit f56bf4caf ("gitlab: Run Avocado tests manually (except mainstream CI)"), but forgot to document it properly. Do it now. Suggested-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel

[PULL 5/9] gitlab-ci.d/buildtest: Disable iotests 197 and 215

2021-07-29 Thread Thomas Huth
The iotests 197 and 215 are occasionally failing in the gitlab-CI now. According to the log, the failure is "./common.rc: Killed" which might be an indication that the process has been killed due to out-of-memory reasons. Both tests are doing a big read with 2G that likely causes this issue. It use

[PULL 3/9] gitlab-ci: Fix 'when:' condition in EDK2 jobs

2021-07-29 Thread Thomas Huth
From: Philippe Mathieu-Daudé Jobs depending on another should not use the 'when: always' condition, because if a dependency failed we should not keep running jobs depending on it. The correct condition is 'when: on_success'. Fixes: 71920809cea ("gitlab-ci.yml: Add jobs to build EDK2 firmware bin

[PULL 7/9] gitlab-ci.d/custom-runners: Improve rules for the staging branch

2021-07-29 Thread Thomas Huth
If maintainers are currently pushing to a branch called "staging" in their repository, they are ending up with some stuck jobs - unless they have a s390x CI runner machine available. That's ugly, we should make sure that the related jobs are really only started if such a runner is available. So let

Re: [PATCH] tests: Fix migration-test build failure for sparc

2021-07-29 Thread Dr. David Alan Gilbert
* Thomas Huth (th...@redhat.com) wrote: > On 28/07/2021 23.41, Peter Xu wrote: > > Even if seems to exist for all archs on linux, however > > including > > it with __linux__ defined seems to be not working yet as it'll try to > > include > > asm/kvm.h and that can be missing for archs that do no

[PULL 9/9] configure script fix for Haiku

2021-07-29 Thread Thomas Huth
From: Richard Zak Haiku does not support compiling with -fpie. See the discussion here for details: https://discuss.haiku-os.org/t/qemu-on-haiku-sdl-issue/10961/6?u=rjzak Signed-off-by: Richard Zak Message-Id: [thuth: Tweaked title and patch description] Signed-off-by: Thomas Huth --- conf

[PULL 8/9] tests: Fix migration-test build failure for sparc

2021-07-29 Thread Thomas Huth
From: Peter Xu Even if seems to exist for all archs on linux, however including it with __linux__ defined seems to be not working yet as it'll try to include asm/kvm.h and that can be missing for archs that do not support kvm. To fix this (instead of any attempt to fix linux headers..), we can

Re: [PATCH for-6.2 05/43] target/microblaze: Implement do_unaligned_access for user-only

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote: > Cc: Edgar E. Iglesias > Signed-off-by: Richard Henderson > --- > target/microblaze/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

[PATCH v2] block/io_uring: resubmit when result is -EAGAIN

2021-07-29 Thread Fabian Ebner
Linux SCSI can throw spurious -EAGAIN in some corner cases in its completion path, which will end up being the result in the completed io_uring request. Resubmitting such requests should allow block jobs to complete, even if such spurious errors are encountered. Co-authored-by: Stefan Hajnoczi R

Re: [PATCH for-6.2 v3 06/11] machine: Prefer cores over sockets in smp parsing since 6.2

2021-07-29 Thread Cornelia Huck
On Wed, Jul 28 2021, Yanan Wang wrote: > In the real SMP hardware topology world, it's much more likely that > we have high cores-per-socket counts and few sockets totally. While > the current preference of sockets over cores in smp parsing results > in a virtual cpu topology with low cores-per-s

Re: [PATCH for-6.2 v3 07/11] machine: Use ms instead of global current_machine in sanity-check

2021-07-29 Thread Cornelia Huck
On Wed, Jul 28 2021, Yanan Wang wrote: > In the sanity-check of smp_cpus and max_cpus against mc in function > machine_set_smp(), we are now using ms->smp.max_cpus for the check > but using current_machine->smp.max_cpus in the error message. > Tweak this by uniformly using the local ms. > > Revie

modular tcg (was: Re: [PATCH v2 1/1] modules: Improve error message when module is not) found

2021-07-29 Thread Gerd Hoffmann
Hi, > > So we need more work to make this actually work right. > > Yes. I want have all of tcg in the tcg accel module, not only parts of > it, but that needs some more refactoring. I'll go start looking at this > once I managed to wade through my vacation backlog. So, changed the meson.buil

Re: [PATCH] hw/net/can: sja1000 fix buff2frame_bas for dlc out of std CAN 8 bytes

2021-07-29 Thread Pavel Pisa
Hello everybody, please, can somebody accept the fix for master? It should be ideally applied even to stable branches. Or should I send request through some other form then on the list? Thanks, Pavel On Monday 26 of July 2021 18:24:58 Pavel Pisa wrote: > Problem reported by openEuler fuzz-sig

Re: [PATCH for-6.2 15/43] target/sparc: Implement do_unaligned_access for user-only

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 2:46 AM, Richard Henderson wrote: > Cc: Mark Cave-Ayland > Signed-off-by: Richard Henderson > --- > linux-user/sparc/cpu_loop.c | 11 +++ > target/sparc/cpu.c | 2 +- > target/sparc/ldst_helper.c | 2 -- > 3 files changed, 12 insertions(+), 3 deletions(-) > > diff

Re: modular tcg

2021-07-29 Thread Claudio Fontana
On 7/29/21 11:14 AM, Gerd Hoffmann wrote: > Hi, > >>> So we need more work to make this actually work right. >> >> Yes. I want have all of tcg in the tcg accel module, not only parts of >> it, but that needs some more refactoring. I'll go start looking at this >> once I managed to wade through

Re: modular tcg

2021-07-29 Thread Claudio Fontana
On 7/29/21 11:14 AM, Gerd Hoffmann wrote: > Hi, > >>> So we need more work to make this actually work right. >> >> Yes. I want have all of tcg in the tcg accel module, not only parts of >> it, but that needs some more refactoring. I'll go start looking at this >> once I managed to wade through

Re: [PULL 8/9] tests: Fix migration-test build failure for sparc

2021-07-29 Thread Philippe Mathieu-Daudé
On 7/29/21 10:22 AM, Thomas Huth wrote: > From: Peter Xu > > Even if seems to exist for all archs on linux, however including > it with __linux__ defined seems to be not working yet as it'll try to include > asm/kvm.h and that can be missing for archs that do not support kvm. > > To fix this (i

Re: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU type

2021-07-29 Thread Peter Maydell
On Thu, 29 Jul 2021 at 08:31, ishii.shuuic...@fujitsu.com wrote: > > Hi, Peter. > > > This adds a64fx to the list of CPUs we support in the 'virt' board, but it > > hasn't > > changed the valid_cpus[] array in hw/arm/virt.c, so trying to actually use > > -cpu > > a64fx with -machine virt will fa

Re: [PATCH v2] block/io_uring: resubmit when result is -EAGAIN

2021-07-29 Thread Stefano Garzarella
On Thu, Jul 29, 2021 at 11:10:29AM +0200, Fabian Ebner wrote: Linux SCSI can throw spurious -EAGAIN in some corner cases in its completion path, which will end up being the result in the completed io_uring request. Resubmitting such requests should allow block jobs to complete, even if such spur

Re: [PATCH 1/3] docs: Move the protocol part of barrier.txt into interop

2021-07-29 Thread Laurent Vivier
Le 27/07/2021 à 22:41, Peter Maydell a écrit : > Most of docs/barrier.txt is describing the protocol implemented > by the input-barrier device. Move this into the interop > section of the manual, and rstify it. > > Signed-off-by: Peter Maydell > --- > docs/barrier.txt | 318 -

Re: [PATCH 2/3] ui/input-barrier: Move TODOs from barrier.txt to a comment

2021-07-29 Thread Laurent Vivier
Le 27/07/2021 à 22:41, Peter Maydell a écrit : > docs/barrier.txt has a couple of TODO notes about things to be > implemented in this device; move them into a comment in the > source code. > > Signed-off-by: Peter Maydell > --- > docs/barrier.txt | 4 > ui/input-barrier.c | 5 + > 2 f

Re: [PATCH 3/3] docs: Move user-facing barrier docs into system manual

2021-07-29 Thread Laurent Vivier
Le 27/07/2021 à 22:41, Peter Maydell a écrit : > The remaining text in docs/barrier.txt is user-facing description > of what the device is and how to use it. Move this into the > system manual and rstify it. > > Signed-off-by: Peter Maydell > --- > docs/barrier.txt| 48 --

Re: [PATCH RFC 0/3] mirror: rework soft-cancelling READY mirror

2021-07-29 Thread Vladimir Sementsov-Ogievskiy
28.07.2021 10:00, Max Reitz wrote: On 27.07.21 18:47, Vladimir Sementsov-Ogievskiy wrote: Hi all! That's an alternative to (part of) Max's "[PATCH for-6.1? v2 0/7] mirror: Handle errors after READY cancel" and shows' my idea of handling soft-cancelling READY mirror case directly in qmp_block_jo

Re: [PATCH-for-6.1] hw/net/can: sja1000 fix buff2frame_bas for dlc out of std CAN 8 bytes

2021-07-29 Thread Philippe Mathieu-Daudé
Cc'ing QEMU fuzz team. On 7/29/21 11:19 AM, Pavel Pisa wrote: > Hello everybody, > > please, can somebody accept the fix for master? > It should be ideally applied even to stable > branches. > > Or should I send request through some other form > then on the list? I suppose the patch fell throug

Re: Bug in qemu-system-ppc running fedora 12 ppc guest

2021-07-29 Thread BALATON Zoltan
Hello, On Thu, 29 Jul 2021, Howard Spoelstra wrote: Hi, Qemu-system-ppc built from current master can no longer run Fedora 12 ppc as guest. (This the only ppc distro I tested.) Host is Fedora 34. Please see screen shot attached. Booting from both an installation DVD and from an installed system

[PATCH-for-6.1? v2] target/nios2: Mark raise_exception() as noreturn

2021-07-29 Thread Philippe Mathieu-Daudé
Raised exceptions don't return, so mark the helper with noreturn. Fixes: 032c76bc6f9 ("nios2: Add architecture emulation support") Signed-off-by: Philippe Mathieu-Daudé --- v2: use TCG_CALL_NO_WG instead of noreturn (rth) Probably too late for 6.1, sorry I simply forgot to resend this patch (and

RE: [PATCH 4/4] docs/system: Add a64fx(Fujitsu A64FX processor) to supported guest CPU type

2021-07-29 Thread ishii.shuuic...@fujitsu.com
> If you want this CPU to work with the virt board, then yes. > You should put it above 'host' and 'max' (because those are > not-real-cpu special cases, so it makes more sense for them to be last > in the list). > > More generally: how are you testing this patchset? To test it > you should have

Re: modular tcg

2021-07-29 Thread Gerd Hoffmann
Hi, > > It's basically two groups: > > > > * Arch-specific (functions taking CPUX86State as argument), most of the > >unresolved symbols in target/i386/ and i386/ directories go into this > >category. > > Yes, and we need to think about all targets, not just i386. Sure. I just want

Re: modular tcg

2021-07-29 Thread Gerd Hoffmann
Hi, > And another comment: I think we should have some progress on ARM with > the kvm/tcg split and with the KConfig of boards, before we continue > here. Why? This can easily be tacked in parallel. We can flip the switch for modular tcg per target in meson.build. take care, Gerd

Re: [PATCH RFC 0/3] mirror: rework soft-cancelling READY mirror

2021-07-29 Thread Max Reitz
On 29.07.21 12:02, Vladimir Sementsov-Ogievskiy wrote: 28.07.2021 10:00, Max Reitz wrote: On 27.07.21 18:47, Vladimir Sementsov-Ogievskiy wrote: Hi all! That's an alternative to (part of) Max's "[PATCH for-6.1? v2 0/7] mirror: Handle errors after READY cancel" and shows' my idea of handling so

Re: modular tcg

2021-07-29 Thread Claudio Fontana
On 7/29/21 12:26 PM, Gerd Hoffmann wrote: > Hi, > >>> It's basically two groups: >>> >>> * Arch-specific (functions taking CPUX86State as argument), most of the >>>unresolved symbols in target/i386/ and i386/ directories go into this >>>category. >> >> Yes, and we need to think about al

Re: modular tcg

2021-07-29 Thread Claudio Fontana
On 7/29/21 12:29 PM, Gerd Hoffmann wrote: > Hi, > >> And another comment: I think we should have some progress on ARM with >> the kvm/tcg split and with the KConfig of boards, before we continue >> here. > > Why? This can easily be tacked in parallel. We can flip the switch > for modular tcg

[PING][PING][PATCH v2] vhost: make SET_VRING_ADDR, SET_FEATURES send replies

2021-07-29 Thread Denis Plotnikov
On 23.07.2021 12:59, Denis Plotnikov wrote: ping! On 19.07.2021 17:21, Denis Plotnikov wrote: On vhost-user-blk migration, qemu normally sends a number of commands to enable logging if VHOST_USER_PROTOCOL_F_LOG_SHMFD is negotiated. Qemu sends VHOST_USER_SET_FEATURES to enable buffers logging

[PATCH for-6.2 00/53] target/arm: MVE slices 3 and 4

2021-07-29 Thread Peter Maydell
This patchseries provides the third and fourth slices of the MVE implementation, which gives us complete coverage of all instructions and brings us to the point where we can actually enable it. In this series: * fixes for minor bugs in a couple of the insns already upstream * all the remaining i

[PATCH for-6.2 03/53] target/arm: Fix MVE VSLI by 0 and VSRI by

2021-07-29 Thread Peter Maydell
In the MVE shift-and-insert insns, we special case VSLI by 0 and VSRI by . VSRI by means "don't update the destination", which is what we've implemented. However VSLI by 0 is "set destination to the input", so we don't want to use the same special-casing that we do for VSRI by . Since the generic

[PATCH for-6.2 11/53] target/arm: Fix VLDRB/H/W for predicated elements

2021-07-29 Thread Peter Maydell
For vector loads, predicated elements are zeroed, instead of retaining their previous values (as happens for most data processing operations). This means we need to distinguish "beat not executed due to ECI" (don't touch destination element) from "beat executed but predicated out" (zero destination

[PATCH for-6.2 02/53] target/arm: Print MVE VPR in CPU dumps

2021-07-29 Thread Peter Maydell
Include the MVE VPR register value in the CPU dumps produced by arm_cpu_dump_state() if we are printing FPU information. This makes it easier to interpret debug logs when predication is active. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 +++ 1 file chan

[PATCH for-6.2 01/53] target/arm: Note that we handle VMOVL as a special case of VSHLL

2021-07-29 Thread Peter Maydell
Although the architecture doesn't define it as an alias, VMOVL (vector move long) is encoded as a VSHLL with a zero shift. Add a comment in the decode file noting that we handle VMOVL as part of VSHLL. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve.decode | 2 ++

[PATCH for-6.2 12/53] target/arm: Implement MVE VMULL (polynomial)

2021-07-29 Thread Peter Maydell
Implement the MVE VMULL (polynomial) insn. Unlike Neon, this comes in two flavours: 8x8->16 and a 16x16->32. Also unlike Neon, the inputs are in either the low or the high half of each double-width element. The assembler for this insn indicates the size with "P8" or "P16", encoded into bit 28 as

[PATCH for-6.2 08/53] target/arm: Fix calculation of LTP mask when LR is 0

2021-07-29 Thread Peter Maydell
In mve_element_mask(), we calculate a mask for tail predication which should have a number of 1 bits based on the value of LR. However, our MAKE_64BIT_MASK() macro has undefined behaviour when passed a zero length. Special case this to give the all-zeroes mask we require. Signed-off-by: Peter Ma

[PATCH for-6.2 06/53] target/arm: Fix 48-bit saturating shifts

2021-07-29 Thread Peter Maydell
In do_sqrshl48_d() and do_uqrshl48_d() we got some of the edge cases wrong and failed to saturate correctly: (1) In do_sqrshl48_d() we used the same code that do_shrshl_bhs() does to obtain the saturated most-negative and most-positive 48-bit signed values for the large-shift-left case. This give

[PATCH for-6.2 04/53] target/arm: Fix signed VADDV

2021-07-29 Thread Peter Maydell
A cut-and-paste error meant we handled signed VADDV like unsigned VADDV; fix the type used. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_

[PATCH for-6.2 09/53] target/arm: Factor out mve_eci_mask()

2021-07-29 Thread Peter Maydell
In some situations we need a mask telling us which parts of the vector correspond to beats that are not being executed because of ECI, separately from the combined "which bytes are predicated away" mask. Factor this mask calculation out of mve_element_mask() into its own function. Signed-off-by:

[PATCH for-6.2 15/53] target/arm: Implement MVE integer vector comparisons

2021-07-29 Thread Peter Maydell
Implement the MVE integer vector comparison instructions. These are "VCMP (vector)" encodings T1, T2 and T3, and "VPT (vector)" encodings T1, T2 and T3. These insns compare corresponding elements in each vector, and update the VPR.P0 predicate bits with the results of the comparison. VPT also se

[PATCH for-6.2 22/53] target/arm: Implement MVE VABAV

2021-07-29 Thread Peter Maydell
Implement the MVE VABAV insn, which computes absolute differences between elements of two vectors and accumulates the result into a general purpose register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h| 7 +++ target/arm/mve.decode | 6

[PATCH for-6.2 05/53] target/arm: Fix mask handling for MVE narrowing operations

2021-07-29 Thread Peter Maydell
In the MVE helpers for the narrowing operations (DO_VSHRN and DO_VSHRN_SAT) we were using the wrong bits of the predicate mask for the 'top' versions of the insn. This is because the loop works over the double-sized input elements and shifts the predicate mask by that many bits each time, but when

[PATCH for-6.2 23/53] target/arm: Implement MVE narrowing moves

2021-07-29 Thread Peter Maydell
Implement the MVE narrowing move insns VMOVN, VQMOVN and VQMOVUN. These take a double-width input, narrow it (possibly saturating) and store the result to either the top or bottom half of the output element. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h

[PATCH for-6.2 24/53] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn

2021-07-29 Thread Peter Maydell
The MVEGenDualAccOpFn is a bit misnamed, since it is used for the "long dual accumulate" operations that use a 64-bit accumulator. Rename it to MVEGenLongDualAccOpFn so we can use the former name for the 32-bit accumulator insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- t

[PATCH for-6.2 10/53] target/arm: Fix VPT advance when ECI is non-zero

2021-07-29 Thread Peter Maydell
We were not paying attention to the ECI state when advancing the VPT state. Architecturally, VPT state advance happens for every beat (see the pseudocode VPTAdvance()), so on every beat the 4 bits of VPR.P0 corresponding to the current beat are inverted if required, and at the end of beats 1 and 3

[PATCH for-6.2 07/53] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts

2021-07-29 Thread Peter Maydell
We got an edge case wrong in the 48-bit SQRSHRL implementation: if the shift is to the right, although it always makes the result smaller than the input value it might not be within the 48-bit range the result is supposed to be if the input had some bits in [63..48] set and the shift didn't bring a

[PATCH for-6.2 13/53] target/arm: Implement MVE incrementing/decrementing dup insns

2021-07-29 Thread Peter Maydell
Implement the MVE incrementing/decrementing dup insns VIDUP, VDDUP, VIWDUP and VDWDUP. These fill the elements of a vector with successively incrementing values, starting at the offset specified in a general purpose register. The final value of the offset is written back to this register. The wr

[PATCH for-6.2 26/53] target/arm: Implement MVE VMLA

2021-07-29 Thread Peter Maydell
Implement the MVE VMLA insn, which multiplies a vector by a scalar and accumulates into another vector. Signed-off-by: Peter Maydell --- Changes v1->v2: don't decode U bit --- target/arm/helper-mve.h| 4 target/arm/mve.decode | 1 + target/arm/mve_helper.c| 5 + target/arm/

[PATCH for-6.2 28/53] target/arm: Implement MVE VQABS, VQNEG

2021-07-29 Thread Peter Maydell
Implement the MVE 1-operand saturating operations VQABS and VQNEG. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h| 8 target/arm/mve.decode | 3 +++ target/arm/mve_helper.c| 37 + target/arm/tra

[PATCH for-6.2 14/53] target/arm: Factor out gen_vpst()

2021-07-29 Thread Peter Maydell
Factor out the "generate code to update VPR.MASK01/MASK23" part of trans_VPST(); we are going to want to reuse it for the VPT insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-mve.c | 31 +-- 1 file changed, 17 insertions(+),

[PATCH for-6.2 21/53] target/arm: Implement MVE integer min/max across vector

2021-07-29 Thread Peter Maydell
Implement the MVE integer min/max across vector insns VMAXV, VMINV, VMAXAV and VMINAV, which find the maximum from the vector elements and a general purpose register, and store the maximum back into the general purpose register. These insns overlap with VRMLALDAVH (they use what would be RdaHi=0b1

[PATCH for-6.2 29/53] target/arm: Implement MVE VMAXA, VMINA

2021-07-29 Thread Peter Maydell
Implement the MVE VMAXA and VMINA insns, which take the absolute value of the signed elements in the input vector and then accumulate the unsigned max or min into the destination vector. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h| 8 ta

[PATCH for-6.2 30/53] target/arm: Implement MVE VMOV to/from 2 general-purpose registers

2021-07-29 Thread Peter Maydell
Implement the MVE VMOV forms that move data between 2 general-purpose registers and 2 32-bit lanes in a vector register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 1 + target/arm/mve.decode | 4 ++ target/arm/translate-mve.c | 85 +++

[PATCH for-6.2 36/53] target/arm: Implement MVE VADD (floating-point)

2021-07-29 Thread Peter Maydell
Implement the MVE VADD (floating-point) insn. Handling of this is similar to the 2-operand integer insns, except that we must take care to only update the floating point exception status if the least significant bit of the predicate mask for each element is active. Signed-off-by: Peter Maydell -

[PATCH for-6.2 17/53] target/arm: Implement MVE VPSEL

2021-07-29 Thread Peter Maydell
Implement the MVE VPSEL insn, which sets each byte of the destination vector Qd to the byte from either Qn or Qm depending on the value of the corresponding bit in VPR.P0. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h| 2 ++ target/arm/mve.decode

[PATCH for-6.2 33/53] target/arm: Implement MVE scatter-gather insns

2021-07-29 Thread Peter Maydell
Implement the MVE gather-loads and scatter-stores which form the address by adding a base value from a scalar register to an offset in each element of a vector. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v2: UNDEF the UNPREDICTABLE Qd==Qm case for loads --- target/arm/helpe

[PATCH for-6.2 16/53] target/arm: Implement MVE integer vector-vs-scalar comparisons

2021-07-29 Thread Peter Maydell
Implement the MVE integer vector comparison instructions that compare each element against a scalar from a general purpose register. These are "VCMP (vector)" encodings T4, T5 and T6 and "VPT (vector)" encodings T4, T5 and T6. We have to move the decodetree pattern for VPST, because it overlaps w

[PATCH for-6.2 19/53] target/arm: Implement MVE shift-by-scalar

2021-07-29 Thread Peter Maydell
Implement the MVE instructions which perform shifts by a scalar. These are VSHL T2, VRSHL T2, VQSHL T1 and VQRSHL T2. They take the shift amount in a general purpose register and shift every element in the vector by that amount. Mostly we can reuse the helper functions for shift-by-immediate; we

[PATCH for-6.2 18/53] target/arm: Implement MVE VMLAS

2021-07-29 Thread Peter Maydell
Implement the MVE VMLAS insn, which multiplies a vector by a vector and adds a scalar. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- changes: don't decode U bit as it does not affect output values --- target/arm/helper-mve.h| 4 target/arm/mve.decode | 3 +++ t

[PATCH for-6.2 34/53] target/arm: Implement MVE scatter-gather immediate forms

2021-07-29 Thread Peter Maydell
Implement the MVE VLDR/VSTR insns which do scatter-gather using base addresses from Qm plus or minus an immediate offset (possibly with writeback). Note that writeback is not predicated but it does have to honour ECI state, so we have to add an eci_mask check to the VSTR_SG macros (the VLDR_SG macr

[PATCH for-6.2 38/53] target/arm: Implement MVE VCADD

2021-07-29 Thread Peter Maydell
Implement the MVE VCADD insn. Note that here the size bit is the opposite sense to the other 2-operand fp insns. We don't check for the sz == 1 && Qd == Qm UNPREDICTABLE case, because that would mean we can't use the DO_2OP_FP macro in translate-mve.c. Signed-off-by: Peter Maydell --- target/a

[PATCH for-6.2 25/53] target/arm: Implement MVE VMLADAV and VMLSLDAV

2021-07-29 Thread Peter Maydell
Implement the MVE VMLADAV and VMLSLDAV insns. Like the VMLALDAV and VMLSLDAV insns already implemented, these accumulate multiplied vector elements; but they accumulate a 32-bit result rather than a 64-bit one. Note that these encodings overlap with what would be RdaHi=0b111 for VMLALDAV, VMLSLDA

[PATCH for-6.2 35/53] target/arm: Implement MVE interleaving loads/stores

2021-07-29 Thread Peter Maydell
Implement the MVE interleaving load/store functions VLD2, VLD4, VST2 and VST4. VLD2 loads 16 bytes of data from memory and writes to 2 consecutive Qregs; VLD4 loads 16 bytes of data from memory and writes to 4 consecutive Qregs. The 'pattern' field in the encoding determines the offset into memor

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