On Thu, Jul 08, 2021 at 04:01:05PM -0600, Mathieu Poirier wrote:
> Hi Michael,
>
> On Wed, 7 Jul 2021 at 09:03, Michael S. Tsirkin wrote:
> >
> > From: Mathieu Poirier
> >
> > This patch adds entry for the vhost-user-rng related files.
> >
> > Signed-off-by: Mathieu Poirier
> > Message-Id: <202
On Fri, Jul 09, 2021 at 02:58:32AM -0400, Michael S. Tsirkin wrote:
> On Thu, Jul 08, 2021 at 04:01:05PM -0600, Mathieu Poirier wrote:
> > Hi Michael,
> >
> > On Wed, 7 Jul 2021 at 09:03, Michael S. Tsirkin wrote:
> > >
> > > From: Mathieu Poirier
> > >
> > > This patch adds entry for the vhost-
On Tue, Jul 06, 2021 at 02:20:57PM -0600, Mathieu Poirier wrote:
> Good day Michael,
>
> On Fri, Jul 02, 2021 at 12:27:08PM -0400, Michael S. Tsirkin wrote:
> > On Mon, Jun 14, 2021 at 02:28:37PM -0600, Mathieu Poirier wrote:
> > > This sets adds a vhost-user based random number generator (RNG),
>
On Jun 18 16:04, Gollu Appalanaidu wrote:
This will test the PMR functionality.
Signed-off-by: Gollu Appalanaidu
---
tests/qtest/nvme-test.c | 78 -
1 file changed, 77 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-te
On Thu, Jul 08, 2021 at 04:28:01PM -0400, Peter Xu wrote:
> On Thu, Jul 08, 2021 at 01:17:50AM +0300, Maxim Levitsky wrote:
> > As far as I know this looks very good.
> > Thanks for doing this!
> >
> > Reviewed-by: Maxim Levitsky
>
> Thanks!
>
> Michael - I just saw a pull req sent, so I wanted
On Jul 9 08:55, Klaus Jensen wrote:
On Jul 9 08:16, Hannes Reinecke wrote:
On 7/9/21 8:05 AM, Klaus Jensen wrote:
On Jul 7 17:49, Klaus Jensen wrote:
From: Klaus Jensen
Back in May, Hannes posted a fix[1] to re-enable NVMe PCI hotplug. We
discussed a bit back and fourth and I mentioned th
07.07.2021 21:15, Lukas Straub wrote:
s->active_disk is bs->file. Remove it and use local variables instead.
Signed-off-by: Lukas Straub
---
block/replication.c | 38 +-
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/block/replication.c b/
On Thu, Jul 08, 2021 at 11:46:11AM -0400, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
BTW is this actually a bugfix? Worth adding a Fixes tag maybe.
> ---
> CC: drjo...@redhat.com
> CC: peter.mayd...@linaro.org
> CC: shannon.zha...@gmail.com
> CC: qemu-...@nongnu.org
I think these get d
On 7/8/21 10:58 PM, Richard Henderson wrote:
> Replace uses of tcg_const_* with the allocate and free
> close together.
>
> Signed-off-by: Richard Henderson
> ---
> target/hppa/translate.c | 56 +
> 1 file changed, 18 insertions(+), 38 deletions(-)
>
> di
On 08/07/2021 21.09, Alex Bennée wrote:
The check_aligned_anonymous_unfixed_mmaps and
check_aligned_anonymous_unfixed_colliding_mmaps do a lot of mmap's and
copying of data. This is especially unfriendly to targets like hexagon
which have quite large pages and need to do sanity checks on each
mem
07.07.2021 21:15, Lukas Straub wrote:
In preparation for the next patch, initialize s->hidden_disk and
s->secondary_disk later and replace access to them with local variables
in the places where they aren't initialized yet.
Signed-off-by: Lukas Straub
Reviewed-by: Vladimir Sementsov-Ogievskiy
On Thu, 2021-07-08 at 19:20 +0200, Cornelia Huck wrote:
> On Wed, Jul 07 2021, "Cho, Yu-Chen" wrote:
>
> > the lack of target_user_arch makes it hard to fully leverage the
> > build system in order to separate user code from sysemu code.
> >
> > Provide it, so that we can avoid the proliferation
On 7/9/21 5:30 AM, Alistair Francis wrote:
> Expose the 12 interrupt pending bits in MIP as GPIO lines.
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu.c | 30 ++
> 1 file changed, 30 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 7/9/21 5:31 AM, Alistair Francis wrote:
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the external MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/intc/ibex_plic.h | 2 ++
> hw/intc/ibex_plic.c | 19 +--
On 7/9/21 5:31 AM, Alistair Francis wrote:
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the external MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/intc/sifive_plic.h | 4
> hw/intc/sifive_plic.c | 38 +
On 7/9/21 7:31 AM, Andrew Jeffery wrote:
> The logic in the handling for the control register required toggling the
> enable state for writes to stick. Rework the condition chain to allow
> sequential writes that do not update the enable state.
>
> Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog de
On 7/9/21 5:31 AM, Alistair Francis wrote:
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the timer MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/timer/ibex_timer.h | 2 ++
> hw/riscv/opentitan.c | 3 +++
> hw/time
07.07.2021 21:15, Lukas Straub wrote:
The replication driver needs access to the children block-nodes of
it's child so it can issue bdrv_make_empty() and bdrv_co_pwritev()
to manage the replication. However, it does this by directly copying
the BdrvChilds, which is wrong.
Fix this by properly at
On Fri, Jul 09 2021, Al Cho wrote:
> On Thu, 2021-07-08 at 19:20 +0200, Cornelia Huck wrote:
>> On Wed, Jul 07 2021, "Cho, Yu-Chen" wrote:
>>
>> > the lack of target_user_arch makes it hard to fully leverage the
>> > build system in order to separate user code from sysemu code.
>> >
>> > Provi
07.07.2021 21:15, Lukas Straub wrote:
Remove the workaround introduced in commit
6ecbc6c52672db5c13805735ca02784879ce8285
"replication: Avoid blk_make_empty() on read-only child".
It is not needed anymore since s->hidden_disk is guaranteed to be
writable when secondary_do_checkpoint() runs. Beca
Gitlab also provides runners with Windows, we can use them to
test compilation with MSYS2.
However, it takes quite a long time to set up the VM, so to
stay in the 1h time frame, we can only compile and check one
target here. And there is also still a problem with compiling
the multiboot.bin in pc-
Le 02/07/2021 à 00:12, Owen Anderson a écrit :
> The mapping from file-descriptors to translator functions is not guarded
> on realloc which may cause invalid function pointers to be read from a
> previously deallocated mapping.
>
> Signed-off-by: Owen Anderson
> ---
> linux-user/fd-trans.c | 1
On 09.07.21 07:28, Yang Zhong wrote:
Fixes: d5015b801340 ("softmmu/memory: Pass ram_flags to
qemu_ram_alloc_from_fd()")
Signed-off-by: Yang Zhong
Reviewed-by: David Hildenbrand
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pankaj Gupta
Reviewed-by: Peter Xu
---
hw/remote/memory.c | 2 +
On Fri, Jul 09, 2021 at 09:52:18AM +0200, Thomas Huth wrote:
> Gitlab also provides runners with Windows, we can use them to
> test compilation with MSYS2.
>
> However, it takes quite a long time to set up the VM, so to
> stay in the 1h time frame, we can only compile and check one
> target here.
On Thu, 8 Jul 2021 17:02:22 -0400
Eduardo Habkost wrote:
> On Tue, Jun 08, 2021 at 02:08:17PM +0200, Vitaly Kuznetsov wrote:
> > For the beginning, just test 'hv-passthrough' and a couple of custom
> > Hyper-V enlightenments configurations through QMP. Later, it would
> > be great to complement
On 09/07/21 03:25, Akihiko Odaki wrote:
input/output parameters respect dependencies.
Signed-off-by: Akihiko Odaki
---
meson.build| 30 +-
scripts/entitlement.sh | 10 +-
2 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/meson.b
On Thu, 08 Jul 2021 15:08:57 +0200
Markus Armbruster wrote:
> Daniel Henrique Barboza writes:
>
> > MEM_UNPLUG_ERROR is deprecated since the introduction of
> > DEVICE_UNPLUG_ERROR. Keep emitting both while the deprecation of
> > MEM_UNPLUG_ERROR is pending.
> >
> > CC: Michael S. Tsirkin
> >
On 7/9/21 8:55 AM, Klaus Jensen wrote:
On Jul 9 08:16, Hannes Reinecke wrote:
On 7/9/21 8:05 AM, Klaus Jensen wrote:
On Jul 7 17:49, Klaus Jensen wrote:
From: Klaus Jensen
Back in May, Hannes posted a fix[1] to re-enable NVMe PCI hotplug. We
discussed a bit back and fourth and I mentioned
On Friday, July 9, 2021 2:31 AM, Peter Xu wrote:
> > > Yes I think this is the place I didn't make myself clear. It's not
> > > about sleeping, it's about the cmpxchg being expensive already when the vm
> is huge.
> >
> > OK.
> > How did you root cause that it's caused by cmpxchg, instead of lock
On Fri, 9 Jul 2021 03:11:52 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Jul 08, 2021 at 11:46:11AM -0400, Igor Mammedov wrote:
> > Signed-off-by: Igor Mammedov
>
> BTW is this actually a bugfix? Worth adding a Fixes tag maybe.
I don't think I've made any fixes in this patch, maybe you are
tal
Le 10/06/2021 à 11:29, Thomas Huth a écrit :
> On 10/06/2021 10.50, Markus Armbruster wrote:
>> Commit c6ecec43b2 "qemu-option: Check return value instead of @err
>> where convenient" simplified
>>
>> opts = qemu_opts_create(list, qdict_get_try_str(qdict, "id"), 1,
>>
On Thu, 8 Jul 2021 14:38:08 -0400
Stefan Berger wrote:
> Cc: Michael S. Tsirkin
> Cc: Igor Mammedov
> Signed-off-by: Stefan Berger
> ---
> tests/data/acpi/q35/DSDT.tis.tpm2 | 0
> tests/data/acpi/q35/TPM2.tis.tpm2 | 0
> tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
On Thu, 8 Jul 2021 14:38:09 -0400
Stefan Berger wrote:
> Cc: Michael S. Tsirkin
> Cc: Igor Mammedov
> Signed-off-by: Stefan Berger
Reviewed-by: Igor Mammedov
> ---
> tests/qtest/bios-tables-test.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/tests/qtest/bios
On Thu, 8 Jul 2021 14:38:10 -0400
Stefan Berger wrote:
> Cc: Michael S. Tsirkin
> Cc: Igor Mammedov
> Signed-off-by: Stefan Berger
Acked-by: Igor Mammedov
> ---
> tests/data/acpi/q35/DSDT.tis| Bin 8465 -> 0 bytes
> tests/data/acpi/q35/DSDT.tis.tpm2 | Bin 0 -> 84
Le 21/06/2021 à 14:17, Philippe Mathieu-Daudé a écrit :
> On 6/21/21 12:13 PM, Laurent Vivier wrote:
>> Le 21/06/2021 à 12:08, Philippe Mathieu-Daudé a écrit :
>>> Hi Laurent,
>>>
>>> On 6/7/21 1:29 PM, Laurent Vivier wrote:
Le 07/06/2021 à 10:28, Philippe Mathieu-Daudé a écrit :
> On 6/7/
Le 29/06/2021 à 07:14, Philippe Mathieu-Daudé a écrit :
> Fix "havn't (make)" -> "haven't (made)" typo.
>
> Reviewed-by: Luis Pires
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/usb/desc-msos.c | 2 +-
> target/s390x/translate.c | 6 --
> tcg/tcg-op.c | 2 +-
>
Le 01/07/2021 à 23:11, Hubert Jasudowicz a écrit :
> From: Hubert Jasudowicz
>
> Signed-off-by: Hubert Jasudowicz
> ---
> tools/virtiofsd/fuse_virtio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/virtiofsd/fuse_virtio.c b/tools/virtiofsd/fuse_virtio.c
> index
Le 06/07/2021 à 11:55, Philippe Mathieu-Daudé a écrit :
> Cc'ing qemu-trivial@
>
> On 7/6/21 11:44 AM, Li Zhijian wrote:
>> Signed-off-by: Li Zhijian
>> ---
>> migration/rdma.c | 2 +-
>> softmmu/cpus.c | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/migration/rd
Le 06/07/2021 à 12:04, Philippe Mathieu-Daudé a écrit :
> Hi Michael, since I asked a modification on v1, I suppose
> this patch is somehow worth in documentation, so I'm
> pinging again. It could go via qemu-trival if you ack it.
>
> On 6/21/21 12:06 PM, Philippe Mathieu-Daudé wrote:
>> ping?
Ap
Le 06/07/2021 à 10:18, Thomas Huth a écrit :
> The errno numbers are very large on Haiku, so the linking currently
> fails there with a "final link failed: memory exhausted" error
> message. We should not use the errno number as array indexes here,
> thus convert the code to a switch-case statement
On Wed, 7 Jul 2021, Mark Cave-Ayland wrote:
> > You don't need a rootfs to see the jazzsonic driver messages. But if
> > you still want one, you could try the mipsel builds from these distros
> > (not the 64-bit ones):
> >
> > https://ftp.jaist.ac.jp/pub/Linux/Gentoo/experimental/mips/stages/
Le 08/07/2021 à 18:21, Olaf Hering a écrit :
> Fixes commit 3d0684b2ad82a5dde68e3f08b0d7786dccaf619c ("ram: Update
> all functions comments")
>
> Signed-off-by: Olaf Hering
> ---
> migration/ram.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/migration/ram.c b/migrati
On Wed, 7 Jul 2021 15:40:30 +0200
Michal Privoznik wrote:
> When parsing cpus= attribute of -numa object couple of checks
> is performed, such as correct initiator setting (see the if()
> statement at the end of for() loop in
> machine_set_cpu_numa_node()).
>
> However, with the current code cp
Hi experts,
When I used qemu6.0 to boot a VM, then I found that it will hang after I
execute "reboot" command. With a long time waiting, It didn't reboot and
leave the message as blow:
cut here
root@qemux86-64:~# reboot
Broadcast message from root@qemux86-64 (ttyS0) (Fri
On Wed, 7 Jul 2021 15:40:29 +0200
Michal Privoznik wrote:
> When setting up NUMA with HMAT enabled there's a check performed
> in machine_set_cpu_numa_node() that reports an error when a NUMA
> node has a CPU but the node's initiator is not itself. The error
> message reported contains only the
On 7/9/21 11:26 AM, Igor Mammedov wrote:
> On Wed, 7 Jul 2021 15:40:30 +0200
> Michal Privoznik wrote:
>
>> When parsing cpus= attribute of -numa object couple of checks
>> is performed, such as correct initiator setting (see the if()
>> statement at the end of for() loop in
>> machine_set_cpu_n
According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case
since GIC_NCPU == 8.
For SPI, make the interrupt pending on all CPUs and not just the processor
targets of the interrupt.
This behaviour is
08.07.2021 04:29, Eric Blake wrote:
This is mostly a convenience factor as one could already use 'qemu-img
info' to learn which bitmaps are broken and then 'qemu-img bitmap
--remove' to nuke them before calling 'qemu-img convert --bitmaps',
but it does have the advantage that the copied file is u
On Jul 9 10:51, Hannes Reinecke wrote:
> On 7/9/21 8:55 AM, Klaus Jensen wrote:
> > On Jul 9 08:16, Hannes Reinecke wrote:
> > > On 7/9/21 8:05 AM, Klaus Jensen wrote:
> > > > On Jul 7 17:49, Klaus Jensen wrote:
> > > > > From: Klaus Jensen
> > > > >
> > > > > Back in May, Hannes posted a fix[
Am 08.07.2021 um 20:23 hat Peter Lieven geschrieben:
> Am 08.07.2021 um 14:18 schrieb Kevin Wolf :
> > Am 07.07.2021 um 20:13 hat Peter Lieven geschrieben:
> >>> Am 06.07.2021 um 17:25 schrieb Kevin Wolf :
> >>> Am 06.07.2021 um 16:55 hat Peter Lieven geschrieben:
> I will have a decent look a
Richard Henderson writes:
> On 7/8/21 12:09 PM, Alex Bennée wrote:
>> -for (i = 0; i < 0x1fff; i++)
>> +for (i = 0; i < 0x1ff; i++)
>> {
>> size_t len;
>> len = pagesize + (pagesize * i & 7);
>
> There's really no point in i >= 8.
>
> We release all of the
Am 08.07.2021 um 17:52 hat Eric Blake geschrieben:
> When removeing support for qemu-img being able to create backing
> chains without embedded backing formats, we caused a poor error
> message as caught by iotest 114. Improve the situation to inform the
> user what went wrong.
>
> Suggested-by:
From: Sean Christopherson
EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
SGX (Software Guard Extensions). The SDM desribes EPC as:
The Enclave Page Cache (EPC) is the secure storage used to store
enclave pages when they are a part of an executing enclave. For an
From: Sean Christopherson
Add a new RAMBlock flag to denote "protected" memory, i.e. memory that
looks and acts like RAM but is inaccessible via normal mechanisms,
including DMA. Use the flag to skip protected memory regions when
mapping RAM for DMA in VFIO.
Signed-off-by: Sean Christopherson
From: Sean Christopherson
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
h
From: Sean Christopherson
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
enabled
Since Sean Christopherson has left Intel and i am responsible for Qemu SGX
upstream work. His @intel.com address will be bouncing and his new email(
sea...@google.com) is also in CC lists.
This series is Qemu SGX virtualization implementation rebased on latest
Qemu release. The numa support for SG
Add the new 'memory-backend-epc' user creatable QOM object in
the ObjectOptions to support SGX since v6.1, or the sgx backend
object cannot bootup.
Signed-off-by: Yang Zhong
v1-->v2:
- Added the new MemoryBackendEpcProperties and related documents,
and updated the blurb(Eric Blake).
---
From: Sean Christopherson
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL
when the features are exposed to the guest. Our design is the SGX
Launch Control bit will be unconditionally set in FEATURE_CONTROL,
which is unlike host bios.
Signed-off-by: Sean Christopherson
Signed-
From: Sean Christopherson
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible
Launch Control.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/kvm/kvm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/k
From: Sean Christopherson
SGX EPC is enumerated through CPUID, i.e. EPC "devices" need to be
realized prior to realizing the vCPUs themselves, which occurs long
before generic devices are parsed and realized. Because of this,
do not allow 'sgx-epc' devices to be instantiated after vCPUS have
bee
From: Sean Christopherson
On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.
KV
From: Sean Christopherson
Note that SGX EPC is currently guaranteed to reside in a single
contiguous chunk of memory regardless of the number of EPC sections.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc.c | 4
1 file changed, 4 insertions(+)
diff --git a/
From: Sean Christopherson
Expose SGX to the guest if and only if KVM is enabled and supports
virtualization of SGX. While the majority of ENCLS can be emulated to
some degree, because SGX uses a hardware-based root of trust, the
attestation aspects of SGX cannot be emulated in software, i.e.
ult
From: Sean Christopherson
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic EP
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc_piix.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 30b8bd6ea9..c
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc_q35.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 46a0f196f4..656fc
From: Sean Christopherson
If the guest want to fully use SGX, the guest needs to be able to
access provisioning key. Add a new KVM_CAP_SGX_ATTRIBUTE to KVM to
support provisioning key to KVM guests.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/cpu.c |
From: Sean Christopherson
CPUID leaf 12_0_EBX is an Intel-defined feature bits leaf enumerating
the platform's SGX extended capabilities. Currently there is a single
capabilitiy:
- EXINFO: record information about #PFs and #GPs in the enclave's SSA
Signed-off-by: Sean Christopherson
Signed
The Qemu should enable bit mask macro like Linux did in the
kernel, the GENMASK(h, l) and GENMASK_ULL(h, l) will set the
bit to 1 from l to h bit in the 32 bit or 64 bit long type.
Signed-off-by: Yang Zhong
---
include/qemu/bitops.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/incl
If qemu cmdline set the prealloc property for sgx epc and VM do the
reset the prealloc property will be different with cmdline settings.
This patch can make sure same prealloc property setting with cmdline.
Signed-off-by: Yang Zhong
---
backends/hostmem-epc.c | 10 ++
1 file changed, 10
From: Sean Christopherson
SGX capabilities are enumerated through CPUID_0x12.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d5c0f5dba2..4172081cee 100644
-
From: Sean Christopherson
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the e
Add new CONFIG_SGX for sgx support in the Qemu, and the Kconfig
default enable sgx in the i386 platform.
Signed-off-by: Yang Zhong
---
backends/meson.build | 2 +-
default-configs/devices/i386-softmmu.mak | 1 +
hw/i386/Kconfig | 5 +
hw/i386/m
The command can be used to show the SGX information in the monitor
when SGX is enabled on intel platform.
Signed-off-by: Yang Zhong
---
hmp-commands-info.hx | 15 +++
include/monitor/hmp.h | 1 +
monitor/hmp-cmds.c| 6 ++
3 files changed, 22 insertions(+)
diff --git a/hmp
From: Sean Christopherson
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
For multiple virtual EPC sections, we just put them together physically
contiguous for the simplicity
From: Sean Christopherson
The SGX sub-leafs are enumerated at CPUID 0x12. Indices 0 and 1 are
always present when SGX is supported, and enumerate SGX features and
capabilities. Indices >=2 are directly correlated with the platform's
EPC sections. Because the number of EPC sections is dynamic a
Igor Mammedov writes:
> On Thu, 08 Jul 2021 15:08:57 +0200
> Markus Armbruster wrote:
>
>> Daniel Henrique Barboza writes:
>>
>> > MEM_UNPLUG_ERROR is deprecated since the introduction of
>> > DEVICE_UNPLUG_ERROR. Keep emitting both while the deprecation of
>> > MEM_UNPLUG_ERROR is pending.
>>
Since there is no fill_device_info() callback support, and when we
execute "info memory-devices" command in the monitor, the segfault
will be found.
This patch will add this callback support and "info memory-devices"
will show sgx epc memory exposed to guest. The result as below:
qemu) info memor
If the VM is reset, we need make sure sgx virt epc in clean status.
Once the VM is reset, and sgx epc virt device will be reseted by
reset callback registered by qemu_register_reset(). Since this epc
virt device depend on backend, this reset will call backend reset
interface to re-mmap epc to guest
From: Sean Christopherson
The ACPI Device entry for SGX EPC is essentially a hack whose primary
purpose is to provide software with a way to autoprobe SGX support,
e.g. to allow software to implement SGX support as a driver. Details
on the individual EPC sections are not enumerated through ACPI
From: Sean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
docs/intel-sgx.txt | 167 +
1 file changed, 167 insertions(+)
create mode 100644 docs/intel-sgx.txt
diff --git a/docs/intel-sgx.txt b/docs/intel-sgx.txt
new
Since bios do the reset when qemu boot up, and sgx epc will be
reset by the registered reset callback function. Like this, the
sgx epc will do two times initialization. This patch will check
protected mode from cr0 register, and will bypass reset operation
from bios. The reset callback will only ac
On Thu, Jul 08, 2021 at 08:07:44PM +0100, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Wed, Jul 07, 2021 at 09:47:31PM +0200, David Hildenbrand wrote:
> > > On 07.07.21 21:19, Michael S. Tsirkin wrote:
> > > > On Wed, Jul 07, 2021 at 09:14:00PM +0200, David H
Add the sgx_memory_backend_reset() interface to handle EPC backend
reset when VM is reset. This reset function will destroy previous
backend memory region and re-mmap the EPC section for guest.
Signed-off-by: Yang Zhong
---
backends/hostmem-epc.c | 16
include/hw/i386/pc.h |
This QMP query command can be used by some userspaces to retrieve
the SGX information when SGX is enabled on Intel platform.
Signed-off-by: Yang Zhong
v1-->v2:
- "Since: 5.1" to "Since: 6.1", and grammar error(Eric Blake).
---
monitor/qmp-cmds.c | 6 ++
qapi/misc.json
Add the sgx_get_info() interface for hmp and QMP usage, which
will get the SGX info from this API.
Signed-off-by: Yang Zhong
---
hw/i386/sgx.c | 23 +++
include/hw/i386/pc.h | 1 +
include/hw/i386/sgx-epc.h | 1 +
monitor/hmp-cmds.c| 20
Libvirt can use qmp_query_sgx_capabilities() to get the host
sgx capabilities.
Signed-off-by: Yang Zhong
v1-->v2:
- Changed the blurb error and "Since: 5.1" to "Since: 6.1"(Eric Blake).
---
hw/i386/sgx.c | 66 ++
include/hw/i386/pc.h |
On Fri, 9 Jul 2021 10:11:15 +0300
Vladimir Sementsov-Ogievskiy wrote:
> 07.07.2021 21:15, Lukas Straub wrote:
> > s->active_disk is bs->file. Remove it and use local variables instead.
> >
> > Signed-off-by: Lukas Straub
> > ---
> > block/replication.c | 38 +--
On Fri, Jul 9, 2021 at 11:38 AM Alistair Francis
wrote:
>
> OpenTitan has an alias of flash avaliable which is called virtual flash.
typo: available
> Add support for that in the QEMU model.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/riscv/opentitan.h | 2 ++
> hw/riscv/opentitan.c
Save/restore with TrustZone enabled is stil broken.
** Changed in: qemu
Status: Expired => New
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https://bugs.launchpad.net/bugs/1839807
Title:
Snapshots freeze guest Sabrelite
As it happens, in April 2021 commit 335b6389374a53e0 bumped our u-boot
rom to v2021.04 to fix a PCI issue.
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https://bugs.launchpad.net/bugs/1836136
Title:
u-boot: any plans to update u
From: Ilya Dryomov
Jason has moved on from working on RBD and Ceph. I'm taking over
his role upstream.
Signed-off-by: Ilya Dryomov
Message-Id: <20210519112513.19694-1-idryo...@gmail.com>
Acked-by: Stefano Garzarella
Signed-off-by: Kevin Wolf
---
MAINTAINERS | 2 +-
1 file changed, 1 inserti
From: Peter Lieven
Ceph Luminous (version 12.2.z) is almost 4 years old at this point.
Bump the requirement to get rid of the ifdef'ry in the code.
Qemu 6.1 dropped the support for RHEL-7 which was the last supported
OS that required an older librbd.
Signed-off-by: Peter Lieven
Reviewed-by: Ily
The following changes since commit 9db3065c62a983286d06c207f4981408cf42184d:
Merge remote-tracking branch
'remotes/vivier2/tags/linux-user-for-6.1-pull-request' into staging (2021-07-08
16:30:18 +0100)
are available in the Git repository at:
git://repo.or.cz/qemu/kevin.git tags/for-upstrea
From: Peter Lieven
librbd supports 1 byte alignment for all aio operations.
Currently, there is no API call to query limits from the Ceph
ObjectStore backend. So drop the bdrv_refresh_limits completely
until there is such an API call.
Signed-off-by: Peter Lieven
Reviewed-by: Ilya Dryomov
Mes
From: Peter Lieven
While at it just call rbd_get_size and avoid rbd_image_info_t.
Signed-off-by: Peter Lieven
Reviewed-by: Ilya Dryomov
Message-Id: <20210702172356.11574-4-idryo...@gmail.com>
Signed-off-by: Kevin Wolf
---
block/rbd.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
From: Peter Lieven
This patch wittingly sets BDRV_REQ_NO_FALLBACK and silently ignores
BDRV_REQ_MAY_UNMAP for older librbd versions.
The rationale for this is as follows (citing Ilya Dryomov current RBD
maintainer):
---8<---
a) remove the BDRV_REQ_MAY_UNMAP check in qemu_rbd_co_pwrite_zeroes()
From: Or Ozeri
Starting from ceph Pacific, RBD has built-in support for image-level encryption.
Currently supported formats are LUKS version 1 and 2.
There are 2 new relevant librbd APIs for controlling encryption, both expect an
open image context:
rbd_encryption_format: formats an image (i.e.
From: Max Reitz
Allow changing the file mode, UID, and GID through SETATTR.
Without allow_other, UID and GID are not allowed to be changed, because
it would not make sense. Also, changing group or others' permissions
is not allowed either.
For read-only exports, +w cannot be set.
Signed-off-b
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