On 01/07/2021 16:25, Richard Henderson wrote:
Based-on: <20210630183226.3290849-1-richard.hender...@linaro.org>
("[PATCH v2 00/28] accel/tcg: Introduce translator_use_goto_tb")
This is my attempt at fixing #404 ("windows xp boot takes much longer...").
I don't actually have windows xp availabl
On Thu, Jun 17, 2021 at 09:07:33PM +0200, Julia Suvorova wrote:
> PCI Express does not allow hot-plug on pcie.0. Check for Q35 in
> acpi_pcihp_disable_root_bus() to be able to forbid hot-plug using the
> 'acpi-root-pci-hotplug' flag.
>
> Signed-off-by: Julia Suvorova
> Reviewed-by: Igor Mammedov
01.07.2021 22:06, Eric Blake wrote:
The recently-added NBD context qemu:allocation-depth is able to
distinguish between locally-present data (even when that data is
sparse) [shown as depth 1 over NBD], and data that could not be found
anywhere in the backing chain [shown as depth 0]; and the libn
On Fri, Jul 02, 2021 at 06:52:34PM -0300, Fabiano Rosas wrote:
> ../target/ppc/mmu_helper.c: In function 'helper_store_ibatu':
> ../target/ppc/mmu_helper.c:1802:17: error: unused variable 'cpu'
> [-Werror=unused-variable]
> 1802 | PowerPCCPU *cpu = env_archcpu(env);
> |
On Fri, Jul 02, 2021 at 06:52:35PM -0300, Fabiano Rosas wrote:
> ../target/ppc/mmu-hash32.c: In function 'ppc_hash32_bat_lookup':
> ../target/ppc/mmu-hash32.c:204:13: error: 'BATu' undeclared (first use in
> this function);
> 204 | BATu = &BATut[i];
> | ^~~~
>
On Fri, Jul 02, 2021 at 06:52:33PM -0300, Fabiano Rosas wrote:
> ../target/ppc/mmu_helper.c: In function 'get_segment_6xx_tlb':
> ../target/ppc/mmu_helper.c:514:46: error: passing argument 1 of
> 'ppc_hash32_hpt_mask' from incompatible pointer type
> [-Werror=incompatible-pointer-types]
>
> 514
CC'ing NetBSD maintainers.
On 6/23/21 8:00 PM, Philippe Mathieu-Daudé wrote:
> Avocado allows us to select set of tests using tags.
> When wanting to run all tests using a NetBSD guest OS,
> it is convenient to have them tagged, add the 'os:netbsd'
> tag.
>
> Signed-off-by: Philippe Mathieu-Daudé
On Sat, Jul 3, 2021 at 10:41 AM Philippe Mathieu-Daudé wrote:
>
> CC'ing NetBSD maintainers.
>
> On 6/23/21 8:00 PM, Philippe Mathieu-Daudé wrote:
> > Avocado allows us to select set of tests using tags.
> > When wanting to run all tests using a NetBSD guest OS,
> > it is convenient to have them t
On 7/3/21 8:32 AM, Mark Cave-Ayland wrote:
> On 02/07/2021 14:03, Philippe Mathieu-Daudé wrote:
> What was the issue with patch 9 "dp8393x: fix CAM descriptor entry
> index"? That patch ensures that the CAM index is read from the
> descriptor, and not taken from the for() loop i.e. it is unrelated
On 7/3/21 8:21 AM, Mark Cave-Ayland wrote:
> On 02/07/2021 05:36, Finn Thain wrote:
>
>>> On 6/25/21 8:53 AM, Mark Cave-Ayland wrote:
Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that
all accesses to the registers were 32-bit
>>
>> No, that assumption was not made ther
Ping :)
This still applies to master with no conflicts. All patches reviewed except for
08.
24.05.2021 17:20, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
Here are some good refactorings and new (qemu-img check) checks for
qcow2.
v3: add r-b mark by Alberto and t-b marks by Kirill
07, 09:
On 03/07/2021 09:52, Philippe Mathieu-Daudé wrote:
On 7/3/21 8:21 AM, Mark Cave-Ayland wrote:
On 02/07/2021 05:36, Finn Thain wrote:
On 6/25/21 8:53 AM, Mark Cave-Ayland wrote:
Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that
all accesses to the registers were 32-bit
No
On 6/25/21 8:54 AM, Mark Cave-Ayland wrote:
> Currently when a LOAD CAM command is executed the entries are loaded into the
> CAM from memory in order which is incorrect. According to the datasheet the
> first entry in the CAM descriptor is the entry index which means that each
> descriptor may upd
On 7/3/21 2:04 PM, Mark Cave-Ayland wrote:
> On 03/07/2021 09:52, Philippe Mathieu-Daudé wrote:
>> On 7/3/21 8:21 AM, Mark Cave-Ayland wrote:
>>> On 02/07/2021 05:36, Finn Thain wrote:
>>>
> On 6/25/21 8:53 AM, Mark Cave-Ayland wrote:
>> Commit 3fe9a838ec "dp8393x: Always use 32-bit accesse
Let's document how we use file locks in file-posix driver, to allow
external programs to "communicate" in this way with Qemu.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
v2: improve some descriptions
add examples
add notice about old bad POSIX file locks
docs/system/qemu-block-driv
On 03/07/2021 14:10, Philippe Mathieu-Daudé wrote:
On 7/3/21 2:04 PM, Mark Cave-Ayland wrote:
On 03/07/2021 09:52, Philippe Mathieu-Daudé wrote:
On 7/3/21 8:21 AM, Mark Cave-Ayland wrote:
On 02/07/2021 05:36, Finn Thain wrote:
On 6/25/21 8:53 AM, Mark Cave-Ayland wrote:
Commit 3fe9a838ec "
Housekeeping while reviewing Mark's "fixes for MacOS toolbox ROM"
series v2.
RFC because totally untested =) Just compiled.
Mark Cave-Ayland (2):
dp8393x: fix CAM descriptor entry index
dp8393x: don't force 32-bit register access
Philippe Mathieu-Daudé (4):
dp8393x: Restrict bus access to 1
From: Mark Cave-Ayland
Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that all
accesses
to the registers were 32-bit but this is actually not the case. The access size
is
determined by the CPU instruction used and not the number of physical address
lines.
The big_endian worka
Instead of accessing N registers via a single address_space API
call using a temporary buffer (stored in the device state) and
updating each register, move the address_space call in the
register put/get. The load/store and word size checks are moved
to put/get too. This simplifies a bit, making the
From: Mark Cave-Ayland
Currently when a LOAD CAM command is executed the entries are loaded into the
CAM from memory in order which is incorrect. According to the datasheet the
first entry in the CAM descriptor is the entry index which means that each
descriptor may update any single entry in the
Per the DP83932C datasheet from July 1995:
1. Functional Description
1.3 DATA WIDTH AND BYTE ORDERING
The SONIC can be programmed to operate with
either 32-bit or 16-bit wide memory.
Restrict the memory bus to reject 8/64-bit accesses.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/
On 7/3/21 4:16 PM, Mark Cave-Ayland wrote:
> On 03/07/2021 14:10, Philippe Mathieu-Daudé wrote:
>> On 7/3/21 2:04 PM, Mark Cave-Ayland wrote:
>>> I've tested this under Linux/m68k, NetBSD/arc and MacOS and networking
>>> seems fine after a quick test in each OS. The slight curiosity is that
>>> th
Per the DP83932C datasheet from July 1995:
4.0 SONIC Registers
4.1 THE CAM UNIT
The Content Addressable Memory (CAM) consists of sixteen
48-bit entries for complete address filtering of network
packets. Each entry corresponds to a 48-bit destination
address that is user progra
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index e0055b178b1..bbe241ef9db 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -814,8 +814,8 @@ static ssize_t dp8393x
Hi, I'm hitting build errors with clang on i686 userspace on x86_64
kernel. Affects both qemu 6.0.0 and qemu.git, tested with fedora
clang-12.0.1~rc3-1.fc35.i686.
Full build log from the 6.0.0 build:
https://gist.githubusercontent.com/crobinso/7b1206044eac7326490b2adce829e861/raw/9dddef968051fd638
On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
From: Mark Cave-Ayland
Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that all
accesses
to the registers were 32-bit but this is actually not the case. The access size
is
determined by the CPU instruction used and not the nu
On Sat, Jul 3, 2021 at 4:51 PM Vladimir Sementsov-Ogievskiy
wrote:
>
> Let's document how we use file locks in file-posix driver, to allow
> external programs to "communicate" in this way with Qemu.
This makes the locking implementation public, so qemu can never change
it without breaking externa
On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
Per the DP83932C datasheet from July 1995:
1. Functional Description
1.3 DATA WIDTH AND BYTE ORDERING
The SONIC can be programmed to operate with
either 32-bit or 16-bit wide memory.
Restrict the memory bus to reject 8/64-bit
On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
Per the DP83932C datasheet from July 1995:
4.0 SONIC Registers
4.1 THE CAM UNIT
The Content Addressable Memory (CAM) consists of sixteen
48-bit entries for complete address filtering of network
packets. Each entry correspo
On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index e0055b178b1..bbe241ef9db 100644
--- a/hw/net/dp8393x.c
+++ b/hw/
On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
Instead of accessing N registers via a single address_space API
call using a temporary buffer (stored in the device state) and
updating each register, move the address_space call in the
register put/get. The load/store and word size checks are m
Hi Mark, few more patches while reviewing.
Again, not tested (yet)... Simply compiled.
Please tell me what you think of them.
Regards,
Phil.
Philippe Mathieu-Daudé (3):
dp8393x: Store CRC using address_space_stl_le()
dp8393x: Do not amend CRC if it is inhibited (CRCI bit set)
dp8393x: St
The address_space API can handle endianess conversion.
Replace cpu_to_le32() + address_space_write() by a
single address_space_stl_le() call.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw
When the CRCI (CRC INHIBIT) bit is set, the 4-byte FCS field
is not transmitted.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 99e179a5e86..dee823640
Little-Endian CRC is dubious, and the datasheet does not specify
it being little-endian. Proceed similarly with the other memory
accesses, use the device endianess.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --gi
On 7/3/21 5:00 PM, Mark Cave-Ayland wrote:
> On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
>
>> Instead of accessing N registers via a single address_space API
>> call using a temporary buffer (stored in the device state) and
>> updating each register, move the address_space call in the
>> re
Hello,
I just wanted to ask how I can get started developing other than just
starting building? QEMU is a huge project, and getting familiar with all of
the source and stuff is a lot of work. Probably, it wouldn't be helpful to
know the entire source, but just what I need.
I want to add a new sys
On 7/3/21 4:34 PM, Cole Robinson wrote:
> Hi, I'm hitting build errors with clang on i686 userspace on x86_64
> kernel. Affects both qemu 6.0.0 and qemu.git, tested with fedora
> clang-12.0.1~rc3-1.fc35.i686.
> /builddir/build/BUILD/qemu-6.0.0/include/qemu/stats64.h:58:21: warning:
> misaligned at
On 7/3/21 4:34 PM, Cole Robinson wrote:
> Hi, I'm hitting build errors with clang on i686 userspace on x86_64
> kernel. Affects both qemu 6.0.0 and qemu.git, tested with fedora
> clang-12.0.1~rc3-1.fc35.i686.
>
> Full build log from the 6.0.0 build:
> https://gist.githubusercontent.com/crobinso/7b
On 7/3/21 6:20 PM, Philippe Mathieu-Daudé wrote:
> On 7/3/21 4:34 PM, Cole Robinson wrote:
>> Hi, I'm hitting build errors with clang on i686 userspace on x86_64
>> kernel. Affects both qemu 6.0.0 and qemu.git, tested with fedora
>> clang-12.0.1~rc3-1.fc35.i686.
>
>> /builddir/build/BUILD/qemu-6.0
On 7/3/21 4:39 PM, Mark Cave-Ayland wrote:
> On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote:
>
>> From: Mark Cave-Ayland
>>
>> Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that
>> all accesses
>> to the registers were 32-bit but this is actually not the case. The
>> access s
On Mon, Jun 29, 2020 at 09:04:01AM +0200, Eric Auger wrote:
> This patch implements the PROBE request. At the moment,
> only THE RESV_MEM property is handled. The first goal is
> to report iommu wide reserved regions such as the MSI regions
> set by the machine code. On x86 this will be the IOAPIC
On Wed, 30 Jun 2021 16:08:05 -0400
Peter Xu wrote:
> Taking the mutex every time for each dirty bit to clear is too slow,
> especially
> we'll take/release even if the dirty bit is cleared. So far it's only used to
> sync with special cases with qemu_guest_free_page_hint() against migration
> t
Pls ignore, my mail is acting up serving me old patches.
Sorry about the noise!
--
MST
On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
When the CRCI (CRC INHIBIT) bit is set, the 4-byte FCS field
is not transmitted.
You say when CRCI is 1 then no checksum...
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/dp8393x.c | 22 ++
1 file changed, 14 insertions(
On Sat, Jul 3, 2021 at 6:32 PM BALATON Zoltan wrote:
> On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
> > When the CRCI (CRC INHIBIT) bit is set, the 4-byte FCS field
> > is not transmitted.
>
> You say when CRCI is 1 then no checksum...
>
> >
> > Signed-off-by: Philippe Mathieu-Daudé
> > ---
On Tue, May 25, 2021 at 06:59:31AM +, Dov Murik wrote:
> From: James Bottomley
>
> If the VM is using memory encryption and also specifies a kernel/initrd
> or appended command line, calculate the hashes and add them to the
> encrypted data. For this to work, OVMF must support an encrypted a
On Sat, 3 Jul 2021, Kenneth Adam Miller wrote:
I just wanted to ask how I can get started developing other than just
starting building? QEMU is a huge project, and getting familiar with all of
the source and stuff is a lot of work. Probably, it wouldn't be helpful to
know the entire source, but j
On Thu, Jun 17, 2021 at 09:07:32PM +0200, Julia Suvorova wrote:
> The patch set consists of two parts:
> patches 1-4: introduce new feature
> 'acpi-pci-hotplug-with-bridge-support' on Q35
> patches 5-7: make the feature default along with changes in ACPI tables
>
> With the feature di
On Sat, 3 Jul 2021 at 15:37, Cole Robinson wrote:
>
> Hi, I'm hitting build errors with clang on i686 userspace on x86_64
> kernel. Affects both qemu 6.0.0 and qemu.git, tested with fedora
> clang-12.0.1~rc3-1.fc35.i686.
>
> Full build log from the 6.0.0 build:
> https://gist.githubusercontent.com
Hi Phil,
I spent some time trying to debug the problem with
tests/acceptance/machine_arm_n8x0.py:N8x0Machine.test_n810. Although I
could not reproduce it locally, with or without Avocado, I was able to
reproduce it without using Avocado on GitLab CI:
https://gitlab.com/willianrampazzo/qemu/-/pipe
On Thu, 17 Jun 2021 10:47:12 +0800
Lei Rao wrote:
> From: "Rao, Lei"
>
> When a PVM completed its SVM failover steps and begins to run in
> the simplex mode, QEMU would encounter a 'Segmentation fault' if
> the guest poweroff with the following calltrace:
>
> Program received signal SIGSEGV, S
For Haiku: turn off TPM, disable mips & xtensa emulators as they won't
compile on Haiku, use Haiku's capstone. I'm resending this as I previously
sent to the wrong address. This should resolve the memory issue with "make
vm-build-haiku.x86_64"
Signed-off-by: Richard Zak
---
configure | 6 +-
Fix for path to env
Signed-off-by: Richard Zak
---
Makefile | 4
1 file changed, 4 insertions(+)
diff --git a/Makefile b/Makefile
index 30f19d33bb..ced9b97372 100644
--- a/Makefile
+++ b/Makefile
@@ -14,7 +14,11 @@ SRC_PATH=.
# we have explicit rules for everything
MAKEFLAGS += -rR
+ifn
On Sat, 3 Jul 2021 at 22:10, Richard Zak wrote:
>
> For Haiku: turn off TPM, disable mips & xtensa emulators as they won't
> compile on Haiku, use Haiku's capstone. I'm resending this as I previously
> sent to the wrong address. This should resolve the memory issue with "make
> vm-build-haiku.x
For MIPS (all sub-targets, 64-bit and EL) & xtensa(eb), the compiler
complains about running out of memory. Best I can see, that's not what
actually happens, but that's the error message. I was going to investigate
this later, but this was the error which was causing the test with the
Haiku VM with
This is a test. The mailing list seems to reject my patches
--
pgp8mmJ0JCegG.pgp
Description: OpenPGP digital signature
On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
> When the CRCI (CRC INHIBIT) bit is set, the 4-byte FCS field
> is not transmitted.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/dp8393x.c | 22 ++
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --g
On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
> Hi Mark, few more patches while reviewing.
>
>
>
> Again, not tested (yet)... Simply compiled.
>
>
>
> Please tell me what you think of them.
>
>
I think these 3 patches can be reduced to this theoretical bug fix:
diff --git a/hw/net/d
Based on feedback from prior email
Signed-off-by: Richard Zak
---
configure | 4
1 file changed, 4 insertions(+)
diff --git a/configure b/configure
index e799d908a3..8384e22ba3 100755
--- a/configure
+++ b/configure
@@ -358,6 +358,7 @@ oss_lib=""
bsd="no"
linux="no"
solaris="no"
+haiku=
On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
> Instead of accessing N registers via a single address_space API
> call using a temporary buffer (stored in the device state) and
> updating each register, move the address_space call in the
> register put/get. The load/store and word size checks
On Sat, 3 Jul 2021, Philippe Mathieu-Daudé wrote:
> From: Mark Cave-Ayland
>
> Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that all
> accesses
> to the registers were 32-bit but this is actually not the case. The access
> size is
> determined by the CPU instruction used an
ping
On Mon, Jun 21, 2021 at 3:50 PM Kostiantyn Kostiuk
wrote:
> Signed-off-by: Kostiantyn Kostiuk
> ---
> qga/commands-win32.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/qga/commands-win32.c b/qga/commands-win32.c
> index 300b87c859..93b08fd4b5 100644
> --- a/q
ping
On Mon, Apr 5, 2021 at 4:14 PM Basil Salman wrote:
> Currently Requester freeze times out after 10 seconds, while
> the default timeout for Writer Freeze is 60 seconds. according to
> VSS Documentation [1].
> [1]:
> https://docs.microsoft.com/en-us/windows/win32/vss/overview-of-processing-a
Hi Michael,
[+cc Connor, Dave]
On 03/07/2021 19:42, Michael S. Tsirkin wrote:
> On Tue, May 25, 2021 at 06:59:31AM +, Dov Murik wrote:
>> From: James Bottomley
>>
>> If the VM is using memory encryption and also specifies a kernel/initrd
>> or appended command line, calculate the hashes and
On Sun, Jul 04, 2021 at 09:16:59AM +0300, Dov Murik wrote:
> Hi Michael,
>
> [+cc Connor, Dave]
>
> On 03/07/2021 19:42, Michael S. Tsirkin wrote:
> > On Tue, May 25, 2021 at 06:59:31AM +, Dov Murik wrote:
> >> From: James Bottomley
> >>
> >> If the VM is using memory encryption and also spe
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