Patchew URL:
https://patchew.org/QEMU/20210626063631.2411938-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210626063631.2411938-1-richard.hender...@linaro.org
Subject: [PATCH v3 00/29
On 6/26/21 8:36 AM, Richard Henderson wrote:
> Merge tcg_out_bswap16 and tcg_out_bswap16s. Use the flags
> in the internal uses for loads and stores.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target.c.inc | 63 +++---
On 6/26/21 8:36 AM, Richard Henderson wrote:
> For INDEX_op_bswap32_i32, pass 0 for flags: input not zero-extended,
> output does not need extension within the host 64-bit register.
>
> Cc: qemu-...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-target.c.inc | 22 +
On 6/26/21 8:36 AM, Richard Henderson wrote:
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c.inc | 12
> 1 file changed, 12 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 6/26/21 5:31 AM, Bin Meng wrote:
> On Sat, Jun 26, 2021 at 1:17 AM Philippe Mathieu-Daudé
> wrote:
>>
>> On 6/25/21 3:49 PM, Bin Meng wrote:
>>> On Thu, Jun 24, 2021 at 10:28 PM Philippe Mathieu-Daudé
>>> wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 21
On 6/25/21 3:47 PM, Bin Meng wrote:
> On Thu, Jun 24, 2021 at 10:23 PM Philippe Mathieu-Daudé
> wrote:
>>
>> Log illegal commands as GUEST_ERROR.
>>
>> Note: we are logging back the SDIO commands (CMD5, CMD52-54).
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/sd/sd.c | 57 +++
Hi Nolan, Peter,
On 6/25/21 11:02 PM, Nolan Leake wrote:
> This is just enough to make reboot and poweroff work. Works for
> linux, u-boot, and the arm trusted firmware. Not tested, but should
> work for plan9, and bare-metal/hobby OSes, since they seem to generally
> do what linux does for reset.
On Mon, Jun 21, 2021 at 4:49 PM Or Ozeri wrote:
>
> Starting from ceph Pacific, RBD has built-in support for image-level
> encryption.
> Currently supported formats are LUKS version 1 and 2.
>
> There are 2 new relevant librbd APIs for controlling encryption, both expect
> an
> open image contex
On Wed, Jun 16, 2021 at 10:56 AM LIU Zhiwei wrote:
>
> On 6/13/21 6:10 PM, Frank Chang wrote:
>
> LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道:
>
>> The Core-Local Interrupt Controller (CLIC) provides low-latency,
>> vectored, pre-emptive interrupts for RISC-V systems.
>>
>> The CLIC also supports a new S
On Fri, 25 Jun 2021, Mark Cave-Ayland wrote:
> Here is the next set of patches from my attempts to boot MacOS under
> QEMU's Q800 machine related to the Sonic network adapter.
>
> Patches 1 and 2 sort out checkpatch and convert from DPRINTF macros to
> trace-events.
>
> The discussion for the
LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道:
> The Core-Local Interrupt Controller (CLIC) provides low-latency,
> vectored, pre-emptive interrupts for RISC-V systems.
>
> The CLIC also supports a new Selective Hardware Vectoring feature
> that allow users to optimize each interrupt for either faster
> res
LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道:
> The Core-Local Interrupt Controller (CLIC) provides low-latency,
> vectored, pre-emptive interrupts for RISC-V systems.
>
> The CLIC also supports a new Selective Hardware Vectoring feature
> that allow users to optimize each interrupt for either faster
> res
Hi,
I build qemu with MingW, and after the linking, I find the qemu.exe depends on
some dlls like below, I understand the glib dependencies, but why qemu uses
libffi-6.dll, libiconv-2.dll, libpcre-1.dll libssp-0.dll, libintl-8.dll,
libpixman-1-0.dll, zlib1.dll? I just want to use TCG function an
Frank Chang 於 2021年6月26日 週六 下午11:03寫道:
> LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道:
>
>> The Core-Local Interrupt Controller (CLIC) provides low-latency,
>> vectored, pre-emptive interrupts for RISC-V systems.
>>
>> The CLIC also supports a new Selective Hardware Vectoring feature
>> that allow users t
LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道:
> The machine mode mclicbase CSR is an XLEN-bit read-only register providing
> the base address of CLIC memory mapped registers.
>
> Signed-off-by: LIU Zhiwei
> ---
> hw/intc/riscv_clic.c | 1 +
> target/riscv/cpu.h | 1 +
> 2 files changed, 2 insertions(+)
On Mon, Jun 21, 2021 at 10:49 AM Peter Lieven wrote:
>
> Am 18.06.21 um 12:34 schrieb Ilya Dryomov:
> > On Fri, Jun 18, 2021 at 11:00 AM Peter Lieven wrote:
> >> Am 16.06.21 um 14:34 schrieb Ilya Dryomov:
> >>> On Wed, May 19, 2021 at 4:28 PM Peter Lieven wrote:
> Signed-off-by: Peter Lieve
LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道:
> The Core-Local Interrupt Controller (CLIC) provides low-latency,
> vectored, pre-emptive interrupts for RISC-V systems.
>
> The CLIC also supports a new Selective Hardware Vectoring feature
> that allow users to optimize each interrupt for either faster
> res
Frank Chang 於 2021年6月27日 週日 上午1:15寫道:
> LIU Zhiwei 於 2021年4月9日 週五 下午3:57寫道:
>
>> The Core-Local Interrupt Controller (CLIC) provides low-latency,
>> vectored, pre-emptive interrupts for RISC-V systems.
>>
>> The CLIC also supports a new Selective Hardware Vectoring feature
>> that allow users to
LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道:
> The interrupt-level threshold (xintthresh) CSR holds an 8-bit field
> for the threshold level of the associated privilege mode.
>
> For horizontal interrupts, only the ones with higher interrupt levels
> than the threshold level are allowed to preempt.
>
> Si
On 6/25/21 11:02 PM, Nolan Leake wrote:
> This is just enough to make reboot and poweroff work. Works for
> linux, u-boot, and the arm trusted firmware. Not tested, but should
> work for plan9, and bare-metal/hobby OSes, since they seem to generally
> do what linux does for reset.
>
> The watchdog
When eptype is USB_ENDPOINT_XFER_CONTROL and pid is
TSIZ_SC_MC_PID_SETUP, usb_ep_get() should return the control endpoint.
In hw/usb/core.c, the assumed epnum of the control endpoint is 0. When
epnum is not 0, usb_ep_get() will crash due to the check assert(pid ==
USB_TOKEN_IN || pid == USB_TOKEN_O
Hi folks,
I found this bug by my dwc2 fuzzer.
It seems that
* https://bugs.launchpad.net/qemu/+bug/1907042
* https://bugs.launchpad.net/qemu/+bug/1525123
or
* https://gitlab.com/qemu-project/qemu/-/issues/119
* https://gitlab.com/qemu-project/qemu/-/issues/303
have reported similar issues.
Would
From: Hyman Huang(黄勇)
intrduce DIRTY_MEMORY_DIRTY_RATE dirty bits to tracking vm
dirty page for calculating dirty rate
since dirtyrate and migration may be trigger concurrently,
reusing the exsiting DIRTY_MEMORY_MIGRATION dirty bits seems
not a good choice. introduce a fresh new dirty bits for
d
From: Hyman Huang(黄勇)
introduce util functions to setup the DIRTY_MEMORY_DIRTY_RATE
dirty bits for the convenience of tracking dirty bitmap when
calculating dirtyrate.
Signed-off-by: Hyman Huang(黄勇)
---
include/exec/ram_addr.h | 121
softmmu/phy
From: Hyman Huang(黄勇)
introduce kvm_get_manual_dirty_log_protect for measureing
dirtyrate via dirty bitmap. calculation of dirtyrate need
to sync dirty log and depends on the features of dirty log.
Signed-off-by: Hyman Huang(黄勇)
---
accel/kvm/kvm-all.c | 6 ++
include/sysemu/kvm.h | 1 +
From: Hyman Huang(黄勇)
introduce dirty-bitmap mode as the third method of calc-dirty-rate.
implement dirty-bitmap dirtyrate calculation, which can be used
to measuring dirtyrate in the absence of dirty-ring.
introduce "dirty_bitmap:-b" option in hmp calc_dirty_rate to
indicate dirty bitmap method
From: Hyman Huang(黄勇)
the dirtyrate measurement implemented by page-sampling originally, it
is not accurate in some scenarios, so we have introduced dirty-ring
based dirtyrate measurement(maybe it will be merged soon), it fix the
accuracy of page-sampling, and more importantly, it is at the
granu
LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道:
> The xip CSR appears hardwired to zero in CLIC mode, replaced by separate
> memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be
> ignored and will not trap (i.e., no access faults).
>
> Signed-off-by: LIU Zhiwei
---
> target/riscv/csr.c |
LIU Zhiwei 於 2021年4月9日 週五 下午3:51寫道:
> The xie CSR appears hardwired to zero in CLIC mode, replaced by separate
> memory-mapped interrupt enables (clicintie[i]). Writes to xie will be
> ignored and will not trap (i.e., no access faults).
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/csr.c |
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