On 15/06/2021 09:57, Vladimir Sementsov-Ogievskiy wrote:
14.06.2021 13:36, Emanuele Giuseppe Esposito wrote:
On 04/06/2021 11:17, Emanuele Giuseppe Esposito wrote:
Attaching gdbserver implies that the qmp socket
should wait indefinitely for an answer from QEMU.
For Timeout class, create a
New test case enum-dict-no-name.json crashes:
$ python3 scripts/qapi-gen.py tests/qapi-schema/enum-dict-no-name.json
Traceback (most recent call last):
[...]
File "/work/armbru/qemu/scripts/qapi/expr.py", line 458, in check_enum
member_name = member['name']
KeyError:
Witherspoon uses the DPS310 as a temperature sensor. Rainier uses it as
a temperature and humidity sensor.
Signed-off-by: Joel Stanley
---
hw/arm/aspeed.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 0eafc791540d..619ad869dd71 10
v2 addresses the review from Cédric. I chose to drop the qom get/setters
as the logic was quite involved, and requires more work to get right.
This is a model for the Infineon DPS310 temperature and barometric
pressure sensor.
Joel Stanley (2):
hw/misc: Add Infineon DPS310 sensor model
arm/as
This contains some hardcoded register values that were obtained from the
hardware after reading the temperature.
It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
operation modes other than the default as used by Linux are not modelled.
Signed-off-by: Joel Stanley
---
v2:
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, June 15, 2021 7:12 PM
> To: qemu-devel@nongnu.org
> Cc: laur...@vivier.eu; alex.ben...@linaro.org; Taylor Simpson
>
> Subject: [PATCH 07/21] linux-user/hexagon: Implement setup_sigtramp
>
> Continue to initialize the word
Eduardo Habkost writes:
> On Tue, Jun 08, 2021 at 02:08:11PM +0200, Vitaly Kuznetsov wrote:
>> Currently, the only eVMCS version, supported by KVM (and described in TLFS)
>> is '1'. When Enlightened VMCS feature is enabled, QEMU takes the supported
>> eVMCS version range (from KVM_CAP_HYPERV_ENLI
Paolo Bonzini writes:
> This patch introduces a function that merges two keyval-produced
> (or keyval-like) QDicts. It can be used to emulate the behavior of
> .merge_lists = true QemuOpts groups, merging -readconfig sections and
> command-line options in a single QDict, and also to implement -s
On 16/06/2021 02:58, Richard Henderson wrote:
On 6/15/21 6:58 AM, Programmingkid wrote:
Ahh I misread - so those are the addresses of the routines and not where
it's sticking the breakpoint?
I notice from a bit of googling that there is a boot debugger. I wonder
if /nodebug in boot.ini stops t
On 6/15/21 9:28 PM, Patrick Venture wrote:
> Adds a line-item reference to the supported quanta-q71l-bmc aspeed
> entry.
>
> Signed-off-by: Patrick Venture
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> docs/system/arm/aspeed.rst | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/d
On 6/15/21 9:28 PM, Patrick Venture wrote:
> Add line item reference to quanta-gbs-bmc machine.
>
> Signed-off-by: Patrick Venture
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> docs/system/arm/nuvoton.rst | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/docs/sy
On 6/16/21 9:33 AM, Joel Stanley wrote:
> Witherspoon uses the DPS310 as a temperature sensor. Rainier uses it as
> a temperature and humidity sensor.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> hw/arm/aspeed.c | 4 ++--
> 1 file changed, 2 insertions(+
On 6/16/21 9:33 AM, Joel Stanley wrote:
> This contains some hardcoded register values that were obtained from the
> hardware after reading the temperature.
>
> It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
> operation modes other than the default as used by Linux are not
Signed-off-by: Yoshinori Sato
---
include/hw/sh4/sh.h | 8
hw/sh4/sh7750.c | 41 +
hw/sh4/Kconfig | 2 +-
3 files changed, 42 insertions(+), 9 deletions(-)
diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h
index becb596979..74e1ba5
Renesas SH/RX have various SCI in serial interface.
The design of sh_serial is old, so I integrate these SCIs with renesas_sci.
Yoshinori Sato (3):
hw/char: renesas_sci: Refactor for merge all SCI variant..
hw/char: renesas_sci Add SCI and SCIF support.
hw/sh4: sh7750 using renesas_sci.
in
On Wed, Jun 16, 2021 at 2:43 PM Lukas Jünger
wrote:
>
> This cleanes up function names in the SiFive UART model.
typo: cleans
>
> Signed-off-by: Lukas Jünger
> ---
> hw/char/sifive_uart.c | 46 ++-
> 1 file changed, 24 insertions(+), 22 deletions(-)
>
R
On Wed, Jun 16, 2021 at 2:44 PM Lukas Jünger
wrote:
>
> This QOMifies the SiFive UART model. Migration and reset have been
> implemented.
>
> Signed-off-by: Lukas Jünger
> ---
> include/hw/char/sifive_uart.h | 11 ++--
> hw/char/sifive_uart.c | 114 +++---
>
On Tue, Jun 15, 2021 at 03:35:44PM +0200, Paolo Bonzini wrote:
> On 15/06/21 15:07, Gerd Hoffmann wrote:
> > > Hmm, looks like I actually need both. Seems there is no easy way to get
> > > the cflags out of a source_set to construct a cpp command line. Pulling
> > > this out of compile_commands.j
This peripheral using SH7750.
Signed-off-by: Yoshinori Sato
---
include/hw/char/renesas_sci.h | 43 ++-
hw/char/renesas_sci.c | 489 ++
2 files changed, 531 insertions(+), 1 deletion(-)
diff --git a/include/hw/char/renesas_sci.h b/include/hw/char/renesas
In order to handle unified all of the SCI, SCIa and SCIF in one part,
to separate the transmission and reception portion and a register portion.
RenesasSCIBase - common registers operation and event handling.
RenesasSCIA - SCIa specific reigisters / functions.
Signed-off-by: Yoshinori Sato
---
Hi,
> Should I send this patch with tag V2?
Yes, please.
thanks,
Gerd
This cleans up function names in the SiFive UART model.
Signed-off-by: Lukas Jünger
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/char/sifive_uart.c | 46 ++-
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/hw/char/sifive_uar
Hello,
I cleaned up the commit message as requested by Bin.
Best regards,
Lukas
Lukas Jünger (2):
hw/char: Consistent function names for sifive_uart
hw/char: QOMify sifive_uart
include/hw/char/sifive_uart.h | 11 ++-
hw/char/sifive_uart.c | 152 +++---
On Wed, 16 Jun 2021 at 09:09, Cédric Le Goater wrote:
> On 6/16/21 9:33 AM, Joel Stanley wrote:
> > +typedef struct DPS310State {
> > +/*< private >*/
> > +I2CSlave i2c;
> > +
> > +/*< public >*/
> > +uint8_t regs[NUM_REGISTERS];
> > +
> > +int16_t pressure, temperature;
>
>
>
> > Hmm, what would be the use case? Right now qemu has the all-or-nothing
> > approach for modules, i.e. if modules are enabled everything we can
> > build as module will be built as module, and I havn't seen any drawbacks
> > so far. So, why would one compile parts of qemu as module and other
>
This QOMifies the SiFive UART model. Migration and reset have been
implemented.
Signed-off-by: Lukas Jünger
Reviewed-by: Bin Meng
---
include/hw/char/sifive_uart.h | 11 ++--
hw/char/sifive_uart.c | 114 +++---
2 files changed, 109 insertions(+), 16 deletion
Patchew URL:
https://patchew.org/QEMU/20210616091244.33049-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210616091244.33049-1-ys...@users.sourceforge.jp
Subject: [PATCH 0/3] renesas_sci
16.06.2021 10:09, Emanuele Giuseppe Esposito wrote:
On 15/06/2021 09:57, Vladimir Sementsov-Ogievskiy wrote:
14.06.2021 13:36, Emanuele Giuseppe Esposito wrote:
On 04/06/2021 11:17, Emanuele Giuseppe Esposito wrote:
Attaching gdbserver implies that the qmp socket
should wait indefinitely f
On Wed, Jun 16 2021, Eric Farman wrote:
> The Interrupt Response Block is comprised of several other
> structures concatenated together, but only the 12-byte
> Subchannel-Status Word (SCSW) is defined as a proper struct.
> Everything else is a simple array of 32-bit words.
>
> Let's define a prop
* Vivek Goyal (vgo...@redhat.com) wrote:
> On Tue, Jun 15, 2021 at 04:46:45PM +0100, Daniel P. Berrangé wrote:
> > On Fri, Jun 11, 2021 at 11:42:22AM -0400, Vivek Goyal wrote:
> > > On Fri, Jun 11, 2021 at 01:04:27PM +0100, Daniel P. Berrangé wrote:
> > > > Different guest xattr prefixes have disti
Ok, let's assume it's fixed - so I'm closing this now.
** Changed in: qemu
Status: Incomplete => Fix Released
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https://bugs.launchpad.net/bugs/1892962
Title:
Segfault in usb_bu
On Thu, 10 Jun 2021 09:16:33 -0400
Chris Browy wrote:
> From: hchkuo
>
> The Data Object Exchange implementation of CXL Coherent Device Attribute
> Table (CDAT). This implementation is referring to "Coherent Device
> Attribute Table Specification, Rev. 1.02, Oct. 2020" and "Compute
> Express Li
** Changed in: qemu
Status: Incomplete => Confirmed
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https://bugs.launchpad.net/bugs/1911216
Title:
abort issue locates in hw/usb/hcd-ohci.c:1297:ohci_frame_boundary
Status in
On Wed, Jun 16 2021, Eric Farman wrote:
> Wire in the subchannel callback for building the IRB
> ESW and ECW space for passthrough devices, and copy
> the hardware's ESW into the IRB we are building.
>
> If the hardware presented concurrent sense, then copy
> that sense data into the IRB's ECW sp
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> Different guest xattr prefixes have distinct access control rules applied
> by the guest. When remapping a guest xattr care must be taken that the
> remapping does not allow the a guest user to bypass guest kernel access
> control rules.
>
> For
On Jun 14 22:18, Heinrich Schuchardt wrote:
The EUI-64 field is the only identifier for NVMe namespaces in UEFI device
paths. Add a new namespace property "eui64", that provides the user the
option to specify the EUI-64.
v3:
use 52-54-00-00-00-00-00-00 as starting values for generating
On Wed, 16 Jun 2021, Alexey Kardashevskiy wrote:
On 6/16/21 07:09, BALATON Zoltan wrote:
On Tue, 15 Jun 2021, Alexey Kardashevskiy wrote:
The PAPR platform describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration
Hi
On Mon, Jun 14, 2021 at 4:20 PM Markus Armbruster wrote:
> marcandre.lur...@redhat.com writes:
>
> > From: Marc-André Lureau
> >
> > Wrap the 'if' condition in a higher-level object. Not only does this
>
> I can see "wrap in an object". I'm afraid don't get what makes it
> "higher-level".
>
On Wed, 16 Jun 2021, Alexey Kardashevskiy wrote:
On 6/15/21 20:29, BALATON Zoltan wrote:
On Tue, 15 Jun 2021, Alexey Kardashevskiy wrote:
The PAPR platform describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration
On Wed, 16 Jun 2021, Alexey Kardashevskiy wrote:
On 6/15/21 19:44, BALATON Zoltan wrote:
On Tue, 15 Jun 2021, Alexey Kardashevskiy wrote:
On 6/7/21 01:46, BALATON Zoltan wrote:
The pegasos2 board comes with an Open Firmware compliant ROM based on
SmartFirmware but it has some changes that are
On Tue, Jun 15 2021, Alex Bennée wrote:
> Richard Henderson writes:
>
>> The PSW_MASK_CC component of psw.mask was not handled properly
>> in the creation or restoration of signal frames.
>
> Still seeing issues running on s390x machine:
(...)
> However running on x86 backend everything seems
On 6/16/21 11:16 AM, Gerd Hoffmann wrote:
> Hi,
>
>> Should I send this patch with tag V2?
>
> Yes, please.
I don't understand why. Shouldn't it be enough if
Qiang Liu replies with
"Tested-by: Qiang Liu "
?
While the SB16 seems to work up to 48000 Hz, the "Sound Blaster Series
Hardware Programming Guide" limit the sampling range from 4000 Hz to
44100 Hz (Section 3-9, 3-10: Digitized Sound I/O Programming, tables
3-2 and 3-3).
Later, section 6-15 (DSP Commands) is more specific regarding the 41h /
42h
Hi
On Mon, Jun 14, 2021 at 4:48 PM Markus Armbruster wrote:
> marcandre.lur...@redhat.com writes:
>
> > From: Marc-André Lureau
> >
> > Instead of building prepocessor conditions from a list of string, use
> > the result generated from QAPISchemaIfCond.cgen().
>
> I understand why you're doing
On Thu, 10 Jun 2021 09:16:44 -0400
Chris Browy wrote:
> From: hchkuo
>
> Pre-built CDAT table for testing, contains one CDAT header and six
> CDAT entries: DSMAS, DSLBIS, DSMSCIS, DSIS, DSEMTS, and SSLBIS
> respectively.
>
> Signed-off-by: hchkuo
> Signed-off-by: Chris Browy
I can't apply t
+Helge
On 6/16/21 3:11 AM, Richard Henderson wrote:
> We cannot use a raw sigtramp page for hppa,
> but must wait for full vdso support.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/hppa/target_signal.h | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/linux-u
On 16/06/21 10:38, Markus Armbruster wrote:
... and both values are the same other QType (QTYPE_QNULL, QTYPE_QNUM,
QTYPE_QSTRING, QTYPE_QBOOL): overwrite.
Why is overwrite restricted to same QType? Is there no need for
overwriting say a string with a number? Hmm, I guess it's okay, because
ke
On 16/06/21 11:16, Gerd Hoffmann wrote:
I was almost giving up... but it looks like the result of
extract_all_objects(recursive: true) can be passed to custom_target(). Then
you can match it after compile_commands.json's "output" key.
Seems the custom_target commands do not land in compile_comm
From: Marcel Apfelbaum
Ensure mremap boundaries not trusting the guest kernel to
pass the correct buffer length.
Fixes: CVE-2021-3582
Reported-by: VictorV (Kunlun Lab)
Tested-by: VictorV (Kunlun Lab)
Signed-off-by: Marcel Apfelbaum
---
hw/rdma/vmw/pvrdma_cmd.c | 6 ++
1 file changed, 6 i
The QEMU project is only maintaining the very latest releases, so this
could be the current RC version, followed by the current stable release
and maybe also still the previous stable release (in case there are
severe bugs). But it does not make sense to show a fourth release that
we very likely do
Make it more clear that QEMU only supports the latest versions,
improve the color of a button, and put the emphasis on the
source code tarballs.
Thomas Huth (4):
Show only the latest three releases on the website
css: Improve the hover effect of the buttons
State that there is no official s
The hover effect of buttons was hardly visible since the color did
not change much. Use a brighter color to make it clear that the
button can be pressed.
Resolves: https://gitlab.com/qemu-project/qemu-web/-/issues/1
Signed-off-by: Thomas Huth
---
assets/css/style.css | 2 +-
1 file changed, 1 in
The QEMU project provides the source code of QEMU, and not any
binaries. So most people will come here for downloading the latest
version of the source code and not for getting instructions on
how to install the pre-packaged QEMU of their favourite distribution.
Thus let's put the information about
Looking at some new tickets in the bug tracker, some people still
seem to expect support for older releases. Let's make it a little
bit more clear that the QEMU project only focuses on the very latest
version.
Signed-off-by: Thomas Huth
---
support.md | 3 ++-
1 file changed, 2 insertions(+), 1
https://git.qemu.org/?p=qemu.git;a=commit;h=5529b02da2dcd1ef6bc6cd42d4fbfb537fe2276f
** Changed in: qemu
Status: Incomplete => Fix Committed
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https://bugs.launchpad.net/bugs/19235
Thx. I learned a lot about contributing to QEMU from this discussion!
Best,
Qiang
On Wed, Jun 16, 2021 at 6:43 PM Philippe Mathieu-Daudé wrote:
>
> While the SB16 seems to work up to 48000 Hz, the "Sound Blaster Series
> Hardware Programming Guide" limit the sampling range from 4000 Hz to
> 4410
Hi Eduardo,
On 15/06/2021 18:20, Eduardo Habkost wrote:
> On Tue, May 25, 2021 at 06:59:31AM +, Dov Murik wrote:
>> From: James Bottomley
>>
>> If the VM is using memory encryption and also specifies a kernel/initrd
>> or appended command line, calculate the hashes and add them to the
>> encr
On 15/06/2021 18:37, Fabiano Rosas wrote:
Richard Henderson writes:
On 6/15/21 4:32 AM, Bruno Piazera Larsen wrote:
On 14/06/2021 19:37, Richard Henderson wrote:
On 6/14/21 12:16 PM, Bruno Larsen (billionai) wrote:
This patch changes ppc_cpu_get_phys_page_debug so that it is now
able to tr
> On Jun 15, 2021, at 9:58 PM, Richard Henderson
> wrote:
>
> On 6/15/21 6:58 AM, Programmingkid wrote:
>>> Ahh I misread - so those are the addresses of the routines and not where
>>> it's sticking the breakpoint?
>>>
>>> I notice from a bit of googling that there is a boot debugger. I wond
On 6/16/21 11:28 AM, Gerd Hoffmann wrote:
>>> Hmm, what would be the use case? Right now qemu has the all-or-nothing
>>> approach for modules, i.e. if modules are enabled everything we can
>>> build as module will be built as module, and I havn't seen any drawbacks
>>> so far. So, why would one c
On Wed, Jun 16, 2021 at 09:21:21AM +0200, Markus Armbruster wrote:
> New test case enum-dict-no-name.json crashes:
>
> $ python3 scripts/qapi-gen.py tests/qapi-schema/enum-dict-no-name.json
> Traceback (most recent call last):
> [...]
> File "/work/armbru/qemu/scripts/qapi/expr.p
On Wed, May 19, 2021 at 4:26 PM Peter Lieven wrote:
>
> even luminous (version 12.2) is unmaintained for over 3 years now.
> Bump the requirement to get rid of the ifdef'ry in the code.
> Qemu 6.1 dropped the support for RHEL-7 which was the last supported
> OS that required an older librbd.
>
> S
On Wed, May 19, 2021 at 4:28 PM Peter Lieven wrote:
>
> Signed-off-by: Peter Lieven
> ---
> block/rbd.c | 37 -
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/block/rbd.c b/block/rbd.c
> index 0d8612a988..ee13f08a74 100644
> --- a/block/rbd
* Stefan Hajnoczi (stefa...@redhat.com) wrote:
> On Thu, Jun 10, 2021 at 04:29:42PM +0100, Dr. David Alan Gilbert wrote:
> > * Dr. David Alan Gilbert (dgilb...@redhat.com) wrote:
> > > * Stefan Hajnoczi (stefa...@redhat.com) wrote:
> >
> >
> >
> > > > Instead I was thinking about VHOST_USER_DMA_
Following the APM2 I added some checks to
resolve the following tests in kvm-unit-tests for svm:
* vmrun_intercept_check
* asid_zero
* sel_cr0_bug
* CR0 CD=0,NW=1: a0010011
* CR0 63:32: 180010011
* CR0 63:32: 1080010011
* CR0 63:32: 10080010011
* CR0 63:32: 100080010011
* CR0 63
Added cpu_svm_has_intercept to reduce duplication when checking the
corresponding intercept bit outside of cpu_svm_check_intercept_param
Signed-off-by: Lara Lazier
---
target/i386/cpu.h | 3 +
target/i386/tcg/sysemu/svm_helper.c | 105 +++-
2 files cha
When the selective CR0 write intercept is set, all writes to bits in
CR0 other than CR0.TS or CR0.MP cause a VMEXIT.
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/misc_helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/i386/tcg/sysemu/misc_helper.c
b/target/i38
The combination of unset CD and set NW bit in CR0 is illegal.
CR0[63:32] are also reserved and need to be zero.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/cpu.h | 2 ++
target/i386/svm.h | 2 ++
target/i386/
Zero VMRUN intercept and ASID should cause an immediate VMEXIT
during the consistency checks performed by VMRUN.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/svm_helper.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/t
On 6/16/21 1:58 PM, Qiang Liu wrote:
> Thx. I learned a lot about contributing to QEMU from this discussion!
I think this was a misunderstanding with Gerd, the maintainer.
Maintainers use some tools to ease their patch-by-email workflow.
As a tester/reviewer you simply reply to a patch with a "Re
Peter Xu wrote:
> Currently we'll skip the whole migration-test if uffd missing.
>
> It's a bit harsh - we can still run the rest besides postcopy! Enable them
> when we still can.
>
> It'll happen more frequently now after kernel UFFD_USER_MODE_ONLY introduced
> in
> commit 37cd0575b8510159, as
On Tue, 15 Jun 2021 at 16:22, Stefan Berger wrote:
>
> Hello!
>
> The patches in this PR eliminate all TPM related code if CONFIG_TPM is
> not set, thus reducing code size.
>
> Regards,
>Stefan
>
> The following changes since commit 1ea06abceec61b6f3ab33dadb0510b6e09fb61e2:
>
> Merge remote-
Mark Cave-Ayland writes:
> On 16/06/2021 02:58, Richard Henderson wrote:
>
>> On 6/15/21 6:58 AM, Programmingkid wrote:
Ahh I misread - so those are the addresses of the routines and not where
it's sticking the breakpoint?
I notice from a bit of googling that there is a boot d
Peter Xu wrote:
> Add dirty ring test if kernel supports it. Add the dirty ring parameter on
> source should be mostly enough, but let's change the dest too to make them
> match always.
>
> Reviewed-by: Dr. David Alan Gilbert
> Signed-off-by: Peter Xu
Reviewed-by: Juan Quintela
Why we check
On Wed, 2021-06-16 at 11:46 +0200, Cornelia Huck wrote:
> On Wed, Jun 16 2021, Eric Farman wrote:
>
> > The Interrupt Response Block is comprised of several other
> > structures concatenated together, but only the 12-byte
> > Subchannel-Status Word (SCSW) is defined as a proper struct.
> > Everyt
On 16/06/21 14:39, Lara Lazier wrote:
cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
uint64_t param, uintptr_t retaddr)
{ /* no-op */ }
+bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
+{ return false; }
This needs to be declared
On 16/06/21 14:39, Lara Lazier wrote:
Following the APM2 I added some checks to
resolve the following tests in kvm-unit-tests for svm:
* vmrun_intercept_check
* asid_zero
* sel_cr0_bug
* CR0 CD=0,NW=1: a0010011
* CR0 63:32: 180010011
* CR0 63:32: 1080010011
* CR0 63:32: 1008
Based-on: <20210518201146.794854-1-richard.hender...@linaro.org>
This commit attempts to fix the first bug mentioned by Richard Henderson in
https://lists.nongnu.org/archive/html/qemu-devel/2021-05/msg06247.html
To sumarize the bug here, when radix-style mmus are translating an
address, they migh
On Wed, 2021-06-16 at 11:59 +0200, Cornelia Huck wrote:
> On Wed, Jun 16 2021, Eric Farman wrote:
>
> > Wire in the subchannel callback for building the IRB
> > ESW and ECW space for passthrough devices, and copy
> > the hardware's ESW into the IRB we are building.
> >
> > If the hardware presen
On 15/06/21 01:31, Richard Henderson wrote:
Now that we assume gcc 7.5 as a minimum, we have the option of
changing to a newer C standard. The two major new features that
I think apply are _Generic and _Static_assert.
While Paolo created a remarkably functional replacement for _Generic
using bu
On Wed, 16 Jun 2021 at 13:53, Alex Bennée wrote:
>
> Mark Cave-Ayland writes:
> > diff --git a/exec.c b/exec.c
> > index 67e520d18e..7f4074f95e 100644
> > --- a/exec.c
> > +++ b/exec.c
> > @@ -1019,14 +1019,13 @@ void tb_invalidate_phys_addr(AddressSpace *as,
> > hwaddr addr, MemTxAttrs attrs)
>
> When using libvirt for RDMA live migration, if the VM memory is too large,
> it will take a lot of time to deregister the VM at the source side, resulting
> in a long downtime (VM 64G, deregister vm time is about 400ms).
>
> Although the VM's memory uses 2M huge pages, the MLNX driver still us
On 15/06/21 18:18, Max Reitz wrote:
}
+/* Returns the maximum hardware transfer length, in bytes; guaranteed
nonzero */
+uint64_t blk_get_max_hw_transfer(BlockBackend *blk)
+{
+ BlockDriverState *bs = blk_bs(blk);
+ uint64_t max = INT_MAX;
+
+ if (bs) {
+ max = MIN_NON_ZERO(bs
Mark Cave-Ayland writes:
> On 16/06/2021 02:58, Richard Henderson wrote:
>
>> On 6/15/21 6:58 AM, Programmingkid wrote:
Ahh I misread - so those are the addresses of the routines and not where
it's sticking the breakpoint?
I notice from a bit of googling that there is a boot d
Le 14/06/2021 à 16:42, Alex Bennée a écrit :
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - fix typo in summary :-O
> ---
> linux-user/trace-events | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/linux-user/trace-events b/linux-user/trace-events
> index 1ec0d11ee3..e7d
"Zhang, Chen" writes:
>> -Original Message-
>> From: Markus Armbruster
>> Sent: Wednesday, June 16, 2021 2:04 PM
>> To: Zhang, Chen
>> Cc: Lukas Straub ; Daniel P.Berrangé
>> ; Li Zhijian ; Jason Wang
>> ; qemu-dev ; Dr. David
>> Alan Gilbert ; Gerd Hoffmann ;
>> Zhang Chen ; Eric Blake
On Wed, Jun 16, 2021 at 02:55:55PM +0200, Juan Quintela wrote:
> Peter Xu wrote:
> > Add dirty ring test if kernel supports it. Add the dirty ring parameter on
> > source should be mostly enough, but let's change the dest too to make them
> > match always.
> >
> > Reviewed-by: Dr. David Alan Gilb
1e2:
Merge remote-tracking branch
'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-06-14
15:59:13 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210616
On Tue, Jun 15, 2021 at 6:12 PM Richard Henderson
wrote:
>
> Create and record the rt signal trampoline.
> Use it when the guest does not use SA_RESTORER.
>
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> linux-user/xtensa/target_signal.h | 2 ++
> linux-user/xtensa/signal.c
On 11.06.21 22:04, Vivek Goyal wrote:
On Wed, Jun 09, 2021 at 05:55:49PM +0200, Max Reitz wrote:
Currently, lo_inode.fhandle is always NULL and so always keep an O_PATH
FD in lo_inode.fd. Therefore, when the respective inode is unlinked,
its inode ID will remain in use until we drop our lo_inod
On Tue, Jun 15, 2021 at 6:20 PM Richard Henderson
wrote:
>
> Allocate a page to hold the signal trampoline(s).
> Invoke a guest-specific hook to fill in the contents
> of the page before marking it read-execute again.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/qemu.h| 7 +++
On 11.06.21 21:19, Vivek Goyal wrote:
On Wed, Jun 09, 2021 at 05:55:42PM +0200, Max Reitz wrote:
Hi,
v1 cover letter for an overview:
https://listman.redhat.com/archives/virtio-fs/2021-June/msg00033.html
Hi Max,
What's the impact of these patches on performance? Just trying to
get some idea w
Richard Henderson writes:
> ARM is more complicated than the others, in that we also
> have trampolines for using SA_RESTORER with FDPIC, and
> we need to create trampolines for both ARM and Thumb modes.
>
> Cc: qemu-...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> linux-user/arm/targe
On 16.06.21 15:18, Paolo Bonzini wrote:
On 15/06/21 18:18, Max Reitz wrote:
}
+/* Returns the maximum hardware transfer length, in bytes;
guaranteed nonzero */
+uint64_t blk_get_max_hw_transfer(BlockBackend *blk)
+{
+ BlockDriverState *bs = blk_bs(blk);
+ uint64_t max = INT_MAX;
+
+
Alex Bennée writes:
> Richard Henderson writes:
>
>> ARM is more complicated than the others, in that we also
>> have trampolines for using SA_RESTORER with FDPIC, and
>> we need to create trampolines for both ARM and Thumb modes.
>>
>> Cc: qemu-...@nongnu.org
>> Signed-off-by: Richard Henderson
On Wed, Jun 16 2021, Eric Farman wrote:
> On Wed, 2021-06-16 at 11:46 +0200, Cornelia Huck wrote:
>> On Wed, Jun 16 2021, Eric Farman wrote:
>>
>> > The Interrupt Response Block is comprised of several other
>> > structures concatenated together, but only the 12-byte
>> > Subchannel-Status Word
> On Jun 14, 2021, at 9:24 PM, Jason Thorpe wrote:
>> Why can't we just use the existing device model?
>> Certainly duplicating code like this isn't the best way.
>
> Yah, I’m not super happy with that, either, tbh. When I first started
> working on this several months ago, I it looked like
On Wed, Jun 16 2021, Eric Farman wrote:
> On Wed, 2021-06-16 at 11:59 +0200, Cornelia Huck wrote:
>> On Wed, Jun 16 2021, Eric Farman wrote:
>>
>> > Wire in the subchannel callback for building the IRB
>> > ESW and ECW space for passthrough devices, and copy
>> > the hardware's ESW into the IRB
Paolo Bonzini writes:
> Allow parsing multiple keyval sequences into the same dictionary.
> This will be used to simplify the parsing of the -M command line
> option, which is currently a .merge_lists = true QemuOpts group.
>
> Signed-off-by: Paolo Bonzini
Straightforward. Thanks for adjusting
2021年5月12日(水) 3:56 :
> @@ -1877,11 +1934,17 @@ static void cocoa_display_init(DisplayState *ds,
> DisplayOptions *opts)
> qemu_sem_wait(&app_started_sem);
> COCOA_DEBUG("cocoa_display_init: app start completed\n");
>
> +QemuCocoaAppController* controller = (QemuCocoaAppController
>
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