On Fri, 4 Jun 2021 at 16:19, Paolo Bonzini wrote:
>
> The following changes since commit 5a95f5ce3cd5842cc8f61a91ecd4fb4e8d10104f:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-fpu-20210603'
> into staging (2021-06-04 10:04:11 +0100)
>
> are available in the Git repository at:
Gerd Hoffmann 于2021年6月4日周五 下午6:37写道：
>
> Free in correct order to avoid use-after-free.
>
> Resolves: CID 1453812
> Signed-off-by: Gerd Hoffmann
Sorry, my fault.
Reviewed-by: Li Qiang
> ---
> contrib/vhost-user-gpu/vhost-user-gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On Tue, 25 May 2021 03:49:57 +
Wang Xingang wrote:
> From: Xingang Wang
>
> These patches add support for configure bypass_iommu on/off for
> pci root bus, including primary bus and pxb root bus. At present,
> all root bus will go through iommu when iommu is configured,
> which is not flexi
04.06.2021 12:17, Emanuele Giuseppe Esposito wrote:
Signed-off-by: Emanuele Giuseppe Esposito
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
docs/devel/testing.rst | 11 +++
1 file changed, 11 insertions(+)
diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst
index 9d6a8f8636
04.06.2021 12:17, Emanuele Giuseppe Esposito wrote:
Currently, the check script only parses the option and sets the
VALGRIND_QEMU environmental variable to "y".
Add another local python variable that prepares the command line,
identical to the one provided in the test scripts.
Because the python
04.06.2021 12:17, Emanuele Giuseppe Esposito wrote:
From: John Snow
Pylint prior to 2.8.3 (We pin at >= 2.8.0) includes function and method
signatures as part of its duplicate checking algorithm. This check does
not listen to pragmas, so the only way to disable it is to turn it off
completely or
04.06.2021 23:09, Eric Blake wrote:
On Wed, May 05, 2021 at 10:49:57AM +0300, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths.
Main motivation is realization of 64-bit write_zeroes operation for
fast zeroing large disk
04.06.2021 19:39, John Snow wrote:
Since iotests are such a heavy and prominent user of the Python qemu.qmp
and qemu.machine packages, it would be convenient if the Python linting
suite also checked this client for any possible regressions introduced
by shifting around signatures, types, or inter
04.06.2021 19:39, John Snow wrote:
Refactor the core function of the linting configuration out of 297 and
into a new file called linters.py.
Now, linters.py represents an invocation of the linting scripts that
more resembles a "normal" execution of pylint/mypy, like you'd expect to
use if 'qemu'
04.06.2021 13:07, Emanuele Giuseppe Esposito wrote:
There seems to be no benefit in using a field. Replace it with a local
variable.
Signed-off-by: Emanuele Giuseppe Esposito
---
block/blkdebug.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/block/blkdebug
Il ven 4 giu 2021, 16:26 Eric Blake ha scritto:
> As an API, this command seems awkward. How do I query what phase I'm
> currently in? How many times do I have to call it? Do we anticipate
> the number of times I need to call it to change in future qemu
> releases?
>
Indeed this has been chan
On Fri, 4 Jun 2021 at 21:14, Richard Henderson
wrote:
>
> The following changes since commit 1cbd2d914939ee6028e9688d4ba859a528c28405:
>
> Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into
> staging (2021-06-04 13:38:49 +0100)
>
> are available in the Git repository at:
04.06.2021 13:07, Emanuele Giuseppe Esposito wrote:
First, categorize the structure fields to identify what needs
to be protected and what doesn't.
We essentially need to protect only .state, and the 3 lists in
BDRVBlkdebugState.
Then, add the lock and mark the functions accordingly.
Co-develo
Hi Thomas,
On 03.06.2021 12:41, Thomas Huth wrote:
I accidentally came accross vmstate_vmbus_dev and noticed that
it is currently not used at all ... wire it up and make it
static, since it is only used in one file.
Thomas Huth (2):
hw/hyperv/vmbus: Wire up vmstate_vmbus_dev
hw/hyperv/vmb
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
There might be more than just KVM and TCG in the future,
so where appropriate, replace broad "else" statements
with the appropriate if (accel_enabled()) check.
Also invert some checks for !kvm_enabled() or !tcg_enabled()
where it seems
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
test is TCG-only.
Signed-off-by: Claudio Fontana
Cc: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
tests/qtest/bios-tables-test.c | 7 +++
1 file changed, 7 insertions(+)
The new qtest_has_accel should be used instead
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this ca
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
Skip the test_device_intro_concrete for now for ARM KVM-only build,
as on ARM we currently build devices for ARM that are not
compatible with a KVM-only build.
We can remove this workaround when we fix this in KConfig etc,
and we only
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this ca
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
move init, realizefn and reset code into it.
Signed-off-by: Claudio Fontana
Cc: Paolo Bonzini
Signed-off-by: Alex Bennée
---
target/arm/tcg/tcg-cpu.h| 4 ++-
target/arm/cpu.c| 44 ++--
No user for this helper, let's remove it.
[GD>>] These patches seem unrelated to me. Do you think they should be part of
one patch series?
Signed-off-by: Jason Wang
---
include/net/vhost-vdpa.h | 1 -
net/vhost-vdpa.c | 9 -
2 files changed, 10 deletions(-)
diff --git a/inclu
On 05/06/2021 15:28, Vladimir Sementsov-Ogievskiy wrote:
04.06.2021 12:17, Emanuele Giuseppe Esposito wrote:
Currently, the check script only parses the option and sets the
VALGRIND_QEMU environmental variable to "y".
Add another local python variable that prepares the command line,
identical
Leading underscores followed by a capital letter or underscore are
reserved by the C standard.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/369
Signed-off-by: Ahmed Abouzied
---
include/fpu/softfloat-helpers.h | 4 ++--
include/hw/usb/dwc2-regs.h | 4 ++--
Identifiers with leading underscores followed by capital letters or
underscores are reserved for C standards.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/369
Signed-off-by: Ahmed Abouzied
---
include/hw/xen/interface/grant_table.h | 4 ++--
include/hw/xen/interface/io/blkif.h |
On 05/06/2021 17:15, Vladimir Sementsov-Ogievskiy wrote:
04.06.2021 13:07, Emanuele Giuseppe Esposito wrote:
First, categorize the structure fields to identify what needs
to be protected and what doesn't.
We essentially need to protect only .state, and the 3 lists in
BDRVBlkdebugState.
Then
On 6/4/21 8:52 AM, Alex Bennée wrote:
+#ifndef CPU_SVE_H
+#define CPU_SVE_H
+
+/* note: SVE is an AARCH64-only option, only include this for TARGET_AARCH64 */
This seems unnecessary.
@@ -201,13 +202,9 @@ typedef struct {
#ifdef TARGET_AARCH64
# define ARM_MAX_VQ16
-void arm_cpu_sv
On 6/4/21 8:52 AM, Alex Bennée wrote:
@@ -276,8 +276,8 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v,
const char *name,
* of the contents of "name" to determine which bit on which
* to operate.
*/
-static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
return false on error, true on success.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-sve.h | 2 +-
target/arm/cpu-sve.c | 17 +
target/arm/cpu.c | 3 +--
3 files changed, 11 in
Le 16/05/2021 à 22:53, Philippe Mathieu-Daudé a écrit :
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a
Le 19/05/2021 à 13:35, Dmitry Voronetskiy a écrit :
> From: Dmitry Voronetskiy
>
> Signed-off-by: Dmitry Voronetskiy
>
> ---
> hw/i386/kvm/apic.c | 2 +-
> hw/i386/kvm/clock.c | 4 ++--
> hw/i386/kvm/i8254.c | 10 +-
> hw/i386/kvm/i8259.c | 4 ++--
> hw/i386/kvm/ioapic.c | 4 +
Le 21/05/2021 à 12:34, Philippe Mathieu-Daudé a écrit :
> Fix a typo from commit fa2f7b0b9b7 ("meson: Warn when TCI is
> selected but TCG backend is available").
>
> Reported-by: Peter Maydell
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> meson.build | 2 +-
> 1 file changed, 1 insertion(+),
Le 23/05/2021 à 11:40, Philippe Mathieu-Daudé a écrit :
> Such comments make reviewing this file somehow easier.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> v2: only one space before end of comment (mst)
> ---
> hw/virtio/virtio.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a
Le 16/05/2021 à 22:50, Philippe Mathieu-Daudé a écrit :
> Headers should be included from the 'include/' directory,
> not from the root directory.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i386/acpi-common.h | 6 +++---
> include/monitor/monitor.h | 2 +-
> hw/gpio/aspeed_gpio.c
Le 17/05/2021 à 07:52, Philippe Mathieu-Daudé a écrit :
> Keep bitmask_transtbl in .rodata by marking the arrays const.
>
> Reviewed-by: Laurent Vivier
> Reviewed-by: Richard Henderson
> Reviewed-by: Bin Meng
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> linux-user/syscall.c | 4 ++--
> 1 f
Le 11/05/2021 à 21:29, John Snow a écrit :
> Long story short, we need a space here for the reference to work
> correctly.
>
>
> Longer story:
>
> Without the space, kerneldoc generates a line like this:
>
> one of :c:type:`MemoryListener.region_add\(\)
> `,:c:type:`MemoryListener.region_del\(
Le 25/05/2021 à 16:28, Richard Henderson a écrit :
> Laurent, how about through trivial?
Applied to my trivial-patches branch.
Thanks,
Laurent
>
> r~
>
> On 5/24/21 11:40 PM, Pavel Dovgalyuk wrote:
>> ping
>>
>> On 11.05.2021 11:40, Pavel Dovgalyuk wrote:
>>> This patch fixes calculation of nu
05.06.2021 20:38, Emanuele Giuseppe Esposito wrote:
On 05/06/2021 15:28, Vladimir Sementsov-Ogievskiy wrote:
04.06.2021 12:17, Emanuele Giuseppe Esposito wrote:
Currently, the check script only parses the option and sets the
VALGRIND_QEMU environmental variable to "y".
Add another local pytho
Le 31/05/2021 à 09:32, Thomas Huth a écrit :
> The "nubus-macfb" currently shows up as uncategorized device in
> the output of "-device help". Put it into the display category
> to fix this ugliness.
>
> Signed-off-by: Thomas Huth
> ---
> hw/display/macfb.c | 1 +
> 1 file changed, 1 insertion(+
Le 17/05/2021 à 12:15, Philippe Mathieu-Daudé a écrit :
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/hppa/cpu.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 61178fa6a2a..748270bfa31 100644
> --- a/target/hppa/cpu.h
> +++ b/target
Le 07/03/2021 à 08:48, Philippe Mathieu-Daudé a écrit :
> MemoryRegion names is cached on first call to memory_region_name(),
> so displaying the name is trace events is cheap. Add it for read /
> write ops.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> softmmu/memory.c | 12
Le 02/06/2021 à 19:07, Philippe Mathieu-Daudé a écrit :
> Fix Uncoditional -> Unconditional typo.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/tcg/translate.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/mips/tcg/translate.c b/target/mip
Le 02/06/2021 à 19:07, Philippe Mathieu-Daudé a écrit :
> While we only use stdin, the chardev is named 'stdio'.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> scripts/oss-fuzz/reorder_fuzzer_qtest_trace.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/scripts/oss-
On 6/4/21 8:52 AM, Alex Bennée wrote:
DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ);
-DECLARE_BITMAP(tmp, ARM_MAX_VQ);
-uint32_t vq, max_vq = 0;
-
-/* Collect the set of vector lengths supported by KVM. */
-bitmap_zero(kvm_supported, ARM_MAX_VQ);
-if (kvm_enabled() && kvm_ar
Le 17/05/2021 à 14:32, Xie Yongji a écrit :
> The symbol address_space_memory are already declared in
> include/exec/address-spaces.h. So let's add this header file
> and remove the redundant declaration in include/hw/virtio/vhost-vdpa.h.
>
> Signed-off-by: Xie Yongji
> Reviewed-by: Philippe Math
05.06.2021 20:53, Emanuele Giuseppe Esposito wrote:
On 05/06/2021 17:15, Vladimir Sementsov-Ogievskiy wrote:
04.06.2021 13:07, Emanuele Giuseppe Esposito wrote:
First, categorize the structure fields to identify what needs
to be protected and what doesn't.
We essentially need to protect only
On 6/4/21 8:52 AM, Alex Bennée wrote:
+void kvm_sve_get_supported_lens(ARMCPU *cpu, unsigned long *kvm_supported)
+{
+/* Collect the set of vector lengths supported by KVM. */
+bitmap_zero(kvm_supported, ARM_MAX_VQ);
+
+if (kvm_arm_sve_supported()) {
+kvm_arm_sve_get_vls(CPU(c
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
when TARGET_AARCH64 is not defined, it is helpful to make
is_aa64() and arm_el_is_aa64 macros defined to "false".
This way we can make more code TARGET_AARCH64-only.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
t
On 6/4/21 8:52 AM, Alex Bennée wrote:
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -999,6 +999,8 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env,
int fp_el,
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
}
+#ifdef TARGET_AARCH64
+
static
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
this will allow us to restrict more code to TARGET_AARCH64
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
I don't see this as an improvement, necessarily. IIRC, arch_dump is sysemu
only
On 6/4/21 8:52 AM, Alex Bennée wrote:
diff --git a/target/arm/cpu-exceptions-aa64.h b/target/arm/cpu-exceptions-aa64.h
new file mode 100644
index 00..64f800a15d
--- /dev/null
+++ b/target/arm/cpu-exceptions-aa64.h
@@ -0,0 +1,28 @@
+/*
+ * QEMU AArch64 CPU Exceptions Sysemu code
+ *
+ * Co
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
after restricting AArch64-specific code to TARGET_AARCH64 builds,
we can now extract the exception handling code from cpu-sysemu,
and split its AArch64-specific part into its own module.
Signed-off-by: Claudio Fontana
Signed-off-by:
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
restrict zcr_el1, zcr_el2, zcr_no_el2, zcr_el3 reginfo,
and the related SVE functions to TARGET_AARCH64.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
target/arm/tcg/cpregs.c | 8 ++-
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
aarch64_sve_narrow_vq and aarch64_sve_change_el are SVE-related
functions only used for TCG, so we can put them in the
tcg-sve.c module.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
On 6/4/21 8:52 AM, Alex Bennée wrote:
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3edf8bb4ec..e9bfb6f575 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -223,7 +223,8 @@ typedef struct ARMPACKey {
} ARMPACKey;
#else
static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, E
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
now that is_a64() is just always false when !TARGET_AARCH64,
we can just use that instead of introducing a new ifdef.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu-common.c | 10 +++---
1 file chan
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
Pointer Authentication is an AARCH64-only ARMv8.3 optional
extension, whose cpu properties can be separated out in its own module.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 3 --
On 6/4/21 8:52 AM, Alex Bennée wrote:
From: Claudio Fontana
make arm_cpu_pauth_finalize return a bool,
and make the name canonical for the module (cpu_pauth_finalize).
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/tcg/cpu-pauth.h | 2 +-
target/arm/cpu.c
On 6/4/21 8:53 AM, Alex Bennée wrote:
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index fefb6954fc..c762f3f07a 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -469,6 +469,40 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs)
return g_strdup("aarch64");
}
+void ar
On 6/4/21 8:53 AM, Alex Bennée wrote:
@@ -469,11 +469,10 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs)
return g_strdup("aarch64");
}
-void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_finalize_features(ARMCPU *cpu, Error **errp)
{
Error *local_
On 6/4/21 8:53 AM, Alex Bennée wrote:
From: Claudio Fontana
bail out immediately if ARM_FEATURE_AARCH64 is not set,
and add an else statement when checking for accelerators.
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
target/arm/cpu64.c | 33 --
On 6/4/21 8:53 AM, Alex Bennée wrote:
-if (arm_feature(env, ARM_FEATURE_M)) {
-return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
+if (tcg_enabled()) {
+if (arm_feature(env, ARM_FEATURE_M)) {
Merge the two if with &&?
Otherwise,
Reviewed-by: Richard Henderson
On 6/4/21 8:53 AM, Alex Bennée wrote:
From: Philippe Mathieu-Daudé
Add a target-specific Kconfig.
Target foo now has CONFIG_FOO defined.
Two architecture have a particularity, ARM and MIPS:
their 64-bit version include the 32-bit subset.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20
On 6/4/21 8:53 AM, Alex Bennée wrote:
config ARM_V7M
bool
+# currently v7M must be included in a TCG build due to translate.c
+default y if TCG && (ARM || AARCH64)
select PTIMER
+select ARM_COMPATIBLE_SEMIHOSTING
I don't really understand "default", because if one were
On 6/4/21 8:53 AM, Alex Bennée wrote:
We need this functionality due to:
/* XRAM IRQs get ORed into a single line. */
object_initialize_child(OBJECT(s), "xram-irq-orgate",
&s->lpd.xram.irq_orgate, TYPE_OR_IRQ);
Signed-off-by: Alex Bennée
---
hw/arm/Kcon
On 6/4/21 8:53 AM, Alex Bennée wrote:
The assumption that the qemu-system-aarch64 image can run all 32 bit
machines is about to be broken...
Um, what?
r~
and besides it's not likely this is
improving out coverage by much. Test the "virt" machine for both arm
and aarch64 as it can be used
On 6/4/21 8:53 AM, Alex Bennée wrote:
It will soon be possible to build an qemu-system-aarch64 system that
doesn't have this.
Signed-off-by: Alex Bennée
---
tests/qtest/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 6/4/21 8:53 AM, Alex Bennée wrote:
+++ b/configs/aarch64-softmmu/64bit-only.mak
@@ -0,0 +1,10 @@
+#
+# A version of the config that only supports 64bits and their devices.
+# This doesn't quite eliminate all 32 bit devices as some boards like
+# "virt" support both.
It's not really 64bit-onl
On 6/4/21 8:53 AM, Alex Bennée wrote:
We can now build a KVM only aarch64-softmmu image which we need to
cross build. We can also build a version that only supports a limited
set of 64 bit images.
Signed-off-by: Alex Bennée
---
.gitlab-ci.d/buildtest.yml | 10 ++
.gitlab-ci.d/cross
On 6/2/21 8:53 PM, Jason Thorpe wrote:
Don't include system headers. Instead, provide standalone definitions
and declarations of types needed and functions used by the PALcode that
are compatible with the standard Alpha / GCC ABI.
Signed-off-by: Jason Thorpe
---
init.c | 2 --
memcpy.c |
On 6/2/21 8:53 PM, Jason Thorpe wrote:
In the unaligned access exception vector, actually pass the return PC
in the exception frame. This is required in order for unaligned access
fixup handlers in the operating system to work.
Signed-off-by: Jason Thorpe
---
pal.S | 2 +-
1 file changed, 1
On 6/2/21 8:53 PM, Jason Thorpe wrote:
Initialize the hwrpb.hwrpb.cpuid field with the primary CPU ID, not
the processor type, as per the architecture specification. Some
operating systems check and assert this.
Improve a couple of comments.
Signed-off-by: Jason Thorpe
---
init.c | 29 ++
On 6/2/21 8:53 PM, Jason Thorpe wrote:
Move PCI_DEVFN(), PCI_BUS(), PCI_SLOT(), and PCI_FUNC() to pci.h.
Signed-off-by: Jason Thorpe
---
pci.c | 4
pci.h | 5 +
2 files changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 6/2/21 8:53 PM, Jason Thorpe wrote:
- if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
+ if ((old & PCI_BASE_ADDRESS_SPACE_IO) == 0 &&
The correct test is
(old & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY
Bitwise it's the same thing. I'll fix it up while applying.
On 6/2/21 8:53 PM, Jason Thorpe wrote:
Use system-specific information to program the interrupt line register
with the interrupt mappings, which is what the SRM console does on real
hardware; some operating systems (e.g. NetBSD) use this information
rather than having interrupt mappings tables fo
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