clone_test aarch64 binary
** Attachment added: "clone_test (aarch64)"
https://bugs.launchpad.net/qemu/+bug/1926996/+attachment/5494467/+files/clone_test
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clone_test (x86_64)
** Attachment added: "clone_test (x86_64)"
https://bugs.launchpad.net/qemu/+bug/1926996/+attachment/5494470/+files/clone_test
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https://bugs.launchpad.net/bugs/192
On 5/3/21 10:13 AM, Philippe Mathieu-Daudé wrote:
Remove the sun4m_hwdefs[] array by moving assigning the
structure fields directly in each machine class_init()
function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 248 ++-
1 file c
❦ 3 mai 2021 17:05 +02, Igor Mammedov:
>> +/*
>> + * We only handle the case were the device is attached to
>> + * the PCI root bus. The general case is more complex as
>> + * bridges are enumerated later and the table would need
>> + *
On Mon, May 3, 2021 at 7:06 AM Shivaprasad G Bhat wrote:
>
>
> On 5/1/21 12:44 AM, Dan Williams wrote:
> > Some corrections to terminology confusion below...
> >
> >
> > On Wed, Apr 28, 2021 at 8:49 PM Shivaprasad G Bhat
> > wrote:
> >> The nvdimm devices are expected to ensure write persistence
On Mon, May 03, 2021 at 09:34:42PM +0200, Vincent Bernat wrote:
> ❦ 3 mai 2021 17:05 +02, Igor Mammedov:
>
> >> +/*
> >> + * We only handle the case were the device is attached to
> >> + * the PCI root bus. The general case is more complex as
> >> +
On 30/04/2021 21:55, Richard Henderson wrote:
On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote:
Moved all SPR read/write callback, and some related functions, to a
new file specific for it. These callbacks are TCG only, so separating
them is required to support the build flag disable-tcg.
M
Hi all,
I was about to make icount work. but, there is something I still don't
understand. I have this code
timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_wdt_interrupt, s);
and then
void avr_wdt_interrupt(/* some arguments */) {
#define MS2NS(n)((n) * 100ull)
timer_mod_ns(timer,
Hi,
Forwarding this along to the list, so it doesn't get burried during the
gitlab issue migration.
- Forwarded message from "Alexander Bulekov (@a1xndr)"
-
Alexander Bulekov created an issue:
https://gitlab.com/qemu-project/qemu/-/issues/111
Hello,
Reproducer
```
cat << EOF | ./qemu-
On 03/05/2021 12:25, Richard Henderson wrote:
On 5/3/21 4:28 AM, Bruno Piazera Larsen wrote:
Note for future cleanup: Make spr_tcg.c be standalone as well. Just
need to move a few declarations to a translate.h.
it's not that easy, unfortunately. The readers and writers use a lot
of global vari
I suspect it's failing because the qemu-user emulation of clone is
basically enough for what libc uses and not for your own set of flags:
https://qemu-project.gitlab.io/qemu/src/S/2440.html#L6478
** Tags added: linux-user
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https://bugs.launchpad.net/bugs/1926996
Title:
qemu-user clone syscall fails
Status in QEMU:
N
On 03/05/2021 01:54, David Gibson wrote:
On Fri, Apr 30, 2021 at 04:35:28PM -0300, Bruno Larsen (billionai) wrote:
Moved all SPR read/write callback, and some related functions, to a
new file specific for it. These callbacks are TCG only, so separating
them is required to support the build flag
>From looking at the in_asm logs, it looks like that instruction starting
with 0xebde is executed once with no problem but the second time its
changed to 0x.
... # First Time
IN:
0x40126d6880: ebde f000 ec51 tmy -0x14000(%r15), 0xde
0x40126d6886: e3e0 f008 0024 stg
The 4.x branch of Sphinx introduces a breaking change, as generated man
pages are now written to subdirectories corresponding to the manual
section they belong to. This results in `make install` erroring out when
attempting to install the man pages, because they are not where it
expects to find the
Patchew URL:
https://patchew.org/QEMU/20210503161422.15028-1-dgouttegat...@incenp.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210503161422.15028-1-dgouttegat...@incenp.org
Subject: [PATCH] docs: Fix installat
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
not delegated in hideleg (which was not being taken into account). This
was mainly because hs level sie was not always considered enabled when
it should. The spec states that "Interrupts for higher-privilege modes,
y>x, are alway
Still seems to be an issue for me.
Qemu Version 5.2.0
Arch Linux 5.11.16-arch1-1
** Changed in: qemu
Status: Incomplete => New
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https://bugs.launchpad.net/bugs/1860742
Title:
Missing review: 10-12 (bios-tables-test)
Hi,
This series aims at having accelerator-independent qtests
by querying a QEMU instance at runtime to check the list
of built-in accelerators.
First we add the 'query-accels' QMP command,
then we add the qtest_has_accel() method to libqtest,
finally we
Introduce the 'query-accels' QMP command which returns a list
of built-in accelerator names.
- Accelerator is a QAPI enum of all existing accelerators,
- AcceleratorInfo is a QAPI structure providing accelerator
specific information. Currently the common structure base
provides the name of th
Introduce the qtest_has_accel() method which allows a runtime
query on whether a QEMU instance has an accelerator built-in.
Reviewed-by: Eric Blake
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/libqos/libqtest.h | 8
tests/qtest/libqtest.c| 29
Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, do it once at the beginning
and only register the tests we can run.
We can then replace the #ifdef'ry by an assertion.
Signed-off-by: Philippe Mathieu-Daudé
---
v5 had:
Reviewed-by: Eric Blake
Reviewed-by: A
We want the ARM maintainers and the qemu-arm@ list to be
notified when this file is modified. Add an entry to the
'ARM TCG CPUs' section in the MAINTAINERS file.
Acked-by: Andrew Jones
Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1
Use the recently added generic qtest_has_accel() method to
check if KVM is available.
Suggested-by: Claudio Fontana
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 25 +
1 file changed, 1 ins
Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, only run these tests if TCG
is built into the QEMU binary.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-featu
The sve_tests_sve_off_kvm() test is KVM specific.
Only run it if KVM is available.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
sve_tests_sve_off_kvm() and test_query_cpu_model_expansion_kvm()
tests are now only being run if KVM is available. Drop the TCG
fallback.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 2
Various tests don't require TCG, but have '_tcg' in their name.
As this is misleading, remove 'tcg' from their name.
Reported-by: Igor Mammedov
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test.c | 142 -
1 file changed, 71 insertions(+), 71
Some tests require TCG, but don't have '_tcg' in their name,
while others do. Unify the test names by adding 'tcg' to the
TCG specific tests.
Reported-by: Igor Mammedov
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test.c | 8
1 file changed, 4 insertions(+), 4 dele
We might have a s390x/ppc64 QEMU binary built without the KVM
accelerator (configured with --disable-kvm).
Checking for /dev/kvm accessibility isn't enough, also check for the
accelerator in the binary.
Reviewed-by: David Gibson
Reviewed-by: Greg Kurz
Reviewed-by: Cornelia Huck
Reviewed-by: Ale
On 5/3/21 4:10 PM, Philippe Mathieu-Daudé wrote:
> Now than we can probe if the TCG accelerator is available
that
> at runtime with a QMP command, do it once at the beginning
> and only register the tests we can run.
> We can then replace the #ifdef'ry by an assertion.
>
> Signed-off-by: Philipp
Since commit 82bf7ae84ce ("target/arm: Remove KVM support for
32-bit Arm hosts") we can remove the comment / check added in
commit ab6b6a4 and directly run the bios-tables-test.
Reviewed-by: Eric Blake
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
--
On Tue, Apr 27, 2021 at 12:31 AM Gerd Hoffmann wrote:
> Hi,
>
> > Questions: Is this support in QEMU and if so got any pointers to source
> for
> > existing examples?
> > If not, any guidance on how to proceed?
>
> qemu has only usb host controller emulation, not any usb device
> controller emu
This was deprecated back in bc5ee6da7 (qcow2: Deprecate use of
qemu-img amend to change backing file), and no one in the meantime has
given any reasons why it should be supported. Time to make change
attempts a hard error (but for convenience, specifying the _same_
backing chain is not forbidden).
We've gone enough release cycles without noticeable pushback on our
intentions, so time to make it harder to create images that can form a
security hole due to a need for format probing rather than an explicit
format.
Eric Blake (2):
qcow2: Prohibit backing file changes in 'qemu-img amend'
qem
Back in commit d9f059aa6c (qemu-img: Deprecate use of -b without -F),
we deprecated the ability to create a file with a backing image that
requires qemu to perform format probing. Qemu can still probe older
files for backwards compatibility, but it is time to finish off the
ability to create such
On 5/3/21 1:57 AM, Richard Henderson wrote:
> We're going to change how to look up the call flags from a TCGop,
> so extract it as a helper.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/internal.h | 33 +
> tcg/optimize.c | 3 ++-
> tcg/tcg.c | 15 ++
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Let the compiler decide on inlining.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/plugin-gen.c | 12 +---
> 1 file changed, 5 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/3/21 4:36 PM, Eric Blake wrote:
> Back in commit d9f059aa6c (qemu-img: Deprecate use of -b without -F),
> we deprecated the ability to create a file with a backing image that
> requires qemu to perform format probing. Qemu can still probe older
> files for backwards compatibility, but it is t
Hi Richard,
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/internal.h | 5 +
> tcg/tcg.c | 5 ++---
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/internal.h b/tcg/internal.h
> index c2d5e9c42f..cd128e2a83 100644
> --
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Inline it into its one caller, tci_write_reg64.
> Drop the asserts that are redundant with tcg_read_r.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tci.c | 13 ++---
> 1 file changed, 2 insertions(+), 11 deletions(-)
Reviewed-by: Philipp
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/tci/tcg-target.h | 8
> tcg/tci.c| 42
> tcg/tci/tcg-target.c.inc | 32 ++
> 3 files changed, 78 insertions
On 5/3/21 1:57 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/tci/tcg-target.h | 12 +--
> tcg/tci.c| 44
> tcg/tci/tcg-target.c.inc | 9
> 3 files changed, 59 insertions(+), 6 deletions(-)
The following changes since commit 15106f7dc3290ff3254611f265849a314a93eb0e:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502' into
staging (2021-05-02 16:23:05 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply
On 5/3/21 1:57 AM, Richard Henderson wrote:
> These were already present in tcg-target.c.inc,
> but not in the interpreter.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tci/tcg-target.h | 20 ++--
> tcg/tci.c| 40
> 2 files
From: Bin Meng
This was accidentally dropped before. Add it back.
Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
Reported-by: Emmanuel Blot
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 20210331103612.654261-1-bmeng...@gmail
From: Vijai Kumar K
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 2021040118
From: Atish Patra
Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Message-Id: <20210319194534.2082397-2-atish.pa...@wdc.com>
[Changes by AF:
- Rebase on la
From: Axel Heider
Fix style to have a proper description of the parameter 'force-raw'.
Signed-off-by: Axel Heider
Reviewed-by: Alistair Francis
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a65...@gmx.de
Signed-off-by: Alistair Francis
---
docs/system/generic-loader.rst | 9 ++---
1 file cha
From: Vijai Kumar K
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210401181457.73039-5-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
include/hw/riscv/shakti_c.h | 2 ++
hw/riscv/shakti_c.c | 8 +++
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-id:
f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 44 ---
target/riscv/cpu.c| 2 +-
targe
From: Dylan Jhong
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong
Signed-off-by: Ruinland ChuanTzu Tsai
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210329034801.22667-1-dy...@andestech.com
Signed
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 14 +-
target/riscv/csr.c | 629 +++--
2 files cha
From: Vijai Kumar K
Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210401181457.73039-3-vi...@b
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/csr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b
Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.
Also add Bin who has been helping with reviews.
Signed-off-by: Alistair Francis
Acked-by: Bin Meng
Acked-by: Bastian Koppelmann
Reviewed-by: Philippe Mathieu-Daudé
Message-id:
6564ba829c40ad9aa7d2
From: Hou Weiying
Use address 0x390 and 0x391 for the ePMP CSRs.
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Reviewed-by: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
63245b559f477a9ce6d4f930136d2d7fd7f99c78.16
From: Vijai Kumar K
This is the initial implementation of Shakti UART.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210401181457.73039-4-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
include/hw/char/shakti_uart.h | 74 ++
hw/char/shakti_ua
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.fran...@
From: Jade Fink
Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.
Signed-off-by: Jade Fink
Reviewed-by: Alistair Francis
Message-id: 20210406113109.1031033-1-q...@jade.fyi
Signed-off-by: Alis
From: Hou Weiying
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.fran...@wdc.com
[ Changes by AF:
- Rebase on master
- F
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 3 +-
target/riscv/csr.c | 80 +-
2 files chan
imply VIRTIO_VGA for the virt machine, this fixes the following error
when specifying `-vga virtio` as a command line argument:
qemu-system-riscv64: Virtio VGA not available
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
7ac26fafee8bd59d2a0640f3233f8ad1ab270e1e.1617367317.gi
From: LIU Zhiwei
The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
However, when the predication is ture and a is 0, it should return maximum.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20210212150256.885-4-zhiwei_..
The spec is avaliable at:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 1 +
1 file chan
The RISC-V spec says:
if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
pmpaddri-1 are ignored.
The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.
Update the pmp_is_locked() function to not check the supporting fields
and instead enforce t
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 11 +++
target/riscv/csr.c | 37 ++---
From: Hou Weiying
This commit adds support for ePMP v0.9.1.
The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
Rev
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 11 ---
target/riscv/cpu_helper.c | 32
target/riscv/csr.c
From: Hou Weiying
Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Messag
From: Vijai Kumar K
Add documentation for Shakti C reference platform.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210412174248.8668-1-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
docs/system/riscv/shakti-c.rst | 82 ++
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.fran...@wdc.com
---
target
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/targe
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Message-id:
10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.fran...@wdc.com
---
target/riscv/pmp.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e1f5776316..78203291de 1
From: Frank Chang
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
In
From: Frank Chang
ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-id: 20210419060302.14075-1-frank.
From: Emmanuel Blot
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot
Reviewed-by: Alistair Francis
Message-id: fb9e
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 11 ---
target/riscv/cpu_helper.c | 24 +++-
2 files cha
From: Alexander Wagner
The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".
[1]
https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
Signed-off-b
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 10 --
target/riscv/csr.c | 12 ++--
target/riscv/translate.c | 19 +--
This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit
From: Emmanuel Blot
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot
Reviewed-by: Alistair Francis
Message-id: 20210421133236.11323-1-emmanuel.b...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
The Sun4uMachine class inherit from LinuxKernelTest to effectively only use
the KERNEL_COMMON_COMMAND_LINE attribute. This change remove that unneeded
dependency, making Sun4uMachine self-content.
I took the occasion to delint the code: the unused os import was
removed, imports were reordered, and
"Lucas Mateus Castro (alqotel)" writes:
> After the feedback from v1 I reworked the patch with suggested ideas and
> this version has less duplicated code and is overall simpler.
>
> This patch series is still a WIP, there are still 2 main problems I am
> trying to solve, I'll mention them in the
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu.h | 6 --
target/riscv/cpu.c | 6 +-
2 files changed, 5 insertions(+), 7 deletions(-)
This also ensures that the SD bit is not writable.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/cpu_bits.h | 6 --
target/riscv/csr.c
QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
and sifive_u machines. This patch moves that change from the
deprecated.rst file to the removed-features.rst file and the
target-riscv.rst.
Signed-off-by: Alistair Francis
---
docs/system/deprecated.rst | 19 ---
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Message-id:
4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/translate.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/translate.c b/tar
On Tue, May 4, 2021 at 1:13 AM Paolo Bonzini wrote:
>
> On 03/05/21 09:12, Alistair Francis wrote:
> >> deprecated.rst is mainly thought for the things that only have been marked
> >> as deprecated, but not changed yet. Once it's done, the items normally get
> >> moved to docs/system/removed-featu
On 4/30/21 3:15 AM, Richard Henderson wrote:
> These will be used by the decodetree trans_* functions
> to early-exit when the instruction set is not enabled.
>
> Signed-off-by: Richard Henderson
> ---
> target/ppc/translate.c | 26 ++
> 1 file changed, 26 insertions(+)
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/ppc/helper.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure w
This moved exec_command() to ConsoleMixIn class.
Only the multiprocess.py file were touched by that change, so its tests
were adapted.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/avocado_qemu/__init__.py | 22 ++
tests/acceptance/multiprocess.py
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-id:
024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.fran...@wdc.com
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion
The ReplayKernelBase class uses the wait_for_console_pattern from its
parent LinuxKernelTest class, thus it doesn't need to import that method
from avocado_qemu.
Signed-off-by: Wainer dos Santos Moschetta
---
tests/acceptance/replay_kernel.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/te
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Form a hex constant of the appropriate insnwidth.
> Begin using f-strings on changed lines.
>
> Signed-off-by: Richard Henderson
> ---
> scripts/decodetree.py | 66 +--
> 1 file changed, 38 insertions(+), 28 d
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> scripts/decodetree.py | 50 ---
> 1 file changed, 23 insertions(+), 27 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 4/30/21 3:15 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/ppc/insn32.decode | 2 ++
> target/ppc/insn64.decode | 11 +++
> target/ppc/translate/fixedpoint-impl.c.inc | 5 +
> 3 files changed, 18 insertions(+)
>
This created the ConsoleMixIn class to wrap the methods related with console
interaction with the guest that currently are loose in the avocado_qemu
package. It should be used as a mixin on the test classes.
At this point only the interrupt_interactive_console_until_pattern() was moved
to ConsoleM
The avocado_qemu package provides the following methods to interact with the
guest via console, which are mainly used on the acceptance boot tests:
exec_command(), exec_command_and_wait_for_pattern(),
wait_for_console_pattern(),
interrupt_interactive_console_until_pattern()
Those methods are l
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