From: Klaus Jensen
Remove the docs/specs/nvme.txt and replace it with proper documentation
in docs/system/nvme.rst.
Signed-off-by: Klaus Jensen
Reviewed-by: Philippe Mathieu-Daudé
---
docs/specs/nvme.txt | 23 -
docs/system/index.rst | 1 +
docs/system/nvme.rst | 225 +++
Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.
To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.
Signed-off-by: Yifei Jiang
Signed-off-by: Yipeng
From: Klaus Jensen
For most commands, when issuing an AIO, the BlockAIOCB is stored in the
NvmeRequest aiocb pointer when the AIO is issued. The main use of this
is cancelling AIOs when deleting submission queues (it is currently not
used for Abort).
However, some commands like Dataset Managemen
Add virtual time context description to vmstate_riscv_cpu. After cpu being
loaded, virtual time context is updated to KVM.
Signed-off-by: Yifei Jiang
Signed-off-by: Yipeng Yin
---
target/riscv/machine.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/machine.c b
at:
git://git.infradead.org/qemu-nvme.git tags/nvme-fixes-20210412-pull-request
for you to fetch changes up to 98f84f5a4eca5c03e32fff20f246d9b4b96d6422:
hw/block/nvme: drain namespaces on sq deletion (2021-04-12 08:55:23 +0200)
emulated nvme docs
From: Klaus Jensen
nvme_compare() fails to store the aiocb from the blk_aio_preadv() call.
Fix this.
Fixes: 0a384f923f51 ("hw/block/nvme: add compare command")
Cc: Gollu Appalanaidu
Signed-off-by: Klaus Jensen
Reviewed-by: Gollu Appalanaidu
Reviewed-by: Minwoo Im
---
hw/block/nvme.c | 3 ++-
From: Padmakar Kalghatgi
nvme_map_prp needs to calculate the number of list entries based on the
offset value. For the subsequent PRP2 list, need to ensure the number of
entries is within the MAX number of PRP entries for a page.
Signed-off-by: Padmakar Kalghatgi
Signed-off-by: Klaus Jensen
--
在 2021/4/9 下午4:17, Yongji Xie 写道:
On Fri, Apr 9, 2021 at 2:02 PM Jason Wang wrote:
在 2021/4/8 下午6:12, Xie Yongji 写道:
This commit introduces a new vhost-vdpa block device, which
will set up a vDPA device specified by a "vdpa-dev" parameter,
something like:
qemu-system-x86_64 \
-device
On Apr 9 19:39, Thomas Huth wrote:
On 06/04/2021 09.24, Klaus Jensen wrote:
On Apr 6 09:10, Philippe Mathieu-Daudé wrote:
On 4/5/21 7:54 PM, Klaus Jensen wrote:
From: Klaus Jensen
The Non-MDTS DMSRL limit must be recomputed when namespaces are
detached.
Fixes: 645ce1a70cb6 ("hw/block/nvme
Hyper-V 2016 refuses to boot on Skylake+ CPU models because they lack
'xsaves'/'vmx-xsaves' features and this diverges from real hardware. The
same issue emerges with AMD "EPYC" CPU model prior to version 3 which got
'xsaves' added. EPYC-Rome/EPYC-Milan CPU models have 'xsaves' enabled from
the ver
On Mon, Apr 12, 2021 at 3:14 PM Jason Wang wrote:
>
>
> 在 2021/4/9 下午4:17, Yongji Xie 写道:
> > On Fri, Apr 9, 2021 at 2:02 PM Jason Wang wrote:
> >>
> >> 在 2021/4/8 下午6:12, Xie Yongji 写道:
> >>> This commit introduces a new vhost-vdpa block device, which
> >>> will set up a vDPA device specified by
On Fri, Apr 9, 2021 at 3:21 PM Jason Wang wrote:
>
>
> 在 2021/4/8 下午5:38, Cindy Lu 写道:
> > Add configure notifier support in virtio and related driver
> > When peer is vhost vdpa, setup the configure interrupt function
> > vhost_net_start and release the resource when vhost_net_stop
>
>
> Actually
On Fri, Apr 9, 2021 at 3:12 PM Jason Wang wrote:
>
>
> 在 2021/4/8 下午5:38, Cindy Lu 写道:
> > to support configure interrupt, we need to
> > Add new call back function for config interrupt.
>
>
> There're brunch of capital issues.
>
>
> > now聽this call back function only used in vhost-vdpa driver
>
>
On Fri, Apr 9, 2021 at 2:57 PM Jason Wang wrote:
>
>
> 在 2021/4/8 下午5:38, Cindy Lu 写道:
> > To support config interrupt we need to add
> > a new type of interrupt process. So we introduce
> > the vector type
> > enum virtio_vector_type {
> > 聽 聽 聽 聽 VIRTIO_VQ_VECTOR,
> > 聽 聽 聽 聽 VIRTIO_CONFIG_VECTO
On Fri, Apr 9, 2021 at 3:24 PM Jason Wang wrote:
>
>
> 在 2021/4/8 下午5:38, Cindy Lu 写道:
> > Add support for configure interrupt. Set the notifier's fd to
> > the kernel driver when vdpa start. also set -1 while vdpa stop.
> > then the kernel will release the related resource
> >
> > Signed-off-by:
From: Andrew
Additional code that will be used for eBPF setting steering routine.
Signed-off-by: Andrew Melnychenko
---
net/tap-linux.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/tap-linux.h b/net/tap-linux.h
index 2f36d100fc..1d06fe0de6 100644
--- a/net/tap-linux.h
+++ b/net/tap-
This set of patches introduces the usage of eBPF for packet steering
and RSS hash calculation:
* RSS(Receive Side Scaling) is used to distribute network packets to
guest virtqueues by calculating packet hash
* Additionally adding support for the usage of RSS with vhost
The eBPF works on kernels 5.
From: Andrew
For now, that method supported only by Linux TAP.
Linux TAP uses TUNSETSTEERINGEBPF ioctl.
Signed-off-by: Andrew Melnychenko
---
include/net/net.h | 2 ++
net/tap-bsd.c | 5 +
net/tap-linux.c | 13 +
net/tap-solaris.c | 5 +
net/tap-stub.c| 5
From: Andrew
When RSS is enabled the device tries to load the eBPF program
to select RX virtqueue in the TUN. If eBPF can be loaded
the RSS will function also with vhost (works with kernel 5.8 and later).
Software RSS is used as a fallback with vhost=off when eBPF can't be loaded
or when hash pop
From: Andrew
Signed-off-by: Yuri Benditovich
Signed-off-by: Andrew Melnychenko
---
docs/devel/ebpf_rss.rst | 125
docs/devel/index.rst| 1 +
2 files changed, 126 insertions(+)
create mode 100644 docs/devel/ebpf_rss.rst
diff --git a/docs/devel/eb
From: Andrew
Added function that loads RSS eBPF program.
Added stub functions for RSS eBPF loader.
Added meson and configuration options.
By default, eBPF feature enabled if libbpf is present in the build system.
libbpf checked in configuration shell script and meson script.
Signed-off-by: Yuri
From: Andrew
RSS program and Makefile to build it.
The bpftool used to generate '.h' file.
The data in that file may be loaded by libbpf.
EBPF compilation is not required for building qemu.
You can use Makefile if you need to regenerate rss.bpf.skeleton.h.
Signed-off-by: Yuri Benditovich
Signed
From: Andrew
Signed-off-by: Yuri Benditovich
Signed-off-by: Andrew Melnychenko
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 58f342108e..e05a9fd9f6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3311,6 +3311,14 @@ F: include/hw/remo
On Fri, Apr 9, 2021 at 3:39 PM Jason Wang wrote:
>
>
> 在 2021/4/8 下午5:38, Cindy Lu 写道:
> > Add support for configure interrupt, use kvm_irqfd_assign and set the
> > gsi to kernel. When the configure notifier was eventfd_signal by host
> > kernel, this will finally inject an msix interrupt to guest
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
> In nested mode, we call the set_pasid_table() callback on each STE
> update to pass the guest stage 1 configuration to the host and
> apply it at physical level.
>
> In the case of live migration, we need to manual call the
s/manual/manually
>
On Mon, Apr 12, 2021 at 01:57:49PM +0530, Gollu Appalanaidu wrote:
On Sat, Apr 10, 2021 at 12:35:20AM +0900, Keith Busch wrote:
On Wed, Mar 31, 2021 at 02:54:27PM +0530, Gollu Appalanaidu wrote:
This is to add support for Device Self Test Command (DST) and
DST Log Page. Refer NVM Express specif
Patchew URL: https://patchew.org/QEMU/20210412082512.14998-1-and...@daynix.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210412082512.14998-1-and...@daynix.com
Subject: [PATCH v6 0/7] eBPF RSS support for virtio
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
> Hi all,
>
> Since the SMMUv3's nested translation stages[1] has been introduced by Eric,
> we
> need to pay attention to the migration of VFIO PCI devices in SMMUv3 nested
> stage
> mode. At present, it is not yet supported in QEMU. There ar
The commit in question is marked for stable:
commit 841c2be09fe4f495fe5224952a419bd8c7e5b455
Author: Maxim Levitsky
Date: Wed Jul 8 14:57:31 2020 +0300
kvm: x86: replace kvm_spec_ctrl_test_value with runtime test on the host
To avoid complex and in some cases incorrect logic
On Tue, Apr 06, 2021 at 06:51:14PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> If on nbd_close() we detach the thread (in
> nbd_co_establish_connection_cancel() thr->state becomes
> CONNECT_THREAD_RUNNING_DETACHED), after that point we should not use
> s->connect_thread (which is set to NULL), as
12.04.2021 11:45, Roman Kagan wrote:
On Tue, Apr 06, 2021 at 06:51:14PM +0300, Vladimir Sementsov-Ogievskiy wrote:
If on nbd_close() we detach the thread (in
nbd_co_establish_connection_cancel() thr->state becomes
CONNECT_THREAD_RUNNING_DETACHED), after that point we should not use
s->connect_th
On Sat, Apr 10, 2021 at 11:03:19AM +0200, Philippe Mathieu-Daudé wrote:
> On 4/10/21 4:58 AM, Richard Henderson wrote:
> > On development branches, it's not uncommon to push
> > temporary --fixup patches, and normally one doesn't
> > sign those. But then of course one get hate-mail
> > from the gi
Hi Peter,
On 4/8/21 12:36 PM, Peter Maydell wrote:
> On Thu, 8 Apr 2021 at 11:23, Claudio Fontana wrote:
>> Mainly for this code here a question from my side: is the current code
>> actually already "wrong"?
>>
>> I mean, we unconditionally set the aarch64-capable cpu classes to all use
>> aarc
On Fri, Apr 09, 2021 at 07:58:48PM -0700, Richard Henderson wrote:
> On development branches, it's not uncommon to push
> temporary --fixup patches, and normally one doesn't
> sign those. But then of course one get hate-mail
> from the gitlab-ci job about the failing test.
>
> Is there a way to m
On Sun, 11 Apr 2021 at 16:15, Richard Henderson
wrote:
>
> On 4/10/21 10:24 AM, Michael Rolnik wrote:
> > Please review.
>
>
> The first 256b is i/o, the next 768b are ram. But having changed the page
> size, it should mean that the first 1k are now treated as i/o.
>
> We do have a path by which
On Sat, Apr 3, 2021 at 4:04 AM Alistair Francis
wrote:
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu.h | 6 --
> target/riscv/cpu.c | 6 +-
> 2 files changed, 5 insertions(+), 7 deletions(-)
>
Reviewed-by: Bin Meng
On Sat, Apr 3, 2021 at 4:04 AM Alistair Francis
wrote:
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/translate.c | 6 --
> 1 file changed, 6 deletions(-)
>
Reviewed-by: Bin Meng
On Sat, Apr 3, 2021 at 4:04 AM Alistair Francis
wrote:
Worth mentioning that this also fixed the issue of a writable SD bit
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu_bits.h | 6 --
> target/riscv/csr.c | 9 -
> 2 files changed, 8 insertions(+), 7 deletions(-
On Sat, Apr 3, 2021 at 4:05 AM Alistair Francis
wrote:
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu_bits.h | 6 --
> 1 file changed, 6 deletions(-)
>
Reviewed-by: Bin Meng
Some downstreams rename the QEMU binary to "qemu-kvm". This breaks
qtest_get_arch(), which attempts to parse the target architecture from
the QTEST_QEMU_BINARY environment variable.
Print an error instead of returning the architecture "kvm". Things fail
in weird ways when the architecture string i
On Mon, 12 Apr 2021 at 10:05, Claudio Fontana wrote:
>
> Hi Peter,
>
> On 4/8/21 12:36 PM, Peter Maydell wrote:
> > On Thu, 8 Apr 2021 at 11:23, Claudio Fontana wrote:
> >> Mainly for this code here a question from my side: is the current code
> >> actually already "wrong"?
> >>
> >> I mean, we
On 12/04/2021 11.18, Stefan Hajnoczi wrote:
Some downstreams rename the QEMU binary to "qemu-kvm". This breaks
qtest_get_arch(), which attempts to parse the target architecture from
the QTEST_QEMU_BINARY environment variable.
Print an error instead of returning the architecture "kvm". Things fai
On Mon, 12 Apr 2021 at 10:35, Thomas Huth wrote:
>
> On 12/04/2021 11.18, Stefan Hajnoczi wrote:
> > Some downstreams rename the QEMU binary to "qemu-kvm". This breaks
> > qtest_get_arch(), which attempts to parse the target architecture from
> > the QTEST_QEMU_BINARY environment variable.
> >
> >
On Fri, 9 Apr 2021 19:13:46 +0530
Tarun Gupta wrote:
> Document interfaces used for VFIO device migration. Added flow of state
> changes
> during live migration with VFIO device.
>
> Co-developed-by: Kirti Wankhede
This still needs Kirti's S-o-b as well (i.e. both tags need to be
paired.)
>
On Sat, 10 Apr 2021 at 16:15, Peter Maydell wrote:
> I do wonder if the right fix to that would be to make TYPE_MACHINE
> be a subtype of TYPE_DEVICE, though -- machines not being subtypes
> of device has other annoying effects, like their not having reset
> methods or being able to register vmsta
Hi Peter,
On 4/12/21 12:11 PM, Peter Maydell wrote:
> On Sat, 10 Apr 2021 at 16:15, Peter Maydell wrote:
>> I do wonder if the right fix to that would be to make TYPE_MACHINE
>> be a subtype of TYPE_DEVICE, though -- machines not being subtypes
>> of device has other annoying effects, like their
From: Zenghui Yu
The GSIV values in SMMUv3 IORT node are not correct as they don't match
the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
our emulated vSMMU.
Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
Signed-off-by: Zenghui Yu
Acked-by: E
From: Zenghui Yu
In emulation of the CFGI_STE_RANGE command, we now take StreamID as the
start of the invalidation range, regardless of whatever the Range is,
whilst the spec clearly states that
- "Invalidation is performed for an *aligned* range of 2^(Range+1)
StreamIDs."
- "The bottom R
:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210412
for you to fetch changes up to 52c01ada86611136e3122dd139788dbcbc292d86:
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 (2021-04-12 11:06:24 +0100)
target
From: Richard Henderson
Unfortuately, the elements of PAGE_* were not in numerical
order and so PAGE_ANON was added to an "unused" bit.
As an arbitrary choice, move PAGE_TARGET_{1,2} together.
Cc: Laurent Vivier
Fixes: 26bab757d41b ("linux-user: Introduce PAGE_ANON")
Buglink: https://bugs.launc
From: Richard Henderson
We can remove PAGE_WRITE when (internally) marking a page
read-only because it contains translated code.
This can be triggered by tests/tcg/aarch64/bti-2, after
having serviced SIGILL trampolines on the stack.
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
S
From: Richard Henderson
Using mprotect() to change PROT_* does not change the MAP_ANON
previously set with mmap(). Our linux-user version of MTE only
works with MAP_ANON pages, so losing PAGE_ANON caused MTE to
stop working.
Reported-by: Stephen Long
Signed-off-by: Richard Henderson
Reviewed-
Patchew URL:
https://patchew.org/QEMU/20210412103152.28433-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210412103152.28433-1-peter.mayd...@linaro.org
Subject: [PULL 0/5] target-arm queue
On Mon, 12 Apr 2021 at 11:31, Philippe Mathieu-Daudé wrote:
> TIL MachineClass::reset().
>
> - hw/hppa/machine.c
> - hw/i386/pc.c
>
> Used to reset CPUs manually because CPUs aren't sysbus-reset.
pc_machine_reset() is not resetting the CPUs -- it is
re-resetting the APIC devices, which looks li
On 4/7/21 9:57 PM, Mark Cave-Ayland wrote:
> The const pointer returned by fifo8_pop_buf() lies directly within the array
> used
> to model the FIFO. Building with address sanitizers enabled shows that if the
> caller expects a minimum number of bytes present then if the FIFO is nearly
> full,
>
On Wed, 7 Apr 2021 at 21:02, Mark Cave-Ayland
wrote:
>
> The const pointer returned by fifo8_pop_buf() lies directly within the array
> used
> to model the FIFO. Building with address sanitizers enabled shows that if the
> caller expects a minimum number of bytes present then if the FIFO is nearl
On 4/12/21 12:44 PM, Peter Maydell wrote:
> On Mon, 12 Apr 2021 at 11:31, Philippe Mathieu-Daudé wrote:
>> TIL MachineClass::reset().
>>
>> - hw/hppa/machine.c
>> - hw/i386/pc.c
>>
>> Used to reset CPUs manually because CPUs aren't sysbus-reset.
>
> pc_machine_reset() is not resetting the CPUs
ping?
On 4/6/21 4:39 PM, Alexander Bulekov wrote:
> On 210406 1539, Philippe Mathieu-Daudé wrote:
>> sparse-mem.c is added to the 'mem_ss' source set, which itself
>> is conditionally added to softmmu_ss if CONFIG_MEM_DEVICE is
>> selected.
>> But if CONFIG_MEM_DEVICE isn't selected, we get a link
into staging (2021-04-10
> 16:58:56 +0100)
>
> are available in the Git repository at:
>
> git://git.infradead.org/qemu-nvme.git tags/nvme-fixes-20210412-pull-request
>
> for you to fetch changes up to 98f84f5a4eca5c03e32fff20f246d9b4b96d6422:
>
> hw/block/
> You will need to fix these style errors.
Yeah, I was using the checkpatch on a manually generated diff, so I could
commit everything with the correct style, but it didn't go over the new file,
and I forgot to run it after all the commits -.-'
> For future reference, please CC me explicitly on
This series enables 2nd DAWR support on p10 qemu guest. 2nd
DAWR is new watchpoint added in Power10 processor. Kernel/kvm
patches are already in[1]. Watchpoint on powerpc TCG guest is
not supported and thus 2nd DAWR is not enabled for TCG mode.
Patches apply fine on qemu/master branch (f2afdc2ad94
As per the PAPR, bit 0 of byte 64 in pa-features property indicates
availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to
find whether kvm supports 2nd DAWR or not. If it's supported, allow
user to set the pa-feature bit
Power10 is introducing second DAWR. Use real register names (with
suffix 0) from ISA for current macros and variables used by Qemu.
One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel
uapi header and thus not changed in kernel as well as Qemu.
Signed-off-by: Ravi Bangoria
Reviewed-
Update against Linux 5.12-rc3
Signed-off-by: Ravi Bangoria
---
include/standard-headers/drm/drm_fourcc.h | 23 -
include/standard-headers/linux/input.h| 2 +-
.../standard-headers/rdma/vmw_pvrdma-abi.h| 7 ++
linux-headers/asm-generic/unistd.h| 4 +-
linux-head
On 3/28/21 8:40 PM, Richard Henderson wrote:
> On 3/26/21 1:36 PM, Claudio Fontana wrote:
>> extract the exception handling code from cpu-sysemu,
>> and split it into general arm code and an AArch64-specific part.
>>
>> Signed-off-by: Claudio Fontana
>> ---
>> target/arm/cpu-exceptions-aa64.h |
> A general advice for this whole series is: make sure you add in some
> words explaining why you decided to make a particular change. It will be
> much easier to review if we know what were the logical steps leading to
> the change.
Fair point, I should've thought about that.
> > This commit doe
The following changes since commit 555249a59e9cdd6b58da103aba5cf3a2d45c899f:
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request'
into staging (2021-04-10 16:58:56 +0100)
are available in the Git repository at:
https://src.openvz.org/scm/~vsementsov/qemu.git tags/pu
If on nbd_close() we detach the thread (in
nbd_co_establish_connection_cancel() thr->state becomes
CONNECT_THREAD_RUNNING_DETACHED), after that point we should not use
s->connect_thread (which is set to NULL), as running thread may free it
at any time.
Still nbd_co_establish_connection() does exac
Hi Markus,
Any suggestions on this patch?
Thanks
Li
On Fri, Mar 26, 2021 at 3:40 PM Markus Armbruster wrote:
> Li Zhang writes:
>
> > Hi,
> >
> > Any comments about this patch?
>
> I wanted to review this before my Easter break, but I'm out of time :(
>
> When I'm back (April 6), I'll check w
Im not sure about what "better version" means, but my guess would be a faster
or more reliable version. If that's the case:
> for (int i = 0; i < strlen(source); i++) {
Since you're going on ebyte at a time, there's no need to know how big the
array is. As a stopping condition you could use
On Fri, Apr 09, 2021 at 02:17:13PM +0100, Daniel P. Berrangé wrote:
> On Fri, Apr 09, 2021 at 03:12:45PM +0200, Gerd Hoffmann wrote:
> > Hi,
> >
> > > eg a trace point "dma_map_wait" gets mapped to probes in many
> > > .stp files, once per target, because we need to match based on
> > > the exec
On 4/12/21 1:44 PM, Ravi Bangoria wrote:
> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to
> find whether kvm supports 2nd DAWR or not. If it'
Li Zhang writes:
> Hi Markus,
>
> Any suggestions on this patch?
I understand PATCH 1/2 got superseded by Lukas's "[PATCH v8 0/4] yank:
Add chardev tests and fixes". I trust Marc-André will take care of it
in due time.
Before I look at the actual patch: does this patch depend on Lukas's fix
or
On Sun, 11 Apr 2021 at 14:52, Chetan wrote:
> char *qemu_strncpy(char destination[], char source[], size_t destination_size)
> {
> /* Looping through the array and copying the characters from
> * source to destination.
> */
> for (int i = 0; i < strlen(source); i++) {
> d
Hi Markus,
[PATCH 1/2] Fix the segment fault when calling yank_register_instance is
reworked by Lukas.
And his patches have been merged to master branch of qemu.
[PATCH 2/2] Support monitor chardev hotswap with QMP is to change monitor
backend with chardev-change. It is not implemented yet.
On
The AN524 FPGA image supports two memory maps, which differ
in where the QSPI and BRAM are. In the default map, the BRAM
is at 0x_, and the QSPI at 0x2800_. In the second
map, they are the other way around.
In hardware, the initial mapping can be selected by the user
by writing either
On some boards, SCC config register CFG0 bit 0 controls whether
parts of the board memory map are remapped. Support this with:
* a device property scc-cfg0 so the board can specify the
initial value of the CFG0 register
* an outbound GPIO line which tracks bit 0 and which the board
can wire
The MPS2 SCC device doesn't have any documentation of its properties;
add a "QEMU interface" format comment describing them.
Signed-off-by: Peter Maydell
---
include/hw/misc/mps2-scc.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/
The AN524 FPGA image supports two memory maps, which differ
in where the QSPI and BRAM are. In the default map, the BRAM
is at 0x_, and the QSPI at 0x2800_. In the second
map, they are the other way around.
In hardware, the initial mapping can be selected by the user
by writing either
Hi Eric,
On 2021/4/8 21:46, Auger Eric wrote:
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
Extract part of the code from vfio_sync_dirty_bitmap to form a
new helper, which allows to mark dirty pages of a RAM section.
This helper will be called for nested stage.
Signed-off-by: Kunkun Ji
Hi Eric,
On 2021/4/12 16:40, Auger Eric wrote:
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
Hi all,
Since the SMMUv3's nested translation stages[1] has been introduced by Eric, we
need to pay attention to the migration of VFIO PCI devices in SMMUv3 nested
stage
mode. At present, it is
Hi Eric,
On 2021/4/8 21:56, Auger Eric wrote:
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
On Intel, the DMA mapped through the host single stage. Instead
we set up the stage 2 and stage 1 separately in nested mode as there
is no "Caching Mode".
You need to rewrite the above sentences,
Hi Eric,
On 2021/4/12 16:34, Auger Eric wrote:
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
In nested mode, we call the set_pasid_table() callback on each STE
update to pass the guest stage 1 configuration to the host and
apply it at physical level.
In the case of live migration, we nee
Bruno Piazera Larsen writes:
>> > This commit does the necessary code motion from translate_init.c.inc
>>
>> For instance, I don't immediately see why these changes are necessary. I
>> see that translate_init.c.inc already has some `#ifdef CONFIG_TCG`, so
>> why do we need to move a bunch of code
Claudio Fontana writes:
> get_phys_addr is needed for KVM too, and in turn it requires
> the aa64_va_parameter* family of functions.
>
> Create cpu-mmu and cpu-mmu-sysemu to store these and
> other mmu-related functions.
>
> Signed-off-by: Claudio Fontana
> Reviewed-by: Richard Henderson
> --
On Mon, Apr 12, 2021 at 11:35:40AM +0200, Thomas Huth wrote:
> On 12/04/2021 11.18, Stefan Hajnoczi wrote:
> > Some downstreams rename the QEMU binary to "qemu-kvm". This breaks
> > qtest_get_arch(), which attempts to parse the target architecture from
> > the QTEST_QEMU_BINARY environment variable
On Wed 17 Mar 2021 03:34:59 PM CET, Vladimir Sementsov-Ogievskiy
wrote:
> Passing parent aio context is redundant, as child_class and parent
> opaque pointer are enough to retrieve it. Drop the argument and use new
> bdrv_child_get_parent_aio_context() interface.
>
> Signed-off-by: Vladimir Semen
Hi Richard,
Thanks for your quick reply.
For the time, ARCv3 is an under development architecture and
unfortunately, for the time being, there is no public documentation
available.
Please notice that this should be all available once ARCv3 gets released.
QEMU ARCv3 port is really an early stag
Hi Richard,
I totally understand your position with a new scripting language and the
unclean code produced by the auto generated tools.
In order to ease out the review process, I propose to drop the idea of
the generated code and cleanup by hand all of the semfunc.c functions.
What is you opinio
Some downstreams rename the QEMU binary to "qemu-kvm". This breaks
qtest_get_arch(), which attempts to parse the target architecture from
the QTEST_QEMU_BINARY environment variable.
Print an error instead of returning the architecture "kvm". Things fail
in weird ways when the architecture string i
v2:
* Fix "will unavailable" typo [Thomas]
I recently needed to troubleshoot a case where qos-test terminated immediately
with no output. In other words, qos-test decided that no tests are runnable.
After lots of head scratching and some help from Emanuele it turned out that
the machine types we
Cc: Emanuele Giuseppe Esposito
Cc: Paolo Bonzini
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
---
tests/qtest/libqos/qgraph.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/libqos/qgraph.c b/tests/qtest/libqos/qgraph.c
index b3b1a31f81..d1
On 12/04/2021 16.21, Stefan Hajnoczi wrote:
On Mon, Apr 12, 2021 at 11:35:40AM +0200, Thomas Huth wrote:
On 12/04/2021 11.18, Stefan Hajnoczi wrote:
Some downstreams rename the QEMU binary to "qemu-kvm". This breaks
qtest_get_arch(), which attempts to parse the target architecture from
the QTES
It can be tricky to troubleshoot qos-test when a test won't execute. Add
an explanation of how to trace qgraph node connectivity and find which
node has the problem.
Cc: Emanuele Giuseppe Esposito
Cc: Paolo Bonzini
Signed-off-by: Stefan Hajnoczi
---
docs/devel/qgraph.rst | 58 +
Hi Peter,
On 4/12/21 3:43 PM, Peter Maydell wrote:
> The AN524 FPGA image supports two memory maps, which differ
> in where the QSPI and BRAM are. In the default map, the BRAM
> is at 0x_, and the QSPI at 0x2800_. In the second
> map, they are the other way around.
>
> In hardware, th
On Sat, Apr 10, 2021 at 06:41:03AM +0200, Thomas Huth wrote:
> On 09/04/2021 21.01, Stefan Hajnoczi wrote:
> > It can be tricky to troubleshoot qos-test when a test won't execute. Add
> > an explanation of how to trace qgraph node connectivity and find which
> > node has the problem.
> >
> > Cc: E
On 12/04/2021 16.35, Thomas Huth wrote:
On 12/04/2021 16.21, Stefan Hajnoczi wrote:
On Mon, Apr 12, 2021 at 11:35:40AM +0200, Thomas Huth wrote:
On 12/04/2021 11.18, Stefan Hajnoczi wrote:
Some downstreams rename the QEMU binary to "qemu-kvm". This breaks
qtest_get_arch(), which attempts to pa
On 12/04/2021 16.30, Stefan Hajnoczi wrote:
Some downstreams rename the QEMU binary to "qemu-kvm". This breaks
qtest_get_arch(), which attempts to parse the target architecture from
the QTEST_QEMU_BINARY environment variable.
Print an error instead of returning the architecture "kvm". Things fai
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> On Fri, Apr 09, 2021 at 10:34:30AM +0100, Daniel P. Berrangé wrote:
> > On Thu, Apr 08, 2021 at 08:11:54PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > > I had a quick go at trying NBD as well, but I
On Mon, 12 Apr 2021 at 15:37, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 4/12/21 3:43 PM, Peter Maydell wrote:
> > The AN524 FPGA image supports two memory maps, which differ
> > in where the QSPI and BRAM are. In the default map, the BRAM
> > is at 0x_, and the QSPI at 0x2800_
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