Re: [PATCH v4 17/32] sparc: Use DEFINE_PROP for nwindows property

On Mon, Dec 14, 2020 at 03:42:48PM +0100, Igor Mammedov wrote: > On Fri, 11 Dec 2020 17:05:14 -0500 > Eduardo Habkost wrote: > > > Use the DEFINE_PROP macro (which will set extra fields in the > > struct) instead of initializing a Property struct manually. > > > > Signed-off-by: Eduardo Habkost

Re: [PATCH v4 15/32] qdev: Move softmmu properties to qdev-properties-system.h

On Mon, Dec 14, 2020 at 03:25:41PM +0100, Igor Mammedov wrote: > On Fri, 11 Dec 2020 17:05:12 -0500 > Eduardo Habkost wrote: > > > Move the property types and property macros implemented in > > qdev-properties-system.c to a new qdev-properties-system.h > > header. > > > > Signed-off-by: Eduardo

Re: [PATCH v2 3/4] hw/adc: Add an ADC module for NPCM7XX

Thanks for your comment! We'll incorporate them into our next patch version. We plan to let the user use QOM get/set QMP commands to control ADC/PWM values, similar to hw/misc/tmp105.c. The user can set a voltage value as input using QOM-set, and the QEMU guest can read the converted value through

[PATCH] iotests/210: Fix reference output

Commit 8b1170012b1 has added a global maximum disk length for the block layer, so the error message when creating an overly large disk has changed. Fixes: 8b1170012b1de6649c66ac1887f4df7e312abf3b ("block: introduce BDRV_MAX_LENGTH") Signed-off-by: Max Reitz --- tests/qemu-iotests/210.out

Re: [RFC PATCH 1/2] gitlab-ci: Step in to maintain the fedora-i386-cross runner

On 12/14/20 1:35 PM, Thomas Huth wrote: > On 11/12/2020 18.17, Philippe Mathieu-Daudé wrote: >> As I am interested in using the runner based on the fedora-i386-cross >> docker image, add a smoke test job to be sure this image is usable, >> and set the JOB_MAINTAINER_NAME/JOB_MAINTAINER_EMAIL variab

[PATCH] iotests: Quote $cmd in _send_qemu_cmd

With bash 5.1, the output of the following script (which creates an array with a single element, then takes a single-element slice from that array, and echos the result) changes: a=("double space") a=${a[@]:0:1} echo "$a" from "double space" to "double space", i.e. all white space is pres

Re: [PATCH 1/2] target/arm: add support for FEAT_DIT, Data Independent Timing

On 12/11/20 2:37 PM, Peter Maydell wrote: On Fri, 11 Dec 2020 at 19:51, Richard Henderson wrote: I'll let Peter weigh in, but I think it makes sense to move the SS bit somewhere else (e.g. env->pstate) and merge it into SPSR_ELx upon interrupt. While what we're doing here is convenient, it's no

Re: [PATCH v4 25/32] qdev: Make qdev_class_add_property() more flexible

On Mon, Dec 14, 2020 at 04:00:59PM +0100, Igor Mammedov wrote: > On Fri, 11 Dec 2020 17:05:22 -0500 > Eduardo Habkost wrote: > > > Support Property.set_default and PropertyInfo.description even if > > PropertyInfo.create is set. > > > > Signed-off-by: Eduardo Habkost > > --- > > Changes v1 -> v

[PATCH v2 16/16] target/mips: Only build TCG code when CONFIG_TCG is set

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-20-f4...@amsat.org> --- target/mips/meson.build | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 5a49951c6d7

[PATCH v2 00/16] target/mips: Boring code reordering + add "translate.h"

Hi, This series contains the patches previously sent in "Boring code reordering" [1] and "Add translate.h and fpu_translate.h headers" [2]. I removed the patches merged and addressed Richard review comments. Missing review: 1 3-5 9-11 14 15 Available as: https://gitlab.com/philmd/qemu/-/commit

[PATCH v2 01/16] target/mips: Inline cpu_state_reset() in mips_cpu_reset()

Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 26 +- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index aadc6f8e74d..7a0dcb11ecd 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -104,10 +104,1

[PATCH v2 03/16] target/mips: Add !CONFIG_USER_ONLY comment after #endif

To help understand ifdef'ry, add comment after #endif. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/helper.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 87296fbad69..cdd7704789d 100644 --- a/target/m

[PATCH v2 02/16] target/mips: Extract FPU helpers to 'fpu_helper.h'

Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201120210844.2625602-2-f4...@amsat.org> --- target/mips/fpu_helper.h | 59 target/mips/internal.h

[PATCH v2 05/16] target/mips: Extract common helpers from helper.c to common_helper.c

The rest of helper.c is TLB related. Extract the non TLB specific functions to a new file, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 2 + target/mips/cpu.c | 215 +++-

[PATCH v2 04/16] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs

Signed-off-by: Philippe Mathieu-Daudé --- target/mips/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index cdd7704789d..0692e232f0a 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -552,9 +552,7 @@ hwaddr mips_cpu_get_phys_

[PATCH v2 06/16] target/mips: Rename helper.c as tlb_helper.c

This file contains functions related to TLB management, rename it as 'tlb_helper.c'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-13-f4...@amsat.org> --- target/mips/{helper.c => tlb_helper.c} | 2 +- target/mips/meson.build

[PATCH v2 08/16] target/mips: Move mmu_init() functions to tlb_helper.c

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-15-f4...@amsat.org> --- target/mips/internal.h | 1 + target/mips/tlb_helper.c | 46 ++ target/mips/translate_init.c.inc | 48 --

[PATCH v2 10/16] target/mips: Replace gen_exception_err(err=0) by gen_exception_end()

generate_exception_err(err=0) is simply generate_exception_end(). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index d2614796214..2662cf26fe7 100644 --

[PATCH v2 07/16] target/mips: Fix code style for checkpatch.pl

We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-14-f4...@amsat.org> --- target/mips/translate_init.c.inc | 36 1 file changed, 18 insertions(+), 18 dele

[PATCH v2 09/16] target/mips: Rename translate_init.c as cpu-defs.c

This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c| 2 +- target/mips/{translate_init.c.inc => cpu-defs.c.inc} | 0 2 files changed, 1 insertion(+), 1

[PATCH v2 13/16] target/mips/translate: Add declarations for generic code

Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-3-f4...@amsat.org> --

[PATCH v2 11/16] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction

gen_reserved_instruction() is easier to read than generate_exception_end(ctx, EXCP_RI), replace it. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 724 1 file changed, 362 insertions(+), 362 deletions(-) diff --git a/target/mips/tran

[PATCH v2 12/16] target/mips/translate: Extract DisasContext structure

Extract DisasContext to a new 'translate.h' header so different translation files (ISA, ASE, extensions) can use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-2-f4...@amsat.org> --- target/mips/translate.h | 50 +

Re: [PULL 00/30] ppc-for-6.0 queue 20201214

> > are available in the Git repository at: > > https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-20201214 > > for you to fetch changes up to 07b10bc42cc83a49acaa783383a69fb59d7ff71a: > > spapr.c: set a 'kvm-type' default

Re: [PATCH 1/2] target/arm: add support for FEAT_DIT, Data Independent Timing

On Mon, 14 Dec 2020 at 18:11, Rebecca Cran wrote: > > On 12/11/20 2:37 PM, Peter Maydell wrote: > > On Fri, 11 Dec 2020 at 19:51, Richard Henderson > > wrote: > >> I'll let Peter weigh in, but I think it makes sense to move the SS bit > >> somewhere else (e.g. env->pstate) and merge it into SPSR_

[PATCH v2 15/16] target/mips: Extract FPU specific definitions to translate.h

Extract FPU specific definitions that can be used by ISA / ASE / extensions to translate.h header. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.h | 71 + target/mips/translate.c | 70 2 files chan

[PATCH v2 14/16] target/mips: Declare generic FPU functions in 'translate.h'

Some FPU translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.h | 7 +++ target/mips/translate.c | 12 ++-- 2 files changed, 13 insertions(+), 6 deletions(-) diff --g

Re: [PATCH v12 16/23] cpu: Move synchronize_from_tb() to tcg_ops

On Sat, Dec 12, 2020 at 04:55:23PM +0100, Claudio Fontana wrote: > From: Eduardo Habkost > > since tcg_cpu_ops.h is only included in cpu.h, > and as a standalone header it is not really useful, > as tcg_cpu_ops.h starts requiring cpu.h defines, > enums, etc, as well as (later on in the series), >

Re: [PATCH v4 00/32] qdev property code cleanup

On Fri, Dec 11, 2020 at 05:04:57PM -0500, Eduardo Habkost wrote: > This code contains the first 32 patches from the series: > > Subject: [PATCH v3 00/53] Make qdev static property API usable by any QOM > type > > https://lore.kernel.org/qemu-devel/20201112214350.872250-1-ehabk...@redhat.com

Re: [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

Alex Bennée writes: > Hmm scratch that... it fails in a number of linux-user only builds with: > > /usr/bin/ld: > libqemu-aarch64_be-linux-user.fa.p/linux-user_aarch64_cpu_loop.c.o: in > function `cpu_loop': > /builds/stsquad/qemu/build/../linux-user/aarch64/cpu_loop.c:133: undefined > ref

[PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

This series adds support for RISC-V Semihosting, version 0.2 as specified here: https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 This specification references the ARM semihosting release 2.0 as specified here: https://static.docs.arm.com/100863/0200/semihosting.pd

[PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState *

This makes all of the internal interfaces architecture-independent and renames the internal functions to use the 'common_semi' prefix instead of 'arm' or 'arm_semi'. To do this, some new architecture-specific internal helper functions were created: static inline target_ulong common_semi_a

[PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set

env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard --- v2 Explicit

[PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ

These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 16 include/qemu/timer.h | 2 ++ util/qemu-timer-common.c | 4 3 files changed, 22 insertions(+) diff --git a/hw/semihosting/comm

[PATCH 6/9] riscv: Add semihosting support for user mode

From: Kito Cheng This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng Reviewed-by: Keith Packard --- linux-user/riscv/cpu_loop.c | 5 +

[PATCH 2/9] semihosting: Change common-semi API to be architecture-independent

The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-b

[PATCH 8/9] semihosting: Implement SYS_TMPNAM

Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b1368d945c..b0648c381

[PATCH 5/9] riscv: Add semihosting support

Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is handl

[PATCH 1/9] semihosting: Move ARM semihosting code to shared directories

This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONF

[PATCH 9/9] semihosting: Implement SYS_ISERROR

Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard --- hw/semihosting/common-semi.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b0648c3812..abc15bf219 100644 --- a/hw/semihosting/commo

[PATCH 0/3] target/arm: add FEAT_TLBIOS and FEAT_TLBIRANGE support

This series adds support for FEAT_TLBIOS and FEAT_TLBIRANGE, both of which are mandatory in ARMv8.4. Rebecca Cran (3): target/arm: add FEAT_TLBIOS support target/arm: add FEAT_TLBIRANGE support target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type accel/tcg/cputlb.c | 24 ++

[PATCH 1/3] target/arm: add FEAT_TLBIOS support

ARMv8.4 adds the mandatory FEAT_TLBIOS, which provides instructions for TLB invalidation of entries in the Outer Shareable domain. Signed-off-by: Rebecca Cran --- target/arm/helper.c | 30 1 file changed, 30 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper

[PATCH 3/3] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

Enable support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type. Signed-off-by: Rebecca Cran --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 649213082ff9..4b9c5887cc1c 100644

[PATCH 2/3] target/arm: add FEAT_TLBIRANGE support

ARMv8.4 adds the mandatory FEAT_TLBIRANGE, which provides instructions for invalidating ranges of entries. Signed-off-by: Rebecca Cran --- accel/tcg/cputlb.c | 24 ++ include/exec/exec-all.h | 39 +++ target/arm/helper.c | 273 3 files changed, 336 insertions(+)

[PATCH 0/3] qemu-timer: Make timer_free() imply timer_del()

Currently timer_free() is a simple wrapper for g_free(). This means that the timer being freed must not be currently active, as otherwise QEMU might crash later when the active list is processed and still has a pointer to freed memory on it. As a result almost all calls to timer_free() are preced

[PATCH 2/3] scripts/coccinelle: New script to remove unnecessary timer_del() calls

Now that timer_free() implicitly calls timer_del(), sequences timer_del(mytimer); timer_free(mytimer); can be simplified to just timer_free(mytimer); Add a Coccinelle script to do this transformation. Signed-off-by: Peter Maydell --- scripts/coccinelle/timer-del-timer-free.cocci | 18 +++

[PATCH 3/3] Remove superfluous timer_del() calls

This commit is the result of running the timer-del-timer-free.cocci script on the whole source tree. Signed-off-by: Peter Maydell --- I could split this up into multiple patches -- is that worth while ? --- block/iscsi.c | 2 -- block/nbd.c| 1 - block/qcow2.

[PATCH 1/3] util/qemu-timer: Make timer_free() imply timer_del()

Currently timer_free() is a simple wrapper for g_free(). This means that the timer being freed must not be currently active, as otherwise QEMU might crash later when the active list is processed and still has a pointer to freed memory on it. As a result almost all calls to timer_free() are preced

Re: [PULL 00/26] MIPS patches for 2020-12-13

On Sun, 13 Dec 2020 at 20:22, Philippe Mathieu-Daudé wrote: > > The following changes since commit ad717e6da3852b5729217d7938eecdb81c546114: > > Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging > (2020-12-12 00:20:46 +) > > are available in the Git repository at:

[PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- target/riscv/cpu.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..9c064f3094 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -44,6 +44,1

[PATCH v3 00/15] RISC-V: Start to remove xlen preprocess

The RISC-V QEMU port currently has lot of preprocessor directives that check if we are targetting a 32-bit or 64-bit CPU. This means that the 64-bit RISC-V target can not run 32-bit CPUs. This is different to most other QEMU architectures and doesn't allow us to mix xlens (such as when running Hype

[PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs

Currently the riscv_is_32_bit() function only supports the generic rv32 CPUs. Extend the function to support the SiFive and LowRISC CPUs as well. Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b

[PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 33 +++-- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 32a6916b8a..7d6f

[PATCH v3 08/15] hw/riscv: sifive_u: Remove compile time XLEN checks

Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 55 - 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d550befadb..7216329237 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive

[PATCH v3 03/15] riscv: spike: Remove target macro conditionals

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- include/hw/riscv/spike.h | 6 -- hw/riscv/spike.c | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cddeca2e77..cdd1a13011 100644 --- a/include/hw/r

[PATCH v3 04/15] riscv: virt: Remove target macro conditionals

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/hw/riscv/virt.h | 6 -- hw/riscv/virt.c | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b4ed9a32eb..84b7a3848f 100644 -

[PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 9 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9c064f3094..6339e84819 100644 --- a/target/riscv/cpu.h +++ b/t

[PATCH v3 15/15] target/riscv: cpu: Set XLEN independently from target

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- target/riscv/cpu.c | 25 - 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 47b738c314..254cd83f8b 100644 --- a/target/riscv/cpu.c ++

[PATCH v3 07/15] hw/riscv: spike: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c | 45 - 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 875f371f0f..3e47e4579d 100644 --- a/hw/riscv/spike.c +++ b/hw/r

[PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/hw/riscv/boot.h | 8 +++--- hw/riscv/boot.c | 55 ++--- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c| 3 ++- hw/riscv/virt.c | 2 +- 5 files

[PATCH v3 14/15] target/riscv: csr: Remove compile time XLEN checks

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 4 +- target/riscv/csr.c | 176 +--- 2 files changed, 92 insertions(+), 88 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 24b24c69c5..1337269ae8 100644 ---

[PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros

The helper functions defined in helper.h specify that the argument is of type target_long. Let's change the implementation to match the header definition. Signed-off-by: Alistair Francis --- target/riscv/fpu_helper.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --

[PATCH v3 06/15] hw/riscv: virt: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/virt.c | 32 +--- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f8c5509f13..915e9ae216 100644 --- a/hw/riscv/virt.c +++ b/

[PATCH v3 13/15] target/riscv: cpu_helper: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a2787b1d48..1fc9273cea 100644 --- a/target/riscv/cpu_helper.c

[PATCH v3 12/15] target/riscv: cpu: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6f032122..47b738c314 100644 --- a/target/riscv/cpu

Re: [PATCH 1/3] target/arm: add FEAT_TLBIOS support

On Mon, 14 Dec 2020 at 20:23, Rebecca Cran wrote: > > ARMv8.4 adds the mandatory FEAT_TLBIOS, which provides instructions > for TLB invalidation of entries in the Outer Shareable domain. > > Signed-off-by: Rebecca Cran > --- > target/arm/helper.c | 30 > 1 file changed, 30 i

Re: [PATCH] libvhost-user: add a link-static option

On Mon, Dec 14, 2020 at 9:07 PM Marc-André Lureau < marcandre.lur...@gmail.com> wrote: > > > On Mon, Dec 14, 2020 at 8:23 PM Paolo Bonzini wrote: > >> On 12/12/20 10:08, marcandre.lur...@redhat.com wrote: >> > From: Marc-André Lureau >> > >> > Fix linking vhost-user binaries with with ./configur

[PATCH v2 1/3] smbios: Rename SMBIOS_ENTRY_POINT_* enums

Rename the enums to match the naming style used by QAPI. This will allow us to more easily move the enum to the QAPI schema later. Based on portions of a patch submitted by Daniel P. Berrangé. Signed-off-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- First version of this code was s

[PATCH v2 0/3] pc: Support configuration of SMBIOS entry point type

This includes code previously submitted[1] by Daniel P. Berrangé to add a "smbios-ep" machine property on PC. SMBIOS 3.0 is necessary to support more than ~720 VCPUs, as a large number of VCPUs can easily hit the table size limit of SMBIOS 2.1 entry points. [1] https://lore.kernel.org/qemu-devel

Re: [PATCH 1/3] tests/acceptance: Bump avocado requirements to 83.0

On Fri, Dec 11, 2020 at 3:38 PM Wainer dos Santos Moschetta wrote: > > To use Avocado's testlogs plug-in on CI it is required to use > its 83.0 or greater version. > > Signed-off-by: Wainer dos Santos Moschetta > --- > tests/requirements.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-

[PATCH v2 2/3] hw/smbios: Use qapi for SmbiosEntryPointType

This prepares for exposing the SMBIOS entry point type as a machine property on x86. Based on a patch from Daniel P. Berrangé. Signed-off-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- First version of this code was submitted at: https://lore.kernel.org/qemu-devel/20200908165438.1008

[PATCH v2 3/3] hw/i386: expose a "smbios-ep" PC machine property

From: Daniel P. Berrangé The i440fx and Q35 machine types are both hardcoded to use the legacy SMBIOS 2.1 entry point. This is a sensible conservative choice because SeaBIOS only supports SMBIOS 2.1 EDK2, however, can also support SMBIOS 3.0 and QEMU already uses this on the ARM virt machine typ

Re: [PATCH 2/3] gitlab-ci: Refactor code that show logs of failed acceptances

On 12/11/20 3:38 PM, Wainer dos Santos Moschetta wrote: Replace the code (python) on after_script of the acceptance jobs that is currently used to show the logs of failed tests. Instead it is used the Avocado's testlogs plug-in which works likewise. Signed-off-by: Wainer dos Santos Moschetta

Re: [PATCH v4 00/43] Mirror map JIT memory for TCG

Patchew URL: https://patchew.org/QEMU/20201214140314.18544-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201214140314.18544-1-richard.hender...@linaro.org Subject: [PATCH v4 00/43] Mi

Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops

On Sat, Dec 12, 2020 at 11:00:03AM +0100, Claudio Fontana wrote: > On 12/11/20 9:02 PM, Eduardo Habkost wrote: > > On Fri, Dec 11, 2020 at 07:51:54PM +0100, Claudio Fontana wrote: > >> On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote: > >>> On 12/11/20 7:22 PM, Richard Henderson wrote: > On 1

Re: [PATCH] libvhost-user: add a link-static option

Il lun 14 dic 2020, 21:48 Marc-André Lureau ha scritto: > Adding: > meson.override_dependency('glib-2.0', dependency('glib-2.0', static: > enable_static)) > > just before the "vhost_user = not_found..." works. Is that what you had in > mind? > Why not "meson.override_dependency('glib-2.0', glib

Re: [PATCH v12 00/23] i386 cleanup PART 1

On Sat, Dec 12, 2020 at 04:55:07PM +0100, Claudio Fontana wrote: [...] > Claudio Fontana (14): > i386: move kvm accel files into kvm/ > i386: move whpx accel files into whpx/ > i386: move hax accel files into hax/ > i386: hvf: remove stale MAINTAINERS entry for old hvf stubs > i386: move

Re: [PATCH v4 01/43] tcg: Do not flush icache for interpreter

On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson wrote: > > This is currently a no-op within tci/tcg-target.h, but > is about to be moved to a more generic location. > > Signed-off-by: Richard Henderson Reviewed-by: Joelle van Dyne

[PATCH] MAINTAINERS: Update my git repository URLs

I'm moving my git repositories to gitlab.com, update MAINTAINERS to point to the correct URL. Signed-off-by: Eduardo Habkost --- MAINTAINERS | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4663c143c3..6714257cf7 100644 --- a/MAINTAINERS +

Re: [for-6.0 v5 01/13] qom: Allow optional sugar props

On Fri, Dec 04, 2020 at 04:44:03PM +1100, David Gibson wrote: > From: Greg Kurz > > Global properties have an @optional field, which allows to apply a given > property to a given type even if one of its subclasses doesn't support > it. This is especially used in the compat code when dealing with

RE: [PATCH v5 0/4] hw/block/m25p80: Numonyx: Fix dummy cycles and check for SPI mode on cmds

Hi Peter, This series has been reviewed, but it looks like it slipped through the cracks. Is it possible it could be merged through your tree, assuming it looks good? Thanks! Joe -Original Message- From: Qemu-devel On Behalf Of Joe Komlodi Sent: Monday, November 16, 2020 3:11 PM To: qe

Re: [PATCH v12 16/23] cpu: Move synchronize_from_tb() to tcg_ops

Hi Claudio, Eduardo. On 12/14/20 8:10 PM, Eduardo Habkost wrote: > On Sat, Dec 12, 2020 at 04:55:23PM +0100, Claudio Fontana wrote: >> From: Eduardo Habkost >> >> since tcg_cpu_ops.h is only included in cpu.h, >> and as a standalone header it is not really useful, >> as tcg_cpu_ops.h starts requi

Re: [PATCH v4 02/43] util: Extract flush_icache_range to cacheflush.c

On 12/14/20 3:02 PM, Richard Henderson wrote: > This has been a tcg-specific function, but is also in use > by hardware accelerators via physmem.c. This can cause > link errors when tcg is disabled. > > Signed-off-by: Richard Henderson > --- > include/qemu/cacheflush.h | 24 + > tcg

Re: [PATCH v4 05/43] tcg: Move tcg prologue pointer out of TCGContext

On 12/14/20 3:02 PM, Richard Henderson wrote: > This value is constant across all thread-local copies of TCGContext, > so we might as well move it out of thread-local storage. > > Use the correct function pointer type, and name the variable > tcg_qemu_tb_exec, which means that we are able to remov

Re: [PATCH v4 07/43] tcg: Add in_code_gen_buffer

On 12/14/20 3:02 PM, Richard Henderson wrote: > Create a function to determine if a pointer is within the buffer. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg.h | 6 ++ > accel/tcg/translate-all.c | 26 -- > 2 files changed, 14 insertions(+),

Re: [PATCH v4 24/43] disas: Push const down through host disasassembly

Typo "disassembly" in subject? On 12/14/20 3:02 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > include/disas/dis-asm.h | 4 ++-- > disas.c | 4 +--- > disas/capstone.c| 2 +- > 3 files changed, 4 insertions(+), 6 deletions(-) Reviewed-by: Philipp

[PATCH v3 0/4] target/s390x: Improve carry computation

While testing the float128_muladd changes for s390x host, emulating under x86_64 of course, I noticed that the code we generate for strings of ALCGR and SLBGR is pretty awful. I realized that we were missing a trick: the output cc is based only on the output (result and carry) and so we don't need

[PATCH v3 2/4] target/s390x: Improve ADD LOGICAL WITH CARRY

Now that ADD LOGICAL outputs carry, we can use that as input directly. It also means we can re-use CC_OP_ADDU and produce an output carry directly from ADD LOGICAL WITH CARRY. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h| 2 -- target/s390x/cc

Re: [PATCH v4 14/43] tcg: Make DisasContextBase.tb const

On 12/14/20 3:02 PM, Richard Henderson wrote: > There is nothing within the translators that ought to be > changing the TranslationBlock data, so make it const. > > This does not actually use the read-only copy of the > data structure that exists within the rx region. > > Signed-off-by: Richard H

[PATCH v3 1/4] target/s390x: Improve cc computation for ADD LOGICAL

The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs).

Re: [PATCH v4 10/43] tcg: Adjust tcg_out_call for const

On 12/14/20 3:02 PM, Richard Henderson wrote: > We must change all targets at once, since all must match > the declaration in tcg.c. > > Signed-off-by: Richard Henderson > --- > tcg/tcg.c| 2 +- > tcg/aarch64/tcg-target.c.inc | 2 +- > tcg/arm/tcg-target.c.inc | 2 +- > t

[PATCH v3 3/4] target/s390x: Improve cc computation for SUBTRACT LOGICAL

The resulting cc is only dependent on the result and the carry-out. Carry-out and borrow-out are inverses, so are trivially converted. With tcg ops, it is easier to compute borrow-out than carry-out, so save result and borrow-out rather than the inputs. Borrow-out for 64-bit inputs is had via tcg_

[PATCH v3 4/4] target/s390x: Improve SUB LOGICAL WITH BORROW

Now that SUB LOGICAL outputs borrow, we can use that as input directly. It also means we can re-use CC_OP_SUBU and produce an output borrow directly from SUB LOGICAL WITH BORROW. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h| 2 - target/s390x/

Re: [PATCH v4 15/43] tcg: Make tb arg to synchronize_from_tb const

On 12/14/20 3:02 PM, Richard Henderson wrote: > There is nothing within the translators that ought to be > changing the TranslationBlock data, so make it const. > > This does not actually use the read-only copy of the > data structure that exists within the rx region. > > Signed-off-by: Richard H

Re: [PATCH v4 11/43] tcg: Adjust tcg_out_label for const

On 12/14/20 3:02 PM, Richard Henderson wrote: > Simplify the arguments to always use s->code_ptr instead of > take it as an argument. That makes it easy to ensure that > the value_ptr is always the rx version. > > Signed-off-by: Richard Henderson > --- > tcg/tcg.c | 6 +++--- >

[PATCH v1 0/1] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

From: "Edgar E. Iglesias" Hi, Found this while debugging an issue with lockups during boot of Linux on Xen. In the particular setup, I'm running without EL3 firmware so group0 interrupts are disabled on the physical interface and enabled on the virtual interface. Looks like we're checking the

Re: [PATCH v12 16/23] cpu: Move synchronize_from_tb() to tcg_ops

On Mon, Dec 14, 2020 at 10:56:13PM +0100, Philippe Mathieu-Daudé wrote: > Hi Claudio, Eduardo. > > On 12/14/20 8:10 PM, Eduardo Habkost wrote: > > On Sat, Dec 12, 2020 at 04:55:23PM +0100, Claudio Fontana wrote: > >> From: Eduardo Habkost > >> > >> since tcg_cpu_ops.h is only included in cpu.h, >

[PATCH v1 1/1] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

From: "Edgar E. Iglesias" Correct the indexing into s->cpu_ctlr for vCPUs. Signed-off-by: Edgar E. Iglesias --- hw/intc/arm_gic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index c60dc6b5e6..af41e2fb44 100644 --- a/hw/intc/arm_g

Re: [PATCH v1 1/1] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

On 12/14/20 11:21 PM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Correct the indexing into s->cpu_ctlr for vCPUs. > Fixes: cbe1282b568 ("intc/arm_gic: Implement gic_update_virt() function") LGTM but better double-check with GIC specialist ;) Reviewed-by: Philippe Mathieu-Daudé

[PATCH 1/3] [DO-NOT-MERGE] docs: replace single backtick (`) with double-backtick (``)

The single backtick in ReST is the "default role". Currently, Sphinx's default role is called "content". Sphinx suggests you can use the "Any" role instead to turn any single-backtick enclosed item into a cross-reference. Before we do that, though, we'll need to turn all existing usages of the "co

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