On Mon, 14 Dec 2020 at 20:23, Rebecca Cran <rebe...@nuviainc.com> wrote:
>
> ARMv8.4 adds the mandatory FEAT_TLBIOS, which provides instructions
> for TLB invalidation of entries in the Outer Shareable domain.
>
> Signed-off-by: Rebecca Cran <rebe...@nuviainc.com>
> ---
> target/arm/helper.c | 30 ++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 7b8bcd69030f..28556eb48b44 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4870,6 +4870,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
> .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
> .writefn = tlbi_aa64_vmalle1is_write },
> + { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
> + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
> + .writefn = tlbi_aa64_vmalle1is_write },
I think you need to arrange for these new TLBI operations
to only be registered when the CPU has the FEAT_TLBIOS.
Otherwise they won't UNDEF on older CPUs as they ought to.
That means they go in their own reginfo[] (you might need more
than one, haven't checked) that gets used only if a cpu_isar_feature
check passes; compare handling of eg the PAUTH regs:
if (cpu_isar_feature(aa64_pauth, cpu)) {
define_arm_cp_regs(cpu, pauth_reginfo);
}
thanks
-- PMM
