On 03/09/2020 09.08, 罗勇刚(Yonggang Luo) wrote:
> I am also facing some problem alike:
>
> LINK tests/test-qdev-global-props.exe
> LINK tests/test-timed-average.exe
> C:/CI-Tools/msys64/mingw64/bin/../lib/gcc/x86_64-w64-mingw32/10.2.0/../../../../x86_64-w64-mingw32/bin/ld.exe:
> libqemuuti
Michael Tokarev 于2020年9月3日周四 下午1:12写道：
>
> 02.09.2020 19:22, Li Qiang wrote:
> ..
> > @@ -809,6 +809,10 @@ void virtio_gpu_process_cmdq(VirtIOGPU *g)
> > {
> > struct virtio_gpu_ctrl_command *cmd;
> >
> > +if (atomic_read(&g->in_io)) {
> > +return;
> > +}
> > +atomic_set(
On 03/09/2020 00.42, Eduardo Habkost wrote:
> This will make the type name constant consistent with the name of
> the type checking macro.
>
> Signed-off-by: Eduardo Habkost
> ---
> Cc: Christian Borntraeger
> Cc: Tony Krowiak
> Cc: Halil Pasic
> Cc: Pierre Morel
> Cc: Richard Henderson
> Cc
On 03/09/20 12:22, Thomas Huth wrote:
>> Since you didn't remove that conditional, I assume that nothing
>> built in a "if not have_block" scenario was relying on the existing
>> stub ?
Technically there would be a user:
scripts/tracetool/backend/log.py
-> (qemu_get_thread_id) util/oslib-win32.
On 03/09/20 11:49, FelixCuioc wrote:
> Flatview_simplify() will merge many address ranges
> into one range.When a part of the big range needs
> to be changed,this will cause some innocent mappings
> to be unmapped.So we want to skip flatview_simplify().
>
> Signed-off-by: FelixCuioc
This has sev
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.
Signed-off-by: Bin Meng
---
include/hw/{riscv => misc}/sifive_u_prci.h | 0
include/hw/ri
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Peripheral models for a specific SoC are moved to its
corresponding hw/* subdirectories.
This series should be applied after the PolarFire SoC se
On 02.09.20 20:02, John Snow wrote:
> (CC Max for block backend model confusion, see below)
>
> On 8/16/20 11:38 PM, zhaoxin\RockCuioc wrote:
>> This patch is for avoiding win7 IDE driver polling 0x1f7 when
>> no any device attached. During Win7 VM boot procedure, if use virtio for
>> disk and the
From: Bin Meng
Every RISC-V machine needs riscv_hart hence there is no need to
have a dedicated Kconfig option for it. Drop the Kconfig option
and always build riscv_hart.c.
Signed-off-by: Bin Meng
---
hw/riscv/Kconfig | 9 -
hw/riscv/meson.build | 2 +-
2 files changed, 1 inserti
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.
Signed-off-by: Bin Meng
---
include/hw/{riscv => misc}/sifive_e_prci.h | 0
hw/{riscv =>
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.
Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supp
From: Bin Meng
At present the Kconfig file is in disorder. Let's sort the options.
Signed-off-by: Bin Meng
---
hw/riscv/Kconfig | 58
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
i
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng
---
include/hw/{riscv => misc}/sifive_u_otp.h | 0
include/hw/risc
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng
---
{include/hw/riscv => hw/intc}/sifive_plic.h | 0
hw/{riscv => i
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng
---
include/hw/{riscv => intc}/sifive_clint.h | 0
hw/{riscv => in
On 03/09/2020 00.15, 罗勇刚(Yonggang Luo) wrote:
> Seems signal handling are common and process fork are common in qemu,
> I suggest wrapping those in utils library for easily and consistence
> access across different platforms(Win32/POSIX)
For fork()-related things, I guess we could use the function
Daniel P. Berrangé writes:
> On Thu, Sep 03, 2020 at 12:17:29PM +0200, Kevin Wolf wrote:
>> Am 03.09.2020 um 11:48 hat Markus Armbruster geschrieben:
>> > If having to map from drive ID to node-name really is too much of a
>> > burden, we can look for ways to make it easier, or we can make savem
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.
Signed-off-by: Bin Meng
---
include/hw/{riscv => misc}/sifive_test.h | 0
hw/{riscv => misc
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.
Signed-off-by: Bin Meng
---
include/hw/{riscv => char}/riscv_htif.h | 0
hw/{riscv => char}/
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng
---
include/hw/{riscv => char}/sifive_uart.h | 0
hw/{riscv => char
On Thu, Sep 03, 2020 at 10:52:40AM +0200, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > Currently code has to call monitor_fdset_get_fd, then dup
> > the return fd, and then add the duplicate FD back into the
> > fdset. This dance is overly verbose for the caller and
> > introduces
Markus Armbruster writes:
> Markus Armbruster writes:
>
>> I let this series slide to get my Error API rework done, along with much
>> else. My sincere apologies!
>>
>> Unsurprisingly, it needs a rebase now. I suggest to let me review it as
>> is first.
>
> I'm done with v6. Summary:
>
> * A
From: Bin Meng
The name SIFIVE is too vague to convey the required component of
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
each machine instead.
Signed-off-by: Bin Meng
---
hw/riscv/Kconfig | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git
On Thu, 3 Sep 2020 at 06:47, Gerd Hoffmann wrote:
>
> Hi,
>
> > Darn. I've added Gerd's patch since it is needed to fix the acceptance
> > tests in the Gitlab-CI. Could we maybe revert the patch that introduced
> > the regression instead, as long as no other proper fix is available? The
> > fail
On Thu, Sep 3, 2020 at 6:42 PM Thomas Huth wrote:
> On 03/09/2020 00.15, 罗勇刚(Yonggang Luo) wrote:
> > Seems signal handling are common and process fork are common in qemu,
> > I suggest wrapping those in utils library for easily and consistence
> > access across different platforms(Win32/POSIX)
>
On 03/09/2020 12.48, Peter Maydell wrote:
> On Thu, 3 Sep 2020 at 06:47, Gerd Hoffmann wrote:
>>
>> Hi,
>>
>>> Darn. I've added Gerd's patch since it is needed to fix the acceptance
>>> tests in the Gitlab-CI. Could we maybe revert the patch that introduced
>>> the regression instead, as long as
On Thu, 3 Sep 2020 at 04:55, Jason Wang wrote:
> I think we still need to seek a way to address this issue completely.
>
> How about adding a flag in MemoryRegionOps and detect the reentrancy
> through that flag?
This won't catch everything. Consider this situation:
Device A makes DMA access to
On Thu, Sep 03, 2020 at 11:03:52AM +0200, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > Instead of relying on the limited information from errno, we can now
> > also provide detailed error messages to callers that ask for it.
> >
> > Signed-off-by: Daniel P. Berrangé
> > ---
> > u
The new interface starts unused, will start being used by the
next patches.
It provides methods for each accelerator to start a vcpu, kick a vcpu,
synchronize state, get cpu virtual clock and elapsed ticks.
In qemu_wait_io_event, make it clear that APC is used only for HAX
on Windows.
Signed-off
Motivation and higher level steps:
https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg04628.html
Current state is all reviewed, I think this is a good base to
include at this point.
I had to fix one build issue in patch 1 that went undetected previously due to
a meson thing (parallel build)
On Thu, 3 Sep 2020 at 11:42, Bin Meng wrote:
>
> From: Bin Meng
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Peripheral models for a specific SoC are moved to its
> corresponding hw/* subdirectories
register a "CpusAccel" interface for qtest as well.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
MAINTAINERS | 2 +-
accel/meson.build | 2 +-
accel/qtest/meson.build | 7 +++
accel/qtest/qtest-cpus.c | 91 +++
TCG is the first accelerator to register a "CpusAccel" interface
on initialization, providing functions for starting a vcpu,
kicking a vcpu, sychronizing state and getting virtual clock
and ticks.
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daud
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
accel/tcg/cpu-exec.c| 6 +++---
docs/replay.txt | 6 +++---
include/sysemu/cpu-timers.h | 16 +++---
include/sysemu/replay.h | 4 ++--
replay/replay.c | 2 +
refactoring of cpus.c continues with cpu timer state extraction.
cpu-timers: responsible for the softmmu cpu timers state,
including cpu clocks and ticks.
icount: counts the TCG instructions executed. As such it is specific to
the TCG accelerator. Therefore, it is built only under CON
register a "CpusAccel" interface for WHPX as well.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
MAINTAINERS | 1 +
softmmu/cpus.c | 79 -
target/i386/meson.build | 5 ++-
target/i386/whpx-all.c | 3 ++
target/i386/whp
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
softmmu/cpus.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/softmmu/cpus.c b/softmmu/cpus.c
index 2420a447eb..3d8350fba9 100644
--- a/softmmu/cpus.c
+++ b/softmmu/cpus.c
@@ -29,20 +29,13 @@
register a "CpusAccel" interface for HAX as well.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
softmmu/cpus.c| 80 +---
target/i386/hax-all.c | 6 ++-
target/i386/hax-cpus.c| 85 +++
ta
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Roman Bolshakov
---
accel/stubs/hvf-stub.c | 30 --
accel/stubs/meson.build| 1 -
include/sysemu/hvf.h | 8
target/i386/hvf/hvf-cpus.h | 8
target/i386/hvf/x
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
accel/kvm/kvm-cpus.h | 7 +++
accel/stubs/kvm-stub.c | 22 --
include/sysemu/kvm.h | 7 ---
3 files changed, 7 insertions(+), 29 deletions(-)
diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpu
register a "CpusAccel" interface for KVM as well.
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[added const]
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
accel/kvm/kvm-all.c| 14 ++-
accel/kvm/kvm-cpus.c |
kvm: uses the generic handler
qtest: uses the generic handler
whpx: changed to use the generic handler (identical implementation)
hax: changed to use the generic handler (identical implementation)
hvf: changed to use the generic handler (identical implementation)
tcg: adapt tcg-cpus to point to the
now that all accelerators support the CpusAccel interface,
we can remove most checks for non-NULL cpus_accel,
we just add a sanity check/assert at vcpu creation.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
softmmu/cpus.c | 33 +
1 file chang
register a "CpusAccel" interface for HVF as well.
Signed-off-by: Claudio Fontana
Reviewed-by: Roman Bolshakov
[added const]
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
softmmu/cpus.c | 66 --
target/i386/hvf/hvf-cpus.c | 131 +++
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
accel/stubs/meson.build | 1 -
accel/stubs/whpx-stub.c | 47 -
include/sysemu/whpx.h | 19 -
target/i386/whpx-cpus.h | 17 +++
4 files changed, 17 insertions(+
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
accel/stubs/hax-stub.c| 10 --
include/sysemu/hax.h | 17 -
target/i386/hax-all.c | 1 -
target/i386/hax-cpus.c| 1 -
target/i386/hax-cpus.h| 16
target/i386/hax-mem.
On Donnerstag, 3. September 2020 11:35:14 CEST Greg Kurz wrote:
> > On the long term that would be possible, however only with a protocol
> > change allowing server to send minimum, maximum and recommended msize to
> > client.
> Hmm... not sure adding a new 9P protocol version for this is the
> way
+-- On Mon, 31 Aug 2020, Philippe Mathieu-Daudé wrote --+
| > +++ b/hw/ide/core.c
| > @@ -718,7 +718,7 @@ void ide_cancel_dma_sync(IDEState *s)
| > -if (s->bus->dma->aiocb) {
| > +if (s->blk && s->bus->dma->aiocb) {
|
| But s->blk mustn't be null here... IMHO we should assert() here and ad
On 03.09.20 12:13, Fabian Grünbichler wrote:
> On August 21, 2020 3:03 pm, Max Reitz wrote:
>> On 18.02.20 11:07, Fabian Grünbichler wrote:
>>
>> [Sorry :/]
>
> same, I've been meaning to ping/pick this back up but other stuff got in
> the way. so thanks for the reminder to get this upstream ;)
>
Hi Eugenio,
On 9/3/20 12:13 PM, Eugenio Perez Martin wrote:
> Hi Eric,
>
> On Wed, Sep 2, 2020 at 12:32 PM Auger Eric wrote:
>>
>> Hi Eugenio,
>>
>> On 9/1/20 4:26 PM, Eugenio Pérez wrote:
>>> Adapt intel and vhost to use this new notification type
>> I think you should explain in the commit mess
Hi,
I'm not suppose to work on this but I couldn't sleep so kept
wondering about this problem the whole night and eventually
woke up to write this quickly, so comments are scarce, sorry.
The first part is obvious anyway, simply pass MemTxAttrs argument.
The main patch is:
"exec/memattrs: Introdu
From: Klaus Jensen
Some might actually care about the return value of dma_memory_rw. So
let us pass it along instead of ignoring it.
There are no existing users of the return value, so this patch should be
safe.
Signed-off-by: Klaus Jensen
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Mich
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/dma.h | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index 34f957cc278..6068323e48f 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -82,23 +82,2
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ppc/spapr_vio.h | 2 +-
include/sysemu/dma.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h
index bed7df60e35..f134f6cf574 100644
--- a/include/hw/ppc/spapr
Add the 'direct_access' bit to the memory attributes to restrict
bus master access to ROM/RAM.
Have read/write accessors return MEMTX_BUS_ERROR if an access is
restricted and the region is not ROM/RAM ('direct').
Add corresponding trace events.
Signed-off-by: Philippe Mathieu-Daudé
---
include/e
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 3 ++-
include/sysemu/dma.h | 10 +-
dma-helpers.c| 3 ++-
hw/intc/spapr_xive.c | 3 ++-
hw/usb/hcd-ohci.c| 10 ++
5 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/include/hw/pci/pci.h
Patch created mechanically using spatch with this script:
@@
expression E1, E2, E3, E4;
@@
(
- dma_memory_read(E1, E2, E3, E4)
+ dma_memory_read(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED)
|
- dma_memory_write(E1, E2, E3, E4)
+ dma_memory_write(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED)
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ppc/spapr_vio.h | 3 ++-
include/sysemu/dma.h | 3 ++-
dma-helpers.c | 6 +++---
hw/nvram/fw_cfg.c | 3 ++-
4 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/s
Patch created mechanically using spatch with this script:
@@
expression E1, E2, E3, E4;
@@
- dma_memory_map(E1, E2, E3, E4)
+ dma_memory_map(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED)
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h| 3 ++-
include/sysemu/dma.h| 4 +
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/loads-stores.rst | 2 ++
1 file changed, 2 insertions(+)
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
index 9a944ef1af6..5b20f907e4d 100644
--- a/docs/devel/loads-stores.rst
+++ b/docs/devel/loads-stores.rst
@@ -477,6
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 6 --
include/hw/ppc/spapr_vio.h | 15 ++-
include/sysemu/dma.h | 20
hw/intc/pnv_xive.c | 7 ---
hw/nvram/fw_cfg.c | 4 ++--
5 files changed, 32 insertions(+)
Assert DMA accesses are done on direct memory (in particular
to catch invalid accesses to MMIO regions).
Example with the reproducer from LP#1886362 (see previous commit):
qemu-system-i386: include/sysemu/dma.h:111: int dma_memory_rw(AddressSpace *,
dma_addr_t, void *, dma_addr_t, DMADirection
Hi all!
I can trigger long io request with help of nbd reconnect-delay option, which
make the request wait for some time for the connection to establish again and
retry (of course, this works if connection is already lost). So, the request
itself may be long. And this triggers the deadlock, wh
On 9/2/20 10:46 PM, David Gibson wrote:
On Tue, Sep 01, 2020 at 09:56:45AM -0300, Daniel Henrique Barboza wrote:
home_node_associativity reply now uses the associativity
values for tcpu->node_id provided by numa_assoc_array.
This will avoid further changes in this code when numa_assoc_array
Do not allow PCI slaves to write to indirect memory
regions such MMIO.
This fixes LP#1886362 and LP#1888606.
Example with the former reproducer:
$ cat << EOF | \
qemu-system-i386 -M q35,accel=qtest \
-qtest stdio \
-trace memory_access\* \
outl 0
Peter Maydell 于2020年9月3日周四 下午6:53写道：
>
> On Thu, 3 Sep 2020 at 04:55, Jason Wang wrote:
> > I think we still need to seek a way to address this issue completely.
> >
> > How about adding a flag in MemoryRegionOps and detect the reentrancy
> > through that flag?
>
> This won't catch everything. Co
On Thu, 3 Sep 2020 at 12:11, Li Qiang wrote:
>
> Peter Maydell 于2020年9月3日周四 下午6:53写道：
> >
> > On Thu, 3 Sep 2020 at 04:55, Jason Wang wrote:
> > > I think we still need to seek a way to address this issue completely.
> > >
> > > How about adding a flag in MemoryRegionOps and detect the reentranc
Mention a few of the more common naming conventions we follow in the
code base including common variable names and function prefix and
suffix examples.
Signed-off-by: Alex Bennée
---
v2
- punctuation fixes suggested by Cornelia
- re-worded section on qemu_ prefix
- expanded on _locked suff
Hi,
My first series after a holiday is a bunch of clean-ups for testing.
Currently they all apply on top of Thomas' pull-request-2020-09-02 tag
which is currently in flight. The fixes to shippable won't become
apparent until the main registry has been updates with the new images
but I have tested
One of the Travis builds was complaining about:
qemu/include/tcg/tcg.h:437:12: error: ‘cond’ may be used uninitialized in
this function [-Werror=maybe-uninitialized]
return (TCGCond)(c ^ 1);
../target/mips/translate.c:20031:13: note: ‘cond’ was declared here
TCGCond cond;
Rathe
From: Daniel P. Berrangé
If nettle is disabled and gcrypt enabled, the compiler and linker flags
needed for gcrypt are not passed.
Gnutls was also not added as a dependancy when gcrypt is enabled.
Attempting to add the library dependencies at the same time as the
source dependencies is error pr
We need these now for builds to work.
Signed-off-by: Alex Bennée
---
tests/docker/dockerfiles/debian10.docker | 1 +
tests/docker/dockerfiles/debian9.docker | 1 +
2 files changed, 2 insertions(+)
diff --git a/tests/docker/dockerfiles/debian10.docker
b/tests/docker/dockerfiles/debian10.docker
On 9/2/20 10:34 PM, David Gibson wrote:
On Tue, Sep 01, 2020 at 09:56:43AM -0300, Daniel Henrique Barboza wrote:
In a similar fashion as the previous patch, let's move the
handling of ibm,associativity-lookup-arrays from spapr.c to
spapr_numa.c. A spapr_numa_write_assoc_lookup_arrays() helper
Peter Maydell 于2020年9月3日周四 下午7:19写道：
>
> On Thu, 3 Sep 2020 at 12:11, Li Qiang wrote:
> >
> > Peter Maydell 于2020年9月3日周四 下午6:53写道：
> > >
> > > On Thu, 3 Sep 2020 at 04:55, Jason Wang wrote:
> > > > I think we still need to seek a way to address this issue completely.
> > > >
> > > > How about a
The gcov build triggered:
../../migration/global_state.c:47:5: error: ‘strncpy’ specified
bound 100 equals destination size [-Werror=stringop-truncation]
strncpy((char *)global_state.runstate
As we shouldn't be using strncpy anyway lets use the suggested
pstrcpy.
Signed-off-by: Ale
From: Gerd Hoffmann
Fixes build failures with old kernels (USBDEVFS_GET_SPEED missing),
on the assumtion that distros with old kernels also have old libusb.
Reported-by: Alex Bennée
Signed-off-by: Gerd Hoffmann
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Message-Id: <20200
These patches also enable the make check by ignore the
tests errors, so the CI can be passed.
Yonggang Luo (2):
tests: try to disable make check blocker for msys2
ci: Enable msys2 ci in cirrus
.cirrus.yml | 24 +
scripts/ci/windows/msys2_build.sh
From: Paolo Bonzini
check-block has its own test harness, unlike every other test. If
we capture its output, as is in general nicer to do without V=1,
there will be no sign of progress. So for lack of a better option
just move the invocation of the test back to Makefile rules.
As a side effect
As the tests build only softfloat.c no actual TCG machinary is neede
to test them (as is evidenced by GCC check-softfloat). Might as well
fix the wording on Travis while at it.
Signed-off-by: Alex Bennée
---
.travis.yml | 2 +-
tests/meson.build | 3 ++-
2 files changed, 3 insertions(+), 2
tests/test-char are stuck forever on msys2, disable it first
Signed-off-by: Yonggang Luo
---
tests/Makefile.include | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 497f1f21ff..c645e8972a 100644
--- a/tests/Makefile.include
+++ b/tests/M
On Thu, 3 Sep 2020 at 12:24, Li Qiang wrote:
> Peter Maydell 于2020年9月3日周四 下午7:19写道：
> > No. Any device can have an inbound or outbound qemu_irq line.
> > We use them not just for actual IRQ lines but for any
> > situation where we need to pass an on-or-off signal from
> > one device to another.
>
Install msys2 in a proper way refer to
https://github.com/cirruslabs/cirrus-ci-docs/issues/699
The https://wiki.qemu.org/Hosts/W32#Native_builds_with_MSYS2 need to be updated.
There is no need of --cross-prefix, open mingw64.exe instead of msys2.exe then
we don't
need the --cross-prefix, besides
On 9/2/20 10:51 PM, David Gibson wrote:
On Tue, Sep 01, 2020 at 09:56:41AM -0300, Daniel Henrique Barboza wrote:
The next step to centralize all NUMA/associativity handling in
the spapr machine is to create a 'one stop place' for all
things ibm,associativity.
This patch introduces numa_assoc
On Thu, Sep 03, 2020 at 12:20:59PM +0100, Alex Bennée wrote:
> Hi,
>
> My first series after a holiday is a bunch of clean-ups for testing.
> Currently they all apply on top of Thomas' pull-request-2020-09-02 tag
> which is currently in flight. The fixes to shippable won't become
> apparent until
On 03/09/2020 00.42, Eduardo Habkost wrote:
> This will make the type name constant consistent with the name of
> the type checking macro.
>
> Signed-off-by: Eduardo Habkost
> ---
> Cc: Cornelia Huck
> Cc: Thomas Huth
> Cc: Christian Borntraeger
> Cc: Tony Krowiak
> Cc: Halil Pasic
> Cc: Pie
On 03/09/2020 13.21, Alex Bennée wrote:
> We need these now for builds to work.
>
> Signed-off-by: Alex Bennée
> ---
> tests/docker/dockerfiles/debian10.docker | 1 +
> tests/docker/dockerfiles/debian9.docker | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/tests/docker/dockerfiles/d
Signed-off-by: Yonggang Luo
---
tests/docker/dockerfiles/msys2.docker | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 tests/docker/dockerfiles/msys2.docker
diff --git a/tests/docker/dockerfiles/msys2.docker
b/tests/docker/dockerfiles/msys2.docker
new file mode 100644
inde
dubo...@gmail.com writes:
> From: Josh DuBois
>
> Tracing can be enabled at the command line or via the
> monitor. Command-line trace options are recorded during
> trace_opt_parse(), but tracing is not enabled until the various
> front-ends later call trace_init_file(). If the user passes a trace
Il gio 3 set 2020, 13:24 FelixCui-oc ha scritto:
> >I think you're seeing issues when a guest accesses an adjacent mapping
> between the delete and add phases of the KVM MemoryListener.
>
> >We're considering fixing that in the kernel, by adding a new ioctl that
> changes the whole memory map in
Il gio 3 set 2020, 13:21 Alex Bennée ha scritto:
> As the tests build only softfloat.c no actual TCG machinary is neede
> to test them (as is evidenced by GCC check-softfloat). Might as well
> fix the wording on Travis while at it.
>
The reason is that softfloat is not built at all into QEMU if
Il gio 3 set 2020, 13:21 Alex Bennée ha scritto:
> The gcov build triggered:
>
> ../../migration/global_state.c:47:5: error: ‘strncpy’ specified
> bound 100 equals destination size [-Werror=stringop-truncation]
> strncpy((char *)global_state.runstate
>
> As we shouldn't be using str
On Thu, Sep 3, 2020 at 1:06 PM Auger Eric wrote:
>
> Hi Eugenio,
> On 9/3/20 12:13 PM, Eugenio Perez Martin wrote:
> > Hi Eric,
> >
> > On Wed, Sep 2, 2020 at 12:32 PM Auger Eric wrote:
> >>
> >> Hi Eugenio,
> >>
> >> On 9/1/20 4:26 PM, Eugenio Pérez wrote:
> >>> Adapt intel and vhost to use this
Le 03/09/2020 à 00:42, Eduardo Habkost a écrit :
This will make the type name constant consistent with the name of
the type checking macro.
Signed-off-by: Eduardo Habkost
---
Cc: "Hervé Poussineau"
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
include/hw/isa/pc87312.h | 4 ++--
hw/i
Le 03/09/2020 à 00:42, Eduardo Habkost a écrit :
Make the type checking macro name consistent with the TYPE_*
constant.
Signed-off-by: Eduardo Habkost
---
Cc: "Hervé Poussineau"
Cc: David Gibson
Cc: qemu-...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/ppc/rs6000_mc.c | 4 ++--
1 file chang
Le 03/09/2020 à 00:42, Eduardo Habkost a écrit :
Make the type checking macro name consistent with the TYPE_*
constant.
Signed-off-by: Eduardo Habkost
---
Cc: Mark Cave-Ayland
Cc: Laurent Vivier
Cc: "Hervé Poussineau"
Cc: Aleksandar Rikalo
Cc: Aleksandar Markovic
Cc: Aurelien Jarno
Cc: Ji
On 03/09/20 13:21, Alex Bennée wrote:
> Mention a few of the more common naming conventions we follow in the
> code base including common variable names and function prefix and
> suffix examples.
>
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - punctuation fixes suggested by Cornelia
> - re-w
On 03/09/20 13:08, Philippe Mathieu-Daudé wrote:
> Do not allow PCI slaves to write to indirect memory
> regions such MMIO.
>
> This fixes LP#1886362 and LP#1888606.
What is a "PCI slave"? Which devices would still be allowed to write?
I'm worried that there are cases of MMIO reads that would b
On 03/09/2020 09.26, Richard Henderson wrote:
> Version 2 includes fixes for iflags that could cause lockups.
>
> It seems it was easier to do so with icount=7, which is what we do during
> the replay acceptance tests. This causes TBs to contain no more than 7
> insns, and often less to make up f
Hi Kevin,
You already queued v6, but 2 patches from Klaus modified
block/nvme.c so the series needed a rebase... Sorry for
the extra work :/
Since v6: rebased on top of:
- c26f2173704 ("hw/block/nvme: bump spec data structures to v1.3")
- 69265150aa5 ("hw/block/nvme: be consistent about zeros vs
Use self-explicit SCALE_MS definition instead of magic value.
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Stefano Garzarella
Signed-off-by: Philippe Mathieu-Daudé
---
block/nvme.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/nvme.c b/block/nvme.c
index 05485fdd118..a
101 - 200 of 629 matches
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