On 7/22/20 5:50 AM, Thiago Jung Bauermann wrote:
> Remove setting of cs->halted from cpu_devinit(), which seems out of place
> when compared to similar code in other architectures (e.g., ppce500_init()
> in hw/ppc/e500.c).
>
> Signed-off-by: Thiago Jung Bauermann
> ---
> hw/sparc/sun4m.c | 1 -
>
On 7/22/20 8:29 AM, Alex Bennée wrote:
> From: Laurent Vivier
>
> If clock_nanosleep() encounters an error, it returns one of the positive
> error number.
>
> If the call is interrupted by a signal handler, it fails with error EINTR
> and if "remain" is not NULL and "flags" is not TIMER_ABSTIME,
On 7/22/20 5:50 AM, Thiago Jung Bauermann wrote:
> Instead of setting CPUState::halted to 1 in s390_cpu_initfn(), use the
> start-powered-off property which makes cpu_common_reset() initialize it to
> 1 in common code.
>
> Signed-off-by: Thiago Jung Bauermann
> ---
> target/s390x/cpu.c | 3 ++-
>
On 7/22/20 5:50 AM, Thiago Jung Bauermann wrote:
> Instead of setting CPUState::halted to 1 in main_cpu_reset(), use the
> start-powered-off property which makes cpu_common_reset() initialize it
> to 1 in common code.
>
> Signed-off-by: Thiago Jung Bauermann
> ---
> hw/mips/cps.c | 6 +++---
> 1
On 7/22/20 5:50 AM, Thiago Jung Bauermann wrote:
> PowerPC sPAPR CPUs start in the halted state, and spapr_reset_vcpu()
> attempts to implement this by setting CPUState::halted to 1. But that's too
> late for the case of hotplugged CPUs in a machine configure with 2 or more
> threads per core.
>
>
Philippe Mathieu-Daudé writes:
> Since commit 73ac1aac39 qdev_prop_set_drive_err() returns
> a boolean value. Document it.
>
> Fixes: 73ac1aac39 "Make functions taking Error ** return bool, not void"
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/qdev-properties.h | 2 ++
> 1 file c
On 7/22/20 5:50 AM, Thiago Jung Bauermann wrote:
> If we rely on cpu_common_reset() setting CPUState::halted according to the
> start-powered-off property, both reset functions become equivalent and we
> can use only one.
>
> Signed-off-by: Thiago Jung Bauermann
> ---
> hw/sparc/sun4m.c | 21 +++
On 7/22/20 8:43 AM, Christian Borntraeger wrote:
>
>
> On 15.07.20 16:08, Janosch Frank wrote:
>> Normally they don't need to be set up before waiting for an interrupt
>> but are set up on boot. The BIOS however might overwrite the lowcore
>> (and hence the PSWs) when loading a blob into memory a
We have a tracepoint at the same place which can be enabled if needed.
Buglink: https://bugzilla.redhat.com//show_bug.cgi?id=1859236
Signed-off-by: Gerd Hoffmann
---
hw/usb/hcd-ehci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 1495e8f7fab1..426
On 7/22/20 8:50 AM, Christian Borntraeger wrote:
>
>
> On 15.07.20 11:40, Janosch Frank wrote:
>> The two main types of zipl component entries are execute and
>> load/data. The last member of the component entry struct therefore
>> denotes either a PSW or an address. Let's make this a bit more cl
On 22.07.20 09:30, Janosch Frank wrote:
> On 7/22/20 8:50 AM, Christian Borntraeger wrote:
>>
>>
>> On 15.07.20 11:40, Janosch Frank wrote:
>>> The two main types of zipl component entries are execute and
>>> load/data. The last member of the component entry struct therefore
>>> denotes either a
On 22.07.20 09:24, Janosch Frank wrote:
> On 7/22/20 8:43 AM, Christian Borntraeger wrote:
>>
>>
>> On 15.07.20 16:08, Janosch Frank wrote:
>>> Normally they don't need to be set up before waiting for an interrupt
>>> but are set up on boot. The BIOS however might overwrite the lowcore
>>> (and
@keith, please see below - can you comment on the Linux kernel 2 MB
boundary requirement for the CMB? Or should we hail Stephen (or Logan
maybe) since this seems to be related to p2pdma?
On Jul 21 14:54, Andrzej Jakowski wrote:
> On 7/15/20 1:06 AM, Klaus Jensen wrote:
> > Hi Andrzej,
> >
> > I'v
On 7/22/20 9:26 AM, Gerd Hoffmann wrote:
> We have a tracepoint at the same place which can be enabled if needed.
>
> Buglink: https://bugzilla.redhat.com//show_bug.cgi?id=1859236
> Signed-off-by: Gerd Hoffmann
> ---
> hw/usb/hcd-ehci.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw
On 7/21/20 9:57 PM, Guenter Roeck wrote:
> On 7/21/20 10:36 AM, Cédric Le Goater wrote:
>> Hello,
>>
>> On 2/6/20 7:32 PM, Guenter Roeck wrote:
>>> When requesting JEDEC data using the JEDEC_READ command, the Linux kernel
>>> always requests 6 bytes. The current implementation only returns three
>>
Hi Thomas,
> -Original Message-
> From: Thomas Huth
> Sent: Monday, July 20, 2020 1:37 PM
> To: Sai Pavan Boddu ; Philippe Mathieu-Daudé
> ; Markus Armbruster
> Cc: Gerd Hoffmann ; Peter Maydell
> ; Eduardo Habkost ;
> qemu-devel@nongnu.org; Alistair Francis ;
> 'Marc-André Lureau' ; Yin
On Tue, 21 Jul 2020 at 22:16, Gerd Hoffmann wrote:
> Speaking of testing: What is the state of gitlab ci? How much of the
> testing has been migrated over? I've noticed I can push branches and
> tags to a qemu fork @ gitlab.com and gitlab ci runs a bunch of tests.
I still need to look at Clebe
RFC v1: https://lists.nongnu.org/archive/html/qemu-block/2020-05/msg00912.html
RFC v2: https://lists.nongnu.org/archive/html/qemu-block/2020-05/msg00915.html
v1: https://lists.nongnu.org/archive/html/qemu-devel/2020-06/msg09792.html
v2: https://lists.nongnu.org/archive/html/qemu-block/2020-07/msg01
This migration parameter allows mapping block node names and bitmap
names to aliases for the purpose of block dirty bitmap migration.
This way, management tools can use different node and bitmap names on
the source and destination and pass the mapping of how bitmaps are to be
transferred to qemu (
Signed-off-by: Max Reitz
---
tests/qemu-iotests/iotests.py | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py
index 3590ed78a0..20645a6e7d 100644
--- a/tests/qemu-iotests/iotests.py
+++ b/tests/qemu-iotests/iotests.py
@@ -28,6 +2
On 7/22/20 9:33 AM, Christian Borntraeger wrote:
>
>
> On 22.07.20 09:30, Janosch Frank wrote:
>> On 7/22/20 8:50 AM, Christian Borntraeger wrote:
>>>
>>>
>>> On 15.07.20 11:40, Janosch Frank wrote:
The two main types of zipl component entries are execute and
load/data. The last member
Signed-off-by: Max Reitz
---
tests/qemu-iotests/300 | 515 +
tests/qemu-iotests/300.out | 5 +
tests/qemu-iotests/group | 1 +
3 files changed, 521 insertions(+)
create mode 100755 tests/qemu-iotests/300
create mode 100644 tests/qemu-iotests/300.out
On 2020-07-21 at 16:27 CEST, Gerd Hoffmann wrote...
> Hi,
>
>> > DeviceState *qdev_new(const char *name)
>> > {
>> > +if (!object_class_by_name(name)) {
>> > +module_load_qom_one(name);
>> > +}
>>
>> Curious why you don't you call module_object_class_by_name here?
>
> Because
On 2020-07-21 at 16:33 CEST, Gerd Hoffmann wrote...
>> > ifeq ($(CONFIG_USB_SMARTCARD),y)
>> > common-obj-y += dev-smartcard-reader.o
>>
>> I'm curious why you don't use something like:
>>
>> common-obj-$(CONFIG_USB_SMARTCARD)
>>
>> Do we want to be able to configure in
On 7/22/20 9:39 AM, Christian Borntraeger wrote:
>
>
> On 22.07.20 09:24, Janosch Frank wrote:
>> On 7/22/20 8:43 AM, Christian Borntraeger wrote:
>>>
>>>
>>> On 15.07.20 16:08, Janosch Frank wrote:
Normally they don't need to be set up before waiting for an interrupt
but are set up on
On 2020-06-24 at 15:10 CEST, Gerd Hoffmann wrote...
> Little helper function to load modules on demand. In most cases adding
> module loading support for devices and other objects is just
> s/object_class_by_name/module_object_class_by_name/ in the right spot.
>
> Signed-off-by: Gerd Hoffmann
>
Currently where is no way to make a vm snapshot without pausing a vm
for the whole time until the snapshot is done. So, the problem is
the vm downtime on snapshoting. The downtime value depends on the vmstate
size, the major part of which is RAM and the disk performance which is
used for the snapsh
Signed-off-by: Denis Plotnikov
---
migration/ram.c| 4
migration/trace-events | 2 ++
2 files changed, 6 insertions(+)
diff --git a/migration/ram.c b/migration/ram.c
index f187b5b494..29712a11c2 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -2172,12 +2172,16 @@ again:
1. test bit
2. test and set bit
Signed-off-by: Denis Plotnikov
Reviewed-by: Peter Xu
---
include/qemu/bitops.h | 25 +
1 file changed, 25 insertions(+)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index f55ce8b320..63218afa5a 100644
--- a/include/qemu/bito
The capability is used for background snapshot enabling.
The background snapshot logic is going to be added in the following
patch.
Signed-off-by: Denis Plotnikov
---
qapi/migration.json | 7 ++-
migration/migration.h | 1 +
migration/migration.c | 35 +++
By the moment, making a vm snapshot may cause a significant vm downtime,
depending on the vm RAM size and the performance of disk storing
the vm snapshot. This happens because the VM has to be paused until all
vmstate including RAM is written.
To reduce the downtime, the background snapshot capabi
Public bug reported:
Hello, Why the file sizes of http conversion and local conversion are
inconsistent?
Use the http method of qemu-img for conversion. The size of some formats after
conversion is different from the local method of qemu-img. Such as vhd, vdi.
qcow2 and vmdk are normal。
My imag
Xen accelerator requires specific changes to a machine to be able
to use it. See for example the 'Xen PC' machine configure its PCI
bus calling pc_xen_hvm_init_pci(). There is no 'Xen Q35' machine
declared. This code was probably added while introducing the Q35
machine, based on the existing PC mac
Currently edu device doesn't support live migration. Part of PCI
configuration information would be lost after migration.
PCI device state in source VM:
Bus 0, device 3, function 0:
Class 0255: PCI device 1234:11e8
PCI subsystem 1af4:1100
IRQ 11, pin A
BAR0: 32 bit memo
On 2020/7/22 下午1:49, Jason Wang wrote:
On 2020/7/22 下午12:47, Li Qiang wrote:
Jason Wang 于2020年7月22日周三 上午11:32写道：
On 2020/7/21 下午11:17, Li Qiang wrote:
Alexander Bulekov reported a UAF bug related e1000e packets send.
-->https://bugs.launchpad.net/qemu/+bug/1886362
This is because the gu
Le 22/07/2020 à 08:49, Laurent Vivier a écrit :
> Le 22/07/2020 à 08:29, Alex Bennée a écrit :
>> From: Laurent Vivier
>>
>> If clock_nanosleep() encounters an error, it returns one of the positive
>> error number.
>>
>> If the call is interrupted by a signal handler, it fails with error EINTR
>>
On Wed, 22 Jul 2020 at 09:31, Zeng Guang wrote:
>
> Currently edu device doesn't support live migration. Part of PCI
> configuration information would be lost after migration.
>
> PCI device state in source VM:
> Bus 0, device 3, function 0:
> Class 0255: PCI device 1234:11e8
> P
Hi,
On 22/07/2020 09.49, Sai Pavan Boddu wrote:
[...]
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2 of the
Signed-off-by: Markus Armbruster
---
scripts/coccinelle/err-bad-newline.cocci | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/scripts/coccinelle/err-bad-newline.cocci
b/scripts/coccinelle/err-bad-newline.cocci
index 1316cc86a6..5394421873 100644
---
Patch created mechanically by rerunning:
$ spatch --sp-file scripts/coccinelle/error_propagate_null.cocci \
--macro-file scripts/cocci-macro-file.h \
--use-gitgrep .
Cc: Jens Freimann
Cc: Hailiang Zhang
Cc: Juan Quintela
Signed-off-by: Markus Armbruster
---
hw/n
Markus Armbruster (4):
coccinelle/err-bad-newline: Fix for Python 3, and add patterns
error: Strip trailing '\n' from error string arguments (again)
error: Remove NULL checks on error_propagate() calls (again)
error: Use error_fatal to simplify obvious fatal errors (again)
scripts/coccine
Tracked down with scripts/coccinelle/err-bad-newline.cocci.
Cc: Peter Xu
Cc: David Gibson
Signed-off-by: Markus Armbruster
---
hw/i386/intel_iommu.c | 6 +++---
target/ppc/mmu-hash64.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/inte
Patch created mechanically by rerunning:
$ spatch --in-place --sp-file scripts/coccinelle/use-error_fatal.cocci \
--macro-file scripts/cocci-macro-file.h --use-gitgrep .
Variables now unused dropped manually.
Cc: Eric Auger
Cc: David Hildenbrand
Signed-off-by: Markus Armbruste
On 22.07.20 10:40, Markus Armbruster wrote:
> Patch created mechanically by rerunning:
>
> $ spatch --in-place --sp-file scripts/coccinelle/use-error_fatal.cocci \
>--macro-file scripts/cocci-macro-file.h --use-gitgrep .
>
> Variables now unused dropped manually.
>
> Cc: Eric Aug
Initialize spice before chardevs. That allows to register the spice
chardevs directly in the init function and removes the need to maintain
a linked list of chardevs just for registration.
Signed-off-by: Gerd Hoffmann
---
include/chardev/spice.h | 1 -
include/ui/qemu-spice.h | 1 -
chardev/s
Hi,
What exactly do you mean by “file size”? The file length (as reported
by ls -l) or the bytes used on disk (reported as “disk size” by qemu-
img, or by du -B1)?
You say that qcow2 and vmdk are normal – do you mean as input or as
output formats?
One thing that comes to my mind is that from ht
On 32-bit systems with 64-bit time_t, input_event.time is not
directly accessible. Instead, we must use input_event_sec and
input_event_usec accessors to set the time values.
Signed-off-by: Ariadne Conill
---
contrib/vhost-user-input/main.c | 5 -
1 file changed, 4 insertions(+), 1 deletion
On 32-bit systems with 64-bit time_t, input_event.time is not
directly accessible. Instead, we must use input_event_sec and
input_event_usec accessors to set the time values.
Signed-off-by: Ariadne Conill
---
hw/input/virtio-input-host.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
Laurent Vivier writes:
> Le 22/07/2020 à 08:29, Alex Bennée a écrit :
>> From: Laurent Vivier
>>
>> If clock_nanosleep() encounters an error, it returns one of the positive
>> error number.
>>
>> If the call is interrupted by a signal handler, it fails with error EINTR
>> and if "remain" is
The memory API allows DMA into NIC's MMIO area. This means the NIC's
RX routine must be reentrant. Instead of auditing all the NIC, we can
simply detect the reentrancy and return early. The queue->delivering
is set and cleared by qemu_net_queue_deliver() for other queue helpers
to know whether the
In loopback mode, e1000e RX can DMA into TX doorbell which requires
TX to be reentrant. This patch make e1000e's TX routine reentrant by
introducing a per device boolean for recording whether or not a TX
rountine is being called and return early.
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.
* Max Reitz (mre...@redhat.com) wrote:
> This migration parameter allows mapping block node names and bitmap
> names to aliases for the purpose of block dirty bitmap migration.
>
> This way, management tools can use different node and bitmap names on
> the source and destination and pass the mappi
On Tue, 21 Jul 2020 at 13:43, Zong Li wrote:
>
> The real physical address should add the 12 bits page offset. It also
> causes the PMP wrong checking due to the minimum granularity of PMP is
> 4 byte, but we always get the physical address which is 4KB alignment,
> that means, we always use the s
Hi all,
this locks up the guest:
- qemu-system-x86_64 -enable-kvm -cpu host
- trigger hard reset
Host kernel: 5.7.7.
Host CPU: i7-8850H
Jan
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux
On Wed, Jul 22, 2020 at 11:32:28AM +0800, Zhenyu Ye wrote:
> Currently migration_tls_get_creds() adds the reference of creds
> but there was no place to unref it. So the OBJECT(creds) will
> never be freed and result in memory leak.
>
> The leak stack:
> Direct leak of 104 byte(s) in 1 object(s)
From: Frank Chang
This patchset implements the vector extension v0.9 for RISC-V on QEMU.
This patchset is sent as RFC because RVV v0.9 is still in draft state.
However, as RVV v1.0 should be ratified soon and there shouldn't be
critical changes between RVV v1.0 and RVV v0.9. We would like to hav
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 24 ++--
target/riscv/cpu.h | 2 ++
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2800953e6c..641c803089 100644
--- a/target/riscv/cpu.c
+++
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 24 ++--
target/riscv/cpu.h | 2 --
2 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bdb5d..2800953e6c 100644
--- a/target/riscv/cpu.c
+++
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 39f44d1029..4c0a6198e7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv
From: Frank Chang
gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 433cdacbe1..7cd08f0868 100644
--- a/target/riscv/
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a8b3120883..5b0be0bb88 100644
--- a/tar
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
---
target/riscv/cpu.h| 6 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 16 +++-
target/riscv/csr.c| 25 -
4 files changed, 46 insertions(+), 2 del
From: Frank Chang
vill bit is at vtype[XLEN-1].
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 378f6e82bf..27ce075e50 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@
From: Frank Chang
do_opivx_widen() should return false if check function returns false.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 69 -
target/riscv/translate.c| 33
2 files changed, 90 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/
From: Greentime Hu
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7afdd4814b..fe055b67a6 100644
--- a/target/ri
Thomas Huth writes:
> Hi,
>
> On 22/07/2020 09.49, Sai Pavan Boddu wrote:
> [...]
>>> + * This library is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU Lesser General Public
>>> + * License as published by the Free Software Foundation; eit
From: Frank Chang
Introduce the concepts of fractional LMUL, EEW and EMUL for RVV 0.9.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 16 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 17 ++---
target/riscv/internals.h| 11
From: Frank Chang
Remove VXRM and VXSAT fields from FCSR register
as they are only presented in VCSR register.
Signed-off-by: Frank Chang
---
target/riscv/csr.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ab4a4fc132..33c77be06e 10064
On Wed, Jul 22, 2020 at 06:40:28AM +0200, Thomas Huth wrote:
> QEMU on s390x uses virtio via channel I/O instead of PCI by default.
> Add a function to detect and provide information for virtio-scsi and
> virtio-block devices here, too.
>
> Signed-off-by: Thomas Huth
> ---
> qga/commands-posix.c
From: Frank Chang
Update check functions with RVV 0.9 rules.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 706
1 file changed, 474 insertions(+), 232 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_tra
From: Frank Chang
As in RVV 0.9 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 35 +---
target/riscv/internals.h| 9 +-
target/riscv/translate.c
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
---
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c | 21 +
2 files changed, 28 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5b0be0bb88..7afdd4814b 100
From: Frank Chang
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW)
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 6b4b7f6574..af19561e7d 100644
--- a/target
From: Frank Chang
For floating-point operations, the scalar can be taken from a scalar
f register. If FLEN > SEW, the value in the f registers is checked for
a valid NaN-boxed value, in which case the least-significant SEW bits
of the f register are used, else the canonical NaN value is used.
Ad
From: Frank Chang
Introduce the concepts of VMA and VTA for RVV 0.9.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 11 +-
target/riscv/insn_trans/trans_rvv.inc.c | 62 +
target/riscv/internals.h| 6 +-
target/riscv/translate.c
From: Frank Chang
If SEW < FLEN, call narrower_nanbox_fpr helper to generate the
correspond NaN-boxed value.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rv
From: Frank Chang
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 46 -
2 files changed, 40 insertions(+), 9 deletion
On Wed, Jul 22, 2020 at 06:40:27AM +0200, Thomas Huth wrote:
> The libudev-related code is independent from the other pci-related code
> and can be re-used for non-pci devices (like ccw devices on s390x). Thus
> move this part to the generic function.
>
> Buglink: https://bugzilla.redhat.com/show_
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 27 +++-
target/riscv/insn32.decode | 14 +++
target/riscv/insn_trans/trans_rvv.inc.c | 31 --
target/riscv/vector_helper.c| 56 +
* Max Reitz (mre...@redhat.com) wrote:
> RFC v1: https://lists.nongnu.org/archive/html/qemu-block/2020-05/msg00912.html
> RFC v2: https://lists.nongnu.org/archive/html/qemu-block/2020-05/msg00915.html
> v1: https://lists.nongnu.org/archive/html/qemu-devel/2020-06/msg09792.html
>
> Branch: https://
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 12
target/riscv/vector_helper.c| 10 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 0.9's rules.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target
From: Frank Chang
Add the following instructions:
* vl1r.v
* vs1r.v
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvv.inc.c | 61 +
target/riscv/vector_help
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 129 +++---
target/riscv/insn32.decode | 43 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 214 +++-
target/riscv/vector_helper.c| 175 +
From: Frank Chang
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_
From: Frank Chang
Unlike other vector instructions, load/store vector instructions return
the maximum vector size calculated with EMUL.
For other vector instructions, return VLMAX as the maximum vector size.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 118
first, what I said "file size" is file length as reported by ls
-l?field.comment=first, what I said "file size" is file length as
reported by ls -l.
The following attachment shows the size of the same source file after
different conversion methods，
http -> local: qemu-img convert -f raw -O vdi lo
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 67 +
target/riscv/insn32.decode | 21 ++-
target/riscv/insn_trans/trans_rvv.inc.c | 177 +---
target/riscv/vector_helper.c| 84 ++-
4 files
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bc6c788edf..c6a7145aa5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/i
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1d34fa647b..7ad936e605 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.
On Wed, Jul 22, 2020 at 06:40:26AM +0200, Thomas Huth wrote:
> We are going to support non-PCI devices soon. For this we need to split
> the generic GuestDiskAddress and GuestDiskAddressList memory allocation
> and list chaining into a separate function first.
>
> Signed-off-by: Thomas Huth
> ---
From: Frank Chang
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 0.9.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 32 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 11 -
2 files changed, 29 inserti
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 7 ---
target/riscv/vector_helper.c| 6 +++---
4 files changed, 9 insertions(+), 8 deletions
From: Frank Chang
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 956ee9074
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.inc.c | 5 -
target/riscv/vector_helper.c| 4
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn32.decode b/t
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++--
target/riscv/vector_helper.c| 6 +++---
4 files changed, 7 insertions(+), 7 deletions(-)
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 100 ---
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 36 +++-
target/riscv/insn_trans/trans_rvv.inc.c | 212 +++---
target/riscv/ve
1 - 100 of 398 matches
Mail list logo
