On Thu, May 21, 2020 at 1:21 AM Nicolas Dufresne wrote:
>
> Le mercredi 20 mai 2020 à 12:19 +0900, Alexandre Courbot a écrit :
> > On Wed, May 20, 2020 at 2:29 AM Nicolas Dufresne
> > wrote:
> > > Le mardi 19 mai 2020 à 17:37 +0900, Keiichi Watanabe a écrit :
> > > > Hi Nicolas,
> > > >
> > > >
On 5/21/2020 10:38 AM, Yan Zhao wrote:
On Wed, May 20, 2020 at 10:46:12AM -0600, Alex Williamson wrote:
On Wed, 20 May 2020 19:10:07 +0530
Kirti Wankhede wrote:
On 5/20/2020 8:25 AM, Yan Zhao wrote:
On Tue, May 19, 2020 at 10:58:04AM -0600, Alex Williamson wrote:
Hi folks,
My impression
On Thu, May 21, 2020 at 12:39:48PM +0530, Kirti Wankhede wrote:
>
>
> On 5/21/2020 10:38 AM, Yan Zhao wrote:
> > On Wed, May 20, 2020 at 10:46:12AM -0600, Alex Williamson wrote:
> > > On Wed, 20 May 2020 19:10:07 +0530
> > > Kirti Wankhede wrote:
> > >
> > > > On 5/20/2020 8:25 AM, Yan Zhao wro
On 5/21/2020 12:34 PM, Yan Zhao wrote:
On Thu, May 21, 2020 at 12:39:48PM +0530, Kirti Wankhede wrote:
On 5/21/2020 10:38 AM, Yan Zhao wrote:
On Wed, May 20, 2020 at 10:46:12AM -0600, Alex Williamson wrote:
On Wed, 20 May 2020 19:10:07 +0530
Kirti Wankhede wrote:
On 5/20/2020 8:25 AM,
On Wed, 20 May 2020 12:13:35 -0400
"Michael S. Tsirkin" wrote:
> On Wed, May 20, 2020 at 02:20:12PM +0200, Igor Mammedow wrote:
> > On Wed, 20 May 2020 07:23:21 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > On Wed, May 20, 2020 at 01:05:47PM +0200, Igor Mammedow wrote:
> > > > On Wed, 20
On 5/21/2020 12:34 PM, Yan Zhao wrote:
On Thu, May 21, 2020 at 12:39:48PM +0530, Kirti Wankhede wrote:
On 5/21/2020 10:38 AM, Yan Zhao wrote:
On Wed, May 20, 2020 at 10:46:12AM -0600, Alex Williamson wrote:
On Wed, 20 May 2020 19:10:07 +0530
Kirti Wankhede wrote:
On 5/20/2020 8:25 AM,
On 5/20/20 5:43 PM, Markus Armbruster wrote:
> Cédric Le Goater writes:
>
>> On 5/20/20 8:34 AM, Markus Armbruster wrote:
>>> Cédric Le Goater writes:
>>>
The AST2400 and AST2500 SoCs have two MACs but only the first MAC0 is
active on the Aspeed machines using these SoCs. The AST2600 h
On Wed, 20 May 2020 15:19:50 +0200
Gerd Hoffmann wrote:
> Rename memory region and callbacks and ops to carry "evt" in the name
> because a second region will be added shortly.
>
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Igor Mammedow
> ---
> include/hw/acpi/generic_event_device.h | 2 +-
Paolo, Million thanks.
I will try to dig into this code in my spare time.
Thanks,
Feng Li
Paolo Bonzini 于2020年5月20日周三 下午6:27写道：
>
> On 20/05/20 12:15, Li Feng wrote:
> > /root/qemu-master/x86_64-softmmu/qemu-system-x86_64 -enable-kvm
> > -device virtio-balloon -cpu
> > host,-vmx-exit-nosave-deb
Thomas Huth writes:
> On 13/05/2020 19.51, Alex Bennée wrote:
>> First we ensure all guest space initialisation logic comes through
>> probe_guest_base once we understand the nature of the binary we are
>> loading. The convoluted init_guest_space routine is removed and
>> replaced with a number
By force-enabling the WAITPKG bit whenever -overcommit cpu-pm=on is used,
commit 67192a298f ("x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE",
2019-10-23) broke that option is the host processor does not have
WAITPKG or the host kernel is too old. This is because TPAUSE, UMWAIT
and UMONITOR are n
>> +static void realize_event_facility(DeviceState *dev, Error **errp)
>> +{
>> +SCLPEventFacility *event_facility = EVENT_FACILITY(dev);
>> +Error *local_err = NULL;
>> +
>> +qdev_realize(DEVICE(&event_facility->quiesce),
>> + BUS(&event_facility->sbus), &local_err);
On Wed, 20 May 2020 15:19:51 +0200
Gerd Hoffmann wrote:
> Add control regs (sleep, reset) for hw-reduced acpi.
>
> Signed-off-by: Gerd Hoffmann
this should be acompanied by docs update
docs/specs/acpi_hw_reduced_hotplug.rst
to document new registers and their semantics
and probaly rename fil
On Thu, 21 May 2020 15:13:45 +1000
David Gibson wrote:
> On Thu, May 21, 2020 at 01:36:16AM +0200, Greg Kurz wrote:
> > On Mon, 18 May 2020 16:44:18 -0500
> > Reza Arbab wrote:
> >
> > > NUMA nodes corresponding to GPU memory currently have the same
> > > affinity/distance as normal memory node
On Wed, 20 May 2020 15:19:52 +0200
Gerd Hoffmann wrote:
> Set AcpiDeviceIfClass->madt_cpu,
> otherwise identical to TYPE_ACPI_GED.
>
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Igor Mammedov
> ---
> include/hw/acpi/generic_event_device.h | 4 +++
> hw/i386/generic_event_device_x86.c |
On Wed, 20 May 2020 15:19:53 +0200
Gerd Hoffmann wrote:
> Allow reuse for microvm.
>
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Igor Mammedov
> ---
> include/hw/acpi/generic_event_device.h | 1 +
> hw/acpi/generic_event_device.c | 8
> hw/arm/virt-acpi-build.c
Introduce a specialized SMMUTLBEntry to store the result of
the PTW and cache in the IOTLB. This structure extends the
generic IOMMUTLBEntry struct with the level of the entry and
the granule size.
Those latter will be useful when implementing range invalidation.
Signed-off-by: Eric Auger
---
i
Page and block PTE decoding can share some code. Let's
first handle table PTE and factorize some code shared by
page and block PTEs.
Signed-off-by: Eric Auger
---
hw/arm/smmu-common.c | 51
1 file changed, 18 insertions(+), 33 deletions(-)
diff --git
At the moment each entry in the IOTLB corresponds to a page sized
mapping (4K, 16K or 64K), even if the page belongs to a mapped
block. In case of block mapping this unefficiently consume IOTLB
entries.
Change the value of the entry so that it reflects the actual
mapping it belongs to (block or pa
SMMU3.2 brings the support of range-based TLB invalidation and
level hint. When this feature is supported, the SMMUv3 driver
is allowed to send TLB invalidations for a range of IOVAs instead
of using page based invalidation.
Implementing this feature in the virtual SMMUv3 device is
mandated for DP
Let's introduce an helper for S1 IOVA range invalidation.
This will be used for NH_VA and NH_VAA commands. It decodes
the same fields, trace, calls the UNMAP notifiers and
invalidate the corresponding IOTLB entries.
At the moment, we do not support 3.2 range invalidation yet.
So it reduces to a si
Compute the starting level on CD decoding and store it
into SMMUTransTableInfo. We will need this information
on IOTLB lookup so let's avoid to recompute it each time.
Signed-off-by: Eric Auger
---
include/hw/arm/smmu-common.h | 1 +
hw/arm/smmu-common.c | 2 +-
hw/arm/smmuv3.c
Add two helpers to lookup for a given IOTLB entry and
an one. We also more the tracing there.
Signed-off-by: Eric Auger
---
include/hw/arm/smmu-common.h | 2 ++
hw/arm/smmu-common.c | 36
hw/arm/smmuv3.c | 26 ++
Enhance the smmu_iotlb_inv_iova() helper with range invalidation.
This uses the new fields passed in the NH_VA and NH_VAA commands:
the size of the range, the level and the granule.
As NH_VA and NH_VAA both use those fields, their decoding and
handling is factorized in a new smmuv3_s1_range_inval(
On Wed, 20 May 2020 15:19:55 +0200
Gerd Hoffmann wrote:
> Looks like the logiv was copied over from q35.
>
> q35 does this for backward compatibility, there is no reason to do this
> on microvm though. So split @ 2G unconditionally.
>
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Igor Mammedov
Expose the RIL bit so that the guest driver uses range
invalidation.
Signed-off-by: Eric Auger
---
hw/arm/smmuv3-internal.h | 1 +
hw/arm/smmuv3.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 5babf72f7d..4e7ec252ed 1006
Instead of using a Jenkins hash function to generate
the key let's just use a 64 bit unsigned integer that
contains the asid and the 40 upper bits of the iova.
A maximum of 52-bit IOVA is supported. This change in the
key format also prepares for the addition of new fields
in subsequent patches (gr
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v8).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode pro
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
On Wed, 20 May 2020 15:19:55 +0200
Gerd Hoffmann wrote:
> Looks like the logiv was copied over from q35.
>
> q35 does this for backward compatibility, there is no reason to do this
> on microvm though. So split @ 2G unconditionally.
not related to your ACPI rework, but just an idea for future
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.
On Wed, Apr 29, 2020 at 03:44:17PM -0400, Daniele Buono wrote:
> diff --git a/include/qemu/coroutine_int.h b/include/qemu/coroutine_int.h
> index bd6b0468e1..2ffd75ddbe 100644
> --- a/include/qemu/coroutine_int.h
> +++ b/include/qemu/coroutine_int.h
> @@ -28,6 +28,12 @@
> #include "qemu/queue.h"
>
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v8).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode pro
On Thu, May 21, 2020 at 09:40:55AM +0800, Robert Hoo wrote:
> On Wed, 2020-05-20 at 10:17 +0100, Daniel P. Berrangé wrote:
> > On Wed, May 20, 2020 at 10:10:07AM +0800, Chenyi Qiang wrote:
> > > There are no Icelake Desktop products in the market. Remove the
> > > Icelake-Client CPU model.
> >
> >
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.
On Wed, Apr 29, 2020 at 03:44:18PM -0400, Daniele Buono wrote:
s/sigalstack/sigaltstack/ in the commit message.
> LLVM's SafeStack instrumentation cannot be used inside signal handlers
> that make use of sigaltstack().
> Since coroutine-sigaltstack relies on sigaltstack(), it is not
> compatible
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.
* Kirti Wankhede (kwankh...@nvidia.com) wrote:
> These functions save and restore PCI device specific data - config
> space of PCI device.
> Tested save and restore with MSI and MSIX type.
>
> Signed-off-by: Kirti Wankhede
> Reviewed-by: Neo Jia
So I'm OK with this from the migration side, but
On Wed, Apr 29, 2020 at 03:44:19PM -0400, Daniele Buono wrote:
> This patch adds a flag to enable the SafeStack instrumentation provided
> by LLVM.
> The checks make sure that the compiler supports the flags, and that we
> are using the proper coroutine implementation (coroutine-ucontext).
> While
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Ri
The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/internals.h | 24
1 file changed, 24 insertions(
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from
Hi,
The cluster_size got from backup_calculate_cluster_size(),
MAX(BACKUP_CLUSTER_SIZE_DEFAULT, bdi.cluster_size), is 64K regardless
of the target image's cluster size.
For example:
If the cluster size of source and target qcow2 images are both 16K, the
64K from backup_calculate_cluster_size(
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h
On Wed, Apr 29, 2020 at 03:44:20PM -0400, Daniele Buono wrote:
> SafeStack is a stack protection technique implemented in llvm. It is
> enabled with a -fsanitize flag.
> iotests are currently disabled when any -fsanitize option is used.
> Since SafeStack is useful on production environments, and it
* Kirti Wankhede (kwankh...@nvidia.com) wrote:
> - Migration functions are implemented for VFIO_DEVICE_TYPE_PCI device in this
> patch series.
> - VFIO device supports migration or not is decided based of migration region
> query. If migration region query is successful and migration region
>
On Wed, May 13, 2020 at 10:48:04AM -0400, Daniele Buono wrote:
> Hello everybody, just pinging since it it's been a few days.
Hi Daniele,
Sorry I'm late to the party. This looks useful, the patches are not
invasive and provide the option of enabling extra security.
I have left comments on specifi
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by:
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Franc
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 25 ++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 291
target/riscv/vector_helper.c
On Wed, May 20, 2020 at 03:20:23PM +0200, Marek Marczykowski-Górecki wrote:
> In case of not using random-number needing feature, it makes sense to
> skip RNG init too. This is especially helpful when QEMU is sandboxed in
> Stubdomain under Xen, where there is very little entropy so initial
> getra
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 49 +++
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 186
target/riscv/vector_helper.
On Thu, May 21, 2020 at 09:32:17AM +0200, Igor Mammedow wrote:
> On Wed, 20 May 2020 12:13:35 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Wed, May 20, 2020 at 02:20:12PM +0200, Igor Mammedow wrote:
> > > On Wed, 20 May 2020 07:23:21 -0400
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On We
+-- On Wed, 20 May 2020, Philippe Mathieu-Daudé wrote --+
| Prasad, I once tried to remove it, and Kevin said he was using it:
|
| https://lists.nongnu.org/archive/html/qemu-devel/2017-12/msg02765.html
|
| I do find qemu's PCI SDHCI support useful for testing.
| SeaBIOS can launch an OS from
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 11 ++
target/riscv/insn_trans/trans_rvv.inc.c | 113 +++
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c
On Wed, 20 May 2020 15:19:57 +0200
Gerd Hoffmann wrote:
> $subject says all. Can be controlled using -M microvm,acpi=on/off.
thanks for really nice and clean impl.
There are a couple minor notes below, but otherwise
Reviewed-by: Igor Mammedov
>
> Signed-off-by: Gerd Hoffmann
> ---
> hw/i3
On Tue, 19 May 2020 at 17:49, Richard Henderson
wrote:
>
> The following changes since commit f2465433b43fb87766d79f42191607dac4aed5b4:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2020-05-19 13:42:58 +0100)
>
> are available in the Git repository
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 52
target/riscv/vector_helper.c
On Wed, 20 May 2020 15:19:58 +0200
Gerd Hoffmann wrote:
> Makes x86 linux kernel find virtio-mmio devices automatically.
>
> Signed-off-by: Gerd Hoffmann
> Reviewed-by: Sergio Lopez
Reviewed-by: Igor Mammedov
> ---
> hw/i386/acpi-microvm.c | 52 ++
>
On Wed, 20 May 2020 15:19:59 +0200
Gerd Hoffmann wrote:
> With ACPI enabled and IO-APIC being properly declared in the ACPI tables
> we can use interrupt lines 16-23 for virtio and avoid shared interrupts.
>
> With acpi disabled we continue to use lines 8-15.
>
> Signed-off-by: Gerd Hoffmann
>
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 90 +
target/riscv/vector_helper.c
On Wed, 20 May 2020 15:20:00 +0200
Gerd Hoffmann wrote:
> With acpi=off continue to use qboot.
>
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Igor Mammedov
> ---
> hw/i386/microvm.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/hw/i386/microvm.c b/hw/i386/micr
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode | 20
target/riscv/insn_trans/trans_rvv.inc.c | 46 +
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 71
On Thu, May 07, 2020 at 10:28:32AM +0100, Daniel P. Berrangé wrote:
> If the person in the host launching virtiofsd is non-root, then
> user namespaces mean they can offer the guest the full range of
> POSIX APIs wrt access control & file ownership, since they're
> no longer restricted to their sin
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 33 +
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 163 +
Newer clangs rightly spot that you can never exceed the full address
space of 64 bit hosts with:
linux-user/elfload.c:2076:41: error: result of comparison 'unsigned
long' > 18446744073709551615 is always false
[-Werror,-Wtautological-type-limit-compare]
4685 if ((guest_hiaddr - gue
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51 ++
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 88 ++
On Wed, 20 May 2020 15:20:02 +0200
Gerd Hoffmann wrote:
> Allow setting acpi default value for each machine type.
>
> Signed-off-by: Gerd Hoffmann
> ---
> include/hw/i386/x86.h | 1 +
> hw/i386/x86.c | 21 ++---
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
>
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 22
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvv.inc.c | 9 +
target/riscv/vector_helper.c|
On Thu, 21 May 2020 at 11:22, Alex Bennée wrote:
>
> Newer clangs rightly spot that you can never exceed the full address
> space of 64 bit hosts with:
>
> linux-user/elfload.c:2076:41: error: result of comparison 'unsigned
> long' > 18446744073709551615 is always false
> [-Werror,-Wtautolog
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 113
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 +
target/riscv/vector_helper.c| 385 ++
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 100
4 files chan
The fix has been merged:
https://git.qemu.org/?p=qemu.git;a=commit;h=f2465433b43fb87766d79f42191607dac4aed5b4
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You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1877716
Title:
Win10 guest unusable after
On Wed, 20 May 2020 15:20:03 +0200
Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> hw/i386/microvm.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
> index 602c6a8f75f3..b5c445b5403b 100644
> --- a/hw/i386/microvm.c
> +++ b/hw/i38
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 107
4 files changed,
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 205
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 117 ++
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 +
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 141
On Thu, May 21, 2020 at 11:19:23AM +0100, Stefan Hajnoczi wrote:
> On Thu, May 07, 2020 at 10:28:32AM +0100, Daniel P. Berrangé wrote:
> > If the person in the host launching virtiofsd is non-root, then
> > user namespaces mean they can offer the guest the full range of
> > POSIX APIs wrt access co
For scalar float instruction, round mode is encoded in instruction,
so fp_status is updating dynamiclly.
For vector float instruction, round mode is always frm, so
update fp_status when frm changes is enough.
Signed-off-by: LIU Zhiwei
---
target/riscv/csr.c| 7 +++
target/riscv/fpu
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 116
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 145
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 49 +++
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22 +++
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 251 +
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 91 +++
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 42
target/riscv/vector_helper.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.inc.c | 6 ++
target/riscv/vector_helper.c|
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 19 ++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
target/riscv/vector_helper.c| 85 +++
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 37 +
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvv.inc.c | 35 +
target/riscv/vector_helper.c| 174
4 files
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c | 33 +
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 +
target/riscv/internals.h
20.05.2020 19:39, Eric Blake wrote:
On 5/20/20 3:35 AM, Vladimir Sementsov-Ogievskiy wrote:
These cases are fixed by previous patches around block_status and
is_allocated.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/274 | 20
tests/qemu-iotests/274.ou
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 38 +
target/riscv/vector_helper.c| 24
4 files changed, 68 insertions(+)
On Mon, May 18, 2020 at 11:28:02PM +0300, Alexey Krasikov wrote:
> Create base class 'common secret'. Move common data and logic from
> 'secret' to 'common_secret' class. This allowed adding abstraction layer
> for easier adding new 'secret' objects in future.
> Convert 'secret' class to child from
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