Re: [PATCH] hw/ide: Remove status register read side effect

Patchew URL: https://patchew.org/QEMU/20200221065015.337915-1-jasper.low...@bt.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN

Re: [PATCH v2 0/2] docs: rstfy some s390 docs

On Thu, 13 Feb 2020 17:29:40 +0100 Cornelia Huck wrote: > https://qemu.readthedocs.io/en/latest/index.html collects various > documents from the QEMU docs/ subdirectory; however, none of the > s390 files are currently included. Therefore, I set out to convert > the existing files to rst and hook

Re: [PATCH] hw/char/pl011: Enable TxFIFO and async transmission

On 21/02/20 05:49, Gavin Shan wrote: > @@ -306,6 +362,7 @@ static const VMStateDescription vmstate_pl011 = { > VMSTATE_UINT32(int_enabled, PL011State), > VMSTATE_UINT32(int_level, PL011State), > VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16), > +VMSTATE_UINT8_ARR

Re: [PATCH qemu v7 0/5] spapr: Kill SLOF

On 21/02/20 01:18, Alexey Kardashevskiy wrote: > I am not quite sure I understood the request. Write my own small > firmware and replace GRUB with it? The firmware from 5/5 reads first 2 > sectors and the entire PReP, I could add there stuff if that helps (I > have "work in progress" patch for the

Re: [PATCH v1 10/13] migrate/ram: Handle RAM block resizes during postcopy

On 20.02.20 21:54, Peter Xu wrote: > On Wed, Feb 19, 2020 at 05:17:22PM +0100, David Hildenbrand wrote: >> Resizing while migrating is dangerous and does not work as expected. >> The whole migration code works on the usable_length of ram blocks and does >> not expect this to change at random points

Re: [PATCH] maint: Include top-level *.rst files early in git diff

On Thu, Feb 20, 2020 at 10:22:13AM -0600, Eric Blake wrote: > We are converting more doc files to *.rst rather than *.texi. Most > doc files are already listed early in diffs due to our catchall > docs/*, but a few top-level files get missed by that glob. > > Signed-off-by: Eric Blake > --- > >

Re: [PATCH v3 08/20] Remove unnecessary cast when using the address_space API

On Thu, 20 Feb 2020 14:05:36 +0100 Philippe Mathieu-Daudé wrote: > This commit was produced with the included Coccinelle script > scripts/coccinelle/exec_rw_const. > > Two lines in hw/net/dp8393x.c that Coccinelle produced that > were over 80 characters were re-wrapped by hand. > > Suggested-by

Re: [PATCH v1 10/13] migrate/ram: Handle RAM block resizes during postcopy

On 21.02.20 09:35, David Hildenbrand wrote: > On 20.02.20 21:54, Peter Xu wrote: >> On Wed, Feb 19, 2020 at 05:17:22PM +0100, David Hildenbrand wrote: >>> Resizing while migrating is dangerous and does not work as expected. >>> The whole migration code works on the usable_length of ram blocks and d

Re: [PATCH v3 19/20] Let cpu_[physical]_memory() calls pass a boolean 'is_write' argument

On Thu, 20 Feb 2020 14:05:47 +0100 Philippe Mathieu-Daudé wrote: > Use an explicit boolean type. > > This commit was produced with the included Coccinelle script > scripts/coccinelle/exec_rw_const. > > Signed-off-by: Philippe Mathieu-Daudé > --- > scripts/coccinelle/exec_rw_const.cocci | 14 +

Re: [PATCH v1 13/13] migrate/ram: Tolerate partially changed mappings in postcopy code

On 20.02.20 22:07, Peter Xu wrote: > On Thu, Feb 20, 2020 at 12:24:42PM +0100, David Hildenbrand wrote: >> On 19.02.20 17:17, David Hildenbrand wrote: >>> When we partially change mappings (e.g., mmap over parts of an existing >>> mmap) where we have a userfaultfd handler registered, the handler wi

Re: [PATCH 1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u

On 2/21/20 6:54 AM, Anup Patel wrote: On Fri, Feb 21, 2020 at 8:08 AM Bin Meng wrote: Hi Philippe, On Fri, Feb 21, 2020 at 1:31 AM Philippe Mathieu-Daudé wrote: Hi Bin, On 2/20/20 3:42 PM, Bin Meng wrote: Although the real world SiFive HiFive Unleashed board is a 64-bit hardware configur

Re: [Virtio-fs] [PATCH] virtiofsd: Remove fuse.h and struct fuse_module

On Fri, Feb 21, 2020 at 02:55:15PM +0800, Xiao Yang wrote: > All code in fuse.h and struct fuse_module are not used by virtiofsd > so removing them is safe. > > Signed-off-by: Xiao Yang > --- > tools/virtiofsd/fuse.h | 1229 -- > tools/virtiofsd/fuse_i.h |

Re: [PATCH v1 1/2] linux-user: Protect more syscalls

On 2/21/20 12:18 AM, Alistair Francis wrote: New y2038 safe 32-bit architectures (like RISC-V) don't support old syscalls with a 32-bit time_t. The kernel defines new *_time64 versions of these syscalls. Add some more #ifdefs to syscall.c in linux-user to allow us to compile without these old sys

Re: [PATCH] hw/char/pl011: Enable TxFIFO and async transmission

On 2/21/20 7:25 PM, Paolo Bonzini wrote: On 21/02/20 05:49, Gavin Shan wrote: @@ -306,6 +362,7 @@ static const VMStateDescription vmstate_pl011 = { VMSTATE_UINT32(int_enabled, PL011State), VMSTATE_UINT32(int_level, PL011State), VMSTATE_UINT32_ARRAY(read_fifo, PL011S

Re: [PATCH] target: i386: Check float overflow about register stack

On 21/02/20 04:45, cheng...@emindsoft.com.cn wrote: > static inline void fpush(CPUX86State *env) > { > -env->fpstt = (env->fpstt - 1) & 7; > -env->fptags[env->fpstt] = 0; /* validate stack entry */ > +set_fpstt(env, env->fpstt - 1, false, true); On overflow fpstt is ~0, so this does:

Re: [PATCH] rcu_queue: add QSLIST functions

On Thu, Feb 20, 2020 at 11:38:28AM +0100, Paolo Bonzini wrote: > QSLIST is the only family of lists for which we do not have RCU-friendly > accessors, > add them. > > Signed-off-by: Paolo Bonzini > --- > include/qemu/queue.h | 15 +++-- > include/qemu/rcu_queue.h | 47 ++

Re: [PATCH v1 06/13] migrate/ram: Discard new RAM when growing RAM blocks and the VM is stopped

On 19.02.20 17:17, David Hildenbrand wrote: > In case we grow our RAM after ram_postcopy_incoming_init() (e.g., when > synchronizing the RAM block state with the migration source), the resized > part would not get discarded. Let's perform that when being notified > about a resize while postcopy has

Re: [PATCH] hw/char/pl011: Output characters using best-effort mode

Hi Gavin, On 2020-02-21 04:24, Gavin Shan wrote: Hi Peter and Marc, On 2/20/20 9:10 PM, Peter Maydell wrote: On Thu, 20 Feb 2020 at 09:10, Marc Zyngier wrote: On 2020-02-20 06:01, Gavin Shan wrote: This fixes the issue by using newly added API qemu_chr_fe_try_write_all(), which provides ano

Re: [PATCH v4] Implement the Screamer sound chip for the mac99 machine type

Hi, It might be worth mentioning that any testing of your screamer implementation with MacOS/OSX guests on the mac99 machine needs a custom-built openbios. Where possible I'll compare your screamer with the current screamer implementation built from: git clone -b screamer https://github.com/mcayl

Re: [PATCH v1 05/13] migrate/ram: Handle RAM block resizes during precopy

On 20.02.20 21:17, Peter Xu wrote: > On Thu, Feb 20, 2020 at 04:16:02PM +0100, David Hildenbrand wrote: >> On 19.02.20 17:17, David Hildenbrand wrote: >>> Resizing while migrating is dangerous and does not work as expected. >>> The whole migration code works on the usable_length of ram blocks and d

Re: [PATCH v7 02/11] error: auto propagated local_err

Vladimir Sementsov-Ogievskiy writes: > Here is introduced ERRP_AUTO_PROPAGATE macro, to be used at start of > functions with an errp OUT parameter. > > It has three goals: > > 1. Fix issue with error_fatal and error_prepend/error_append_hint: user > can't see this additional information, because

Re: [PATCH v7 01/11] qapi/error: add (Error **errp) cleaning APIs

21.02.2020 10:38, Markus Armbruster wrote: Vladimir Sementsov-Ogievskiy writes: Add functions to clean Error **errp: call corresponding Error *err cleaning function an set pointer to NULL. New functions: error_free_errp error_report_errp warn_report_errp Signed-off-by: Vladimir Seme

Re: [PATCH] hw/char/pl011: Enable TxFIFO and async transmission

Cc'ing Igor & Drew. On 2/21/20 7:28 AM, no-re...@patchew.org wrote: Patchew URL: https://patchew.org/QEMU/20200221044908.266883-1-gs...@redhat.com/ > === TEST SCRIPT BEGIN === #!/bin/bash make docker-image-centos7 V=1 NETWORK=1 time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1 ===

[PATCH v3] util/async: make bh_aio_poll() O(1)

The ctx->first_bh list contains all created BHs, including those that are not scheduled. The list is iterated by the event loop and therefore has O(n) time complexity with respected to the number of created BHs. Rewrite BHs so that only scheduled or deleted BHs are enqueued. Only BHs that actuall

Re: [PATCH v7 02/11] error: auto propagated local_err

21.02.2020 12:19, Markus Armbruster wrote: Vladimir Sementsov-Ogievskiy writes: Here is introduced ERRP_AUTO_PROPAGATE macro, to be used at start of functions with an errp OUT parameter. It has three goals: 1. Fix issue with error_fatal and error_prepend/error_append_hint: user can't see thi

[PATCH v5 0/4] target-riscv: support vector extension part 1

This is the first part of v5 patchset. The changelog of v5 is only coverd the part1. Features: * support specification riscv-v-spec-0.7.1. * support basic vector extension. * support Zvlsseg. * support Zvamo. * not support Zvediv as it is changing. * SLEN always equals VLEN. * elemen

[PATCH v5 3/4] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 - 2 files

[PATCH v5 2/4] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 7 +++ target/riscv/cpu.h | 5 + 2 files changed, 12 insertions(+) diff --git a/ta

Re: [PATCH] hw/char/pl011: Enable TxFIFO and async transmission

On 2/21/20 10:37 AM, Philippe Mathieu-Daudé wrote: Cc'ing Igor & Drew. On 2/21/20 7:28 AM, no-re...@patchew.org wrote: Patchew URL: https://patchew.org/QEMU/20200221044908.266883-1-gs...@redhat.com/ > === TEST SCRIPT BEGIN === #!/bin/bash make docker-image-centos7 V=1 NETWORK=1 time make doc

[PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 12 1 file

Re: [PATCH] virtiofsd: Remove fuse.h and struct fuse_module

On 2/21/20 7:55 AM, Xiao Yang wrote: All code in fuse.h and struct fuse_module are not used by virtiofsd so removing them is safe. Signed-off-by: Xiao Yang --- tools/virtiofsd/fuse.h | 1229 -- tools/virtiofsd/fuse_i.h | 16 - 2 files changed, 1245 de

[PATCH v5 4/4] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei --- MAINTAINERS |

Re: [PATCH v4 02/16] s390x: protvirt: Add diag308 subcodes 8 - 10

On Thu, 20 Feb 2020 07:56:24 -0500 Janosch Frank wrote: > For diag308 subcodes 8 - 10 we have a new ipib of type 5. The ipib > holds the address and length of the secure execution header, as well > as a list of guest components. > > Each component is a block of memory, for example kernel or init

Re: Race condition in overlayed qcow2?

Vladimir Sementsov-Ogievskiy писал 2020-02-20 12:36: 20.02.2020 12:05, Vladimir Sementsov-Ogievskiy wrote: 20.02.2020 11:31, dovgaluk wrote: Vladimir Sementsov-Ogievskiy писал 2020-02-19 19:07: 19.02.2020 17:32, dovgaluk wrote: I encountered a problem with record/replay of QEMU execution and

Re: [PATCH v3] util/async: make bh_aio_poll() O(1)

On Fri, Feb 21, 2020 at 9:40 AM Stefan Hajnoczi wrote: > > The ctx->first_bh list contains all created BHs, including those that > are not scheduled. The list is iterated by the event loop and therefore > has O(n) time complexity with respected to the number of created BHs. > > Rewrite BHs so tha

Re: [PATCH v4 16/16] docs: Add protvirt docs

On Thu, 20 Feb 2020 07:56:38 -0500 Janosch Frank wrote: > Lets add some documentation for the Protected VM functionality. > > Signed-off-by: Janosch Frank > --- > docs/protvirt.rst | 53 +++ > 1 file changed, 53 insertions(+) > create mode 100644 do

Re: [PATCH] console: make QMP screendump use coroutine

Am 20.02.2020 um 17:01 hat Markus Armbruster geschrieben: > >> > void qmp_screendump(const char *filename, bool has_device, const char > >> > *device, > >> > bool has_head, int64_t head, Error **errp) > >> > { > >> > QemuConsole *con; > >> > DisplaySurface *surface

Re: Race condition in overlayed qcow2?

21.02.2020 12:49, dovgaluk wrote: Vladimir Sementsov-Ogievskiy писал 2020-02-20 12:36: 20.02.2020 12:05, Vladimir Sementsov-Ogievskiy wrote: 20.02.2020 11:31, dovgaluk wrote: Vladimir Sementsov-Ogievskiy писал 2020-02-19 19:07: 19.02.2020 17:32, dovgaluk wrote: I encountered a problem with r

Re: [PATCH v1 05/13] migrate/ram: Handle RAM block resizes during precopy

On 21.02.20 10:18, David Hildenbrand wrote: > On 20.02.20 21:17, Peter Xu wrote: >> On Thu, Feb 20, 2020 at 04:16:02PM +0100, David Hildenbrand wrote: >>> On 19.02.20 17:17, David Hildenbrand wrote: Resizing while migrating is dangerous and does not work as expected. The whole migration c

[Bug 1857811] Re: qemu user static binary seems to lack support for network namespace.

Yes, it's fixed in v4.2.0, and with the help of your test program I've bisect to the fix: commit 1645fb5a1e537f85eda744bfa6e9d3dda047ba28 Author: Shu-Chun Weng Date: Thu Oct 17 17:19:20 2019 -0700 Fix unsigned integer underflow in fd-trans.c In any of these `*_for_each_*` function

Re: [PATCH] maint: Include top-level *.rst files early in git diff

On Thu, 20 Feb 2020 at 16:22, Eric Blake wrote: > > We are converting more doc files to *.rst rather than *.texi. Most > doc files are already listed early in diffs due to our catchall > docs/*, but a few top-level files get missed by that glob. > > Signed-off-by: Eric Blake > --- > > Both *.tex

Re: [PATCH v1 05/13] migrate/ram: Handle RAM block resizes during precopy

On 21.02.20 11:10, David Hildenbrand wrote: > On 21.02.20 10:18, David Hildenbrand wrote: >> On 20.02.20 21:17, Peter Xu wrote: >>> On Thu, Feb 20, 2020 at 04:16:02PM +0100, David Hildenbrand wrote: On 19.02.20 17:17, David Hildenbrand wrote: > Resizing while migrating is dangerous and doe

Re: [PATCH] hw/char/pl011: Output characters using best-effort mode

On Fri, 21 Feb 2020 at 04:24, Gavin Shan wrote: > If above analysis is correct and the first approach doesn't work out. We have > to > consider the 2nd approach - adding option to backend to allow losing data. I'm > going to add "allow-data-lost" option for TYPE_CHARDEV_SOCKET. With the > option

Re: [PATCH] console: make QMP screendump use coroutine

* Markus Armbruster (arm...@redhat.com) wrote: > "Dr. David Alan Gilbert" writes: > > > * Markus Armbruster (arm...@redhat.com) wrote: > [...] > >> Collecting several users before building infrastructure makes sense when > >> the design of the infrastructure isn't obvious, or when the need for it

Re: [PATCH/RFC 0/1] Vhost User Cross Cable: Intro

On Thu, Feb 13, 2020 at 03:48:59PM +0200, Nikos Dragazis wrote: > On Tue, 14 Jan 2020 at 10:20 Stefan Hajnoczi > wrote: > > On Fri, Jan 10, 2020 at 10:34 AM Marc-André Lureau > > wrote: > > > On Wed, Jan 8, 2020 at 5:57 AM V. wrote: > > > > Hi V., > > I think I remember you from Etherboot/gPXE d

Re: [PATCH v2 2/4] virtio-scsi: default num_queues to -smp N

On Wed, Feb 12, 2020 at 11:18:32AM +, Stefan Hajnoczi wrote: > On Tue, Feb 11, 2020 at 11:31:17AM -0500, Michael S. Tsirkin wrote: > > On Tue, Feb 11, 2020 at 04:20:41PM +, Stefan Hajnoczi wrote: > > > On Mon, Feb 03, 2020 at 12:39:49PM +0100, Sergio Lopez wrote: > > > > On Mon, Feb 03, 202

Re: [GSoC/Outreachy] Arduino complete setup visualization and emulation

On Tue, Feb 11, 2020 at 10:51:19AM +, Stefan Hajnoczi wrote: > On Mon, Feb 10, 2020 at 08:58:28PM +0100, Philippe Mathieu-Daudé wrote: Ping? QEMU has been accepted as a mentoring organization. Please post a final version of this project idea on the wiki: https://wiki.qemu.org/Google_Summe

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

Hi all. How is it going? Regards, Michael. On Mon, Feb 10, 2020 at 9:39 AM Michael Rolnik wrote: > Hi all. > > When I decided to implement AVR 8 bit CPU support for QEMU I found this > document > > whi

[Bug 1722884] Re: keyboard input while mouse moving triggers mouse failure

I tracked this down and fixed it last year, your issue is unrelated. https://github.com/qemu/qemu/commit/143c04c7e0639e53086519592ead15d2556bfbf2 #diff-3b5bd599c018d558b135bd19647a00c6 https://github.com/qemu/qemu/commit/7abe7eb29494b4e4a11ec99ae5623083409a2f1e #diff-3b5bd599c018d558b135bd19647a0

Re: [GSoC/Outreachy] Arduino complete setup visualization and emulation

On 2/21/20 11:56 AM, Stefan Hajnoczi wrote: On Tue, Feb 11, 2020 at 10:51:19AM +, Stefan Hajnoczi wrote: On Mon, Feb 10, 2020 at 08:58:28PM +0100, Philippe Mathieu-Daudé wrote: Ping? QEMU has been accepted as a mentoring organization. Please post a final version of this project idea on t

Re: [PATCH v3 1/4] luks: extract qcrypto_block_calculate_payload_offset()

On Wed, Feb 19, 2020 at 02:03:50PM +0100, Max Reitz wrote: > On 11.02.20 17:03, Stefan Hajnoczi wrote: > > The qcow2 .bdrv_measure() code calculates the crypto payload offset. > > This logic really belongs in crypto/block.c where it can be reused by > > other image formats. > > > > The "luks" bloc

Re: [PATCH v3 2/4] luks: implement .bdrv_measure()

On Wed, Feb 19, 2020 at 04:46:34PM +0100, Max Reitz wrote: > On 11.02.20 17:03, Stefan Hajnoczi wrote: > > Add qemu-img measure support in the "luks" block driver. > > > > Signed-off-by: Stefan Hajnoczi > > --- > > block/crypto.c | 62 ++ > > 1 fil

Re: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm

On Fri, Feb 21, 2020 at 02:35:11PM +0800, Yubo Miao wrote: > From: miaoyubo > > Currently virt machine is not supported by pxb-pcie, > and only one main host bridge described in ACPI tables. > In this patch,PXB-PCIE is supproted by arm and certain > resource is allocated for each pxb-pcie in acpi

Re: [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm

On Fri, Feb 21, 2020 at 02:35:12PM +0800, Yubo Miao wrote: > From: miaoyubo > > Currently, pxb-pcie could be defined by the cmdline like > --device pxb-pcie,id=pci.9,bus_nr=128 > However pxb-pcie is not described in acpi tables for arm. > > The formal two patches support pxb-pcie for arm, es

Re: [PULL 00/13] Linux user for 5.0 patches

On Thu, 20 Feb 2020 at 09:22, Laurent Vivier wrote: > > The following changes since commit 6c599282f8ab382fe59f03a6cae755b89561a7b3: > > Merge remote-tracking branch > 'remotes/armbru/tags/pull-monitor-2020-02-15-v2' into staging (2020-02-17 > 13:32:25 +) > > are available in the Git repos

[PATCH v4 3/4] qemu-img: allow qemu-img measure --object without a filename

In most qemu-img sub-commands the --object option only makes sense when there is a filename. qemu-img measure is an exception because objects may be referenced from the image creation options instead of an existing image file. Allow --object without a filename. Signed-off-by: Stefan Hajnoczi Re

[PATCH v4 2/4] luks: implement .bdrv_measure()

Add qemu-img measure support in the "luks" block driver. Signed-off-by: Stefan Hajnoczi Reviewed-by: Max Reitz --- block/crypto.c | 62 ++ 1 file changed, 62 insertions(+) diff --git a/block/crypto.c b/block/crypto.c index 24823835c1..23e9c74d6f

[PATCH v4 1/4] luks: extract qcrypto_block_calculate_payload_offset()

The qcow2 .bdrv_measure() code calculates the crypto payload offset. This logic really belongs in crypto/block.c where it can be reused by other image formats. The "luks" block driver will need this same logic in order to implement .bdrv_measure(), so extract the qcrypto_block_calculate_payload_of

[PATCH v4 0/4] luks: add qemu-img measure support

v4: * This revision is what German speakers call "das Tüpfelchen auf dem I". "The icing on the cake" is the English equivalent. Since I like cake and don't want it to be half-baked, and because I like my metaphors shaken, not stirred, I went ahead with the extra revision so I could writ

[PATCH v4 4/4] iotests: add 282 luks qemu-img measure test

This test exercises the block/crypto.c "luks" block driver .bdrv_measure() code. Signed-off-by: Stefan Hajnoczi Reviewed-by: Max Reitz --- tests/qemu-iotests/282 | 93 ++ tests/qemu-iotests/282.out | 30 tests/qemu-iotests/group | 1 + 3 f

Re: [PATCH v4] Implement the Screamer sound chip for the mac99 machine type

> On Feb 21, 2020, at 4:13 AM, Howard Spoelstra wrote: > > Hi, > > It might be worth mentioning that any testing of your screamer implementation > with MacOS/OSX guests on the mac99 machine needs a custom-built openbios. > > Where possible I'll compare your screamer with the current screamer

Re: [PATCH 2/2] vhost-use-blk: convert to new virtio_delete_queue

On Thu, Feb 13, 2020 at 09:28:07AM +0800, pannengy...@huawei.com wrote: > diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c > index 2eba8b9db0..ed6a5cc03b 100644 > --- a/hw/block/vhost-user-blk.c > +++ b/hw/block/vhost-user-blk.c > @@ -420,9 +420,10 @@ static void vhost_user_blk_de

Re: [PATCH 1/2] vhost-user-blk: delete virtioqueues in unrealize to fix memleaks

On Thu, Feb 13, 2020 at 09:28:06AM +0800, pannengy...@huawei.com wrote: > From: Pan Nengyuan > > virtio queues forgot to delete in unrealize, and aslo error path in > realize, this patch fix these memleaks, the leak stack is as follow: > > Direct leak of 114688 byte(s) in 16 object(s) allocated

Re: [PATCH] hw/char/pl011: Output characters using best-effort mode

On 21/02/20 11:21, Peter Maydell wrote: > Before you do that, I would suggest investigating: > * is this a problem we've already had on x86 and that there is a >standard solution for Disconnected sockets always lose data (see tcp_chr_write in chardev/char-socket.c). For connected sockets, 825

Re: [PATCH] tcg: gdbstub: Fix single-step issue on arm target

On Thu, Feb 20, 2020 at 10:24:37PM +0100, Luc Michel wrote: > I'm curious, I never experienced this behaviour from GDB. What GDB and > QEMU versions are you using? > > On my side (GDB 9.1), even without 'vContSupported+' in the 'qSupported' > answer, GDB sends a 'vCont?' packet on the first stepi:

Re: [PATCH] pcie_root_port: Add disable_hotplug option

On Tue, Feb 18, 2020 at 12:18:04PM -0500, Laine Stump wrote: > On 2/18/20 11:17 AM, Julia Suvorova wrote: > > Make hot-plug/hot-unplug on PCIe Root Ports optional to allow libvirt > > to manage it and restrict unplug for the entire machine. This is going > > to prevent user-initiated unplug in gues

[Bug 1863601] Re: unable to type "|" character in french keyboard.

Can you provide more information here. What command line have you launched QEMU with ? How are you interacting with QEMU (serial console, GTK UI, VNC, SPICE ?) If VNC/SPICE, what client app are you using ? -- You received this bug notification because you are a member of qemu- devel-ml, which i

Re: [PULL SUBSYSTEM qemu-pseries] pseries: Update SLOF firmware image

On Fri, Feb 21, 2020 at 03:09:46PM +1100, Alexey Kardashevskiy wrote: > > > On 18/02/2020 16:48, Philippe Mathieu-Daudé wrote: > > On 2/17/20 11:46 PM, David Gibson wrote: > >> On Mon, Feb 17, 2020 at 11:24:11AM +0100, Philippe Mathieu-Daudé wrote: > >>> On 2/17/20 10:26 AM, Philippe Mathieu-Daud

Re: [PATCH v4] Implement the Screamer sound chip for the mac99 machine type

On Fri, Feb 21, 2020 at 12:30 PM Programmingkid wrote: > > > On Feb 21, 2020, at 4:13 AM, Howard Spoelstra > wrote: > > > > Hi, > > > > It might be worth mentioning that any testing of your screamer > implementation with MacOS/OSX guests on the mac99 machine needs a > custom-built openbios. > >

Re: [PATCH v1 00/13] migrate/ram: Fix resizing RAM blocks while migrating

On 19.02.20 17:17, David Hildenbrand wrote: > This is the follow up of > "[PATCH RFC] memory: Don't allow to resize RAM while migrating" [1] > > This series contains some (slightly modified) patches also contained in: > "[PATCH v2 fixed 00/16] Ram blocks with resizable anonymous allocation

Re: [PATCH] tcg: gdbstub: Fix single-step issue on arm target

On 2/21/20 12:51 PM, Changbin Du wrote: On Thu, Feb 20, 2020 at 10:24:37PM +0100, Luc Michel wrote: I'm curious, I never experienced this behaviour from GDB. What GDB and QEMU versions are you using? On my side (GDB 9.1), even without 'vContSupported+' in the 'qSupported' answer, GDB sends a 'v

Re: Race condition in overlayed qcow2?

Vladimir Sementsov-Ogievskiy писал 2020-02-21 13:09: 21.02.2020 12:49, dovgaluk wrote: Vladimir Sementsov-Ogievskiy писал 2020-02-20 12:36: 1 or 2 are ok, and 4 or 8 lead to the failures. That is strange. I could think, that it was caused by the bugs in deterministic CPU execution, but the fi

Re: [PATCH v2] gdbstub: Fix single-step issue by confirming 'vContSupported+' feature to gdb

On 2/21/20 1:25 AM, Changbin Du wrote: > Recently when debugging an arm32 system on qemu, I found sometimes the > single-step command (stepi) is not working. This can be reproduced by > below steps: > 1) start qemu-system-arm -s -S .. and wait for gdb connection. > 2) start gdb and connect to qem

Re: [PATCH] hw/char/pl011: Output characters using best-effort mode

On Fri, 21 Feb 2020 at 11:44, Paolo Bonzini wrote: > > On 21/02/20 11:21, Peter Maydell wrote: > > Before you do that, I would suggest investigating: > > * is this a problem we've already had on x86 and that there is a > >standard solution for > Disconnected sockets always lose data (see tcp_

[Bug 1863601] Re: unable to type "|" character in french keyboard.

Hi Daniel, Thanks for your response. I am using virt-manager to start with to connect with VNC. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1863601 Title: unable to type "|" character in french k

Re: [PATCH 5/5] aio-posix: make AioHandler dispatch O(1) with epoll

On Wed, Feb 19, 2020 at 12:13:40PM +0100, Paolo Bonzini wrote: > On 14/02/20 18:17, Stefan Hajnoczi wrote: > > +while ((node = QLIST_FIRST(ready_list))) { > > +QLIST_SAFE_REMOVE(node, node_ready); > > Why does this need safe remove? Yes, it's necessary. QLIST_SAFE_REMOVE() has two pr

[Bug 1863601] Re: unable to type "|" character in french keyboard.

Can you provide the QEMU command line (/var/log/libvirt/qemu/$GUEST.log) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1863601 Title: unable to type "|" character in french keyboard. Status in QEM

Re: [PATCH 5/5] aio-posix: make AioHandler dispatch O(1) with epoll

On 21/02/20 13:59, Stefan Hajnoczi wrote: > 1. It doesn't crash if the node is currently not on a list. > 2. It clears the node's linked list pointers so that future linked >list operations (like QLIST_SAFE_REMOVE()) aren't accidentally >performed on stale pointers. > > The node has a long

[PULL 00/52] target-arm queue

/tags/linux-user-for-5.0-pull-request' into staging (2020-02-20 17:35:42 +) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200221 for you to fetch changes up to 270a679b3f950d7c4c600f324aab8bff292d0971: target/arm: A

[PULL 01/52] aspeed/scu: Create separate write callbacks

From: Joel Stanley This splits the common write callback into separate ast2400 and ast2500 implementations. This makes it clearer when implementing differing behaviour. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé M

[PULL 05/52] z2: Make providing flash images non-mandatory

From: Guenter Roeck Up to now, the z2 machine only boots if a flash image is provided. This is not really necessary; the machine can boot from initrd or from SD without it. At the same time, having to provide dummy flash images is a nuisance and does not add any real value. Make it optional. Sig

[PULL 03/52] hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register

From: Philippe Mathieu-Daudé Fix warning reported by Clang static code analyzer: CC hw/misc/iotkit-secctl.o hw/misc/iotkit-secctl.c:343:9: warning: Value stored to 'value' is never read value &= 0x00f000f3; ^~~ Fixes: b3717c23e1c Reported-by: Clang

[PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT

From: Richard Henderson Writes to AdvSIMD registers flush the bits above 128. Buglink: https://bugs.launchpad.net/bugs/1863247 Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-2-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/a

[PULL 02/52] aspeed/scu: Implement chip ID register

From: Joel Stanley This returns a fixed but non-zero value for the chip id. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200121013302.43839-3-j...@jms.id.au Signed-off-by: Peter Maydell --- hw/misc/a

[PULL 04/52] mainstone: Make providing flash images non-mandatory

From: Guenter Roeck Up to now, the mainstone machine only boots if two flash images are provided. This is not really necessary; the machine can boot from initrd or from SD without it. At the same time, having to provide dummy flash images is a nuisance and does not add any real value. Make it opt

[PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN

From: Richard Henderson Writes to AdvSIMD registers flush the bits above 128. Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-4-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 inser

[PULL 07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX

From: Richard Henderson Writes to AdvSIMD registers flush the bits above 128. Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-3-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 inser

[PULL 10/52] target/arm: Use bit 55 explicitly for pauth

From: Richard Henderson The psuedocode in aarch64/functions/pac/auth/Auth and aarch64/functions/pac/strip/Strip always uses bit 55 for extfield and do not consider if the current regime has 2 ranges. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Messa

[PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS

From: Richard Henderson Writes to AdvSIMD registers flush the bits above 128. Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-5-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 6 ++ 1 file changed, 6

[PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan

In take_aarch32_exception(), we know we are dealing with a CPU that has AArch32, so the right isar_feature test is aa32_pan, not aa64_pan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-3-peter.mayd...@linaro.org --- target/arm/helper.c | 2 +- 1 fil

[PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid

From: Richard Henderson For the purpose of rebuild_hflags_a64, we do not need to compute all of the va parameters, only tbi. Moreover, we can compute them in a form that is more useful to storing in hflags. This eliminates the need for aa64_va_parameter_both, so fold that in to aa64_va_paramete

[PULL 11/52] target/arm: Fix select for aa64_va_parameters_both

From: Richard Henderson Select should always be 0 for a regime with one range. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200216194343.21331-3-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 46 +++

[PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae

From: Richard Henderson Now that aa64_va_parameters_both sets select based on the number of ranges in the regime, the ttbr1_valid check is redundant. Signed-off-by: Richard Henderson Message-id: 20200216194343.21331-4-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter

[PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers

Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As

[PULL 18/52] target/arm: Factor out PMU register definitions

Pull the code that defines the various PMU registers out into its own function, matching the pattern we have already for the debug registers. Apart from one style fix to a multi-line comment, this is purely movement of code with no changes to it. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by:

[PULL 19/52] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1

Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them where we currently have hard-coded bit values. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-7-peter.mayd...@linaro.org --- target/arm/cpu.h| 10 ++

[PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions

Our current usage of the isar_feature feature tests almost always uses an _aa32_ test when the code path is known to be AArch32 specific and an _aa64_ test when the code path is known to be AArch64 specific. There is just one exception: in the vfp_set_fpscr helper we check aa64_fp16 to determine wh

[PULL 21/52] target/arm: Define an aa32_pmu_8_1 isar feature test function

Instead of open-coding a check on the ID_DFR0 PerfMon ID register field, create a standardly-named isar_feature for "does AArch32 have a v8.1 PMUv3" and use it. This entails moving the id_dfr0 field into the ARMISARegisters struct. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Mes

[PULL 23/52] target/arm: Stop assuming DBGDIDR always exists

The AArch32 DBGDIDR defines properties like the number of breakpoints, watchpoints and context-matching comparators. On an AArch64 CPU, the register may not even exist if AArch32 is not supported at EL1. Currently we hard-code use of DBGDIDR to identify the number of breakpoints etc; this works f

[PULL 30/52] target/arm: Correct handling of PMCR_EL0.LC bit

The LC bit in the PMCR_EL0 register is supposed to be: * read/write * RES1 on an AArch64-only implementation * an architecturally UNKNOWN value on reset (and use of LC==0 by software is deprecated). We were implementing it incorrectly as read-only always zero, though we do have all the code nee

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