[PATCH v3 02/17] s390x: Add missing vcpu reset functions

Up to now we only had an ioctl to reset vcpu data QEMU couldn't reach for the initial reset, which was also called for the clear reset. To be architecture compliant, we also need to clear local interrupts on a normal reset. Because of this and the upcoming protvirt support we need to add ioctls fo

[PATCH v3 07/17] s390x: protvirt: Handle diag 308 subcodes 0,1,3,4

As we now have access to the protection state of the cpus, we can implement special handling of diag 308 subcodes for cpus in the protected state. For subcodes 0 and 1 we need to unshare all pages before continuing, so the guest doesn't accidentally expose data when dumping. For subcode 3/4 we te

[PATCH v3 08/17] s390x: protvirt: KVM intercept changes

Secure guests no longer intercept with code 4 for an instruction interception. Instead they have codes 104 and 108 for secure instruction interception and secure instruction notification respectively. The 104 mirrors the 4 interception. The 108 is a notification interception to let KVM and QEMU k

[PATCH v3 00/17] s390x: Protected Virtualization support

Most of the QEMU changes for PV are related to the new IPL type with subcodes 8 - 10 and the execution of the necessary Ultravisor calls to IPL secure guests. Note that we can only boot into secure mode from normal mode, i.e. stfle 161 is not active in secure mode. The other changes related to dat

[PATCH v3 01/17] Header sync

Sync in the new vcpu resets. --- linux-headers/linux/kvm.h | 4 1 file changed, 4 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 9d647fad76..ec146bd52a 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1009,6 +1009,7 @@ struct

[PATCH v3 05/17] s390x: protvirt: Support unpack facility

When a guest has saved a ipib of type 5 and call diagnose308 with subcode 10, we have to setup the protected processing environment via Ultravisor calls. The calls are done by KVM and are exposed via an API. The following steps are necessary: 1. Create a VM (register it with the Ultravisor) 2. Cre

[PATCH v3 03/17] Sync pv

Signed-off-by: Janosch Frank --- linux-headers/linux/kvm.h | 37 + 1 file changed, 37 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index ec146bd52a..e5ad5f9c4d 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux

[PATCH v3 12/17] s390x: protvirt: Set guest IPL PSW

Handling of CPU reset and setting of the IPL psw from guest storage at offset 0 is done by a Ultravisor call. Let's only fetch it if necessary. Signed-off-by: Janosch Frank Reviewed-by: Thomas Huth --- hw/s390x/pv.c | 6 ++ hw/s390x/pv.h | 2 ++ linux-headers/linux

[PATCH v3 10/17] s390x: Add SIDA memory ops

Protected guests save the instruction control blocks in the SIDA instead of QEMU/KVM directly accessing the guest's memory. Let's introduce new functions to access the SIDA. Signed-off-by: Janosch Frank --- linux-headers/linux/kvm.h | 6 +- target/s390x/cpu.h| 7 ++- target/s3

[PATCH v3 09/17] s390: protvirt: Move STSI data over SIDAD

For protected guests, we need to put the STSI emulation results into the SIDA, so SIE will write them into the guest at the next entry. Signed-off-by: Janosch Frank --- target/s390x/kvm.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target/s390x/kvm.c b/ta

[PATCH v3 04/17] s390x: protvirt: Add diag308 subcodes 8 - 10

For diag308 subcodes 8 - 10 we have a new ipib of type 5. The ipib holds the address and length of the secure execution header, as well as a list of guest components. Each component is a block of memory, for example kernel or initrd, which needs to be decrypted by the Ultravisor in order to run a

[PATCH v3 16/17] s390x: protvirt: Handle SIGP store status correctly

Status storing is not done by QEMU anymore, but is handled by SIE. Signed-off-by: Janosch Frank Reviewed-by: Thomas Huth --- target/s390x/helper.c | 4 target/s390x/sigp.c | 1 + 2 files changed, 5 insertions(+) diff --git a/target/s390x/helper.c b/target/s390x/helper.c index a3a49164e4

[PATCH v3 13/17] s390x: protvirt: Move diag 308 data over SIDAD

For protected guests the IPIB is written/read to/from the satellite block, so we need to make those accesses virtual to make them go through KVM mem ops. Signed-off-by: Janosch Frank --- target/s390x/diag.c | 32 +--- 1 file changed, 25 insertions(+), 7 deletions(-)

[PATCH v3 11/17] s390x: protvirt: SCLP interpretation

SCLP for a protected guest is done over the SIDAD, so we need to use the s390_cpu_virt_mem_* functions to access the SIDAD instead of guest memory when reading/writing SCBs. To not confuse the sclp emulation, we set 0x4000 as the SCCB address, since the function that injects the sclp external inte

[PATCH v3 15/17] s390x: protvirt: Move IO control structures over SIDA

For protected guests, we need to put the IO emulation results into the SIDA, so SIE will write them into the guest at the next entry. Signed-off-by: Janosch Frank --- target/s390x/ioinst.c | 87 ++- 1 file changed, 61 insertions(+), 26 deletions(-) diff -

[PATCH v3 14/17] s390x: protvirt: Disable address checks for PV guest IO emulation

IO instruction data is routed through SIDAD for protected guests, so adresses do not need to be checked, as this is kernel memory. Signed-off-by: Janosch Frank Reviewed-by: Thomas Huth --- target/s390x/ioinst.c | 26 +++--- 1 file changed, 19 insertions(+), 7 deletions(-) d

[PATCH v3 17/17] s390x: For now add unpack feature to GA1

Signed-off-by: Janosch Frank --- target/s390x/gen-features.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c index 6278845b12..8ddeebc544 100644 --- a/target/s390x/gen-features.c +++ b/target/s390x/gen-features.c @@ -562,6 +562,7 @@ st

Re: [PATCH] qapi: Expand documentation for LostTickPolicy

Andrea Bolognani writes: > The current documentation is fairly terse and not easy to decode > for someone who's not intimately familiar with the inner workings > of timer devices. Expand on it by providing a somewhat verbose > description of what behavior each policy will result in, as seen > fro

[PATCH v3 06/17] s390x: protvirt: Add migration blocker

Migration is not yet supported. Signed-off-by: Janosch Frank --- hw/s390x/s390-virtio-ccw.c | 16 1 file changed, 16 insertions(+) diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 5fa4372083..d64724af91 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/

Re: [PATCH v2 18/30] qapi: Delete all the "foo: dropped in n.n" notes

On Fri, 14 Feb 2020 at 15:13, Markus Armbruster wrote: > > Markus Armbruster writes: > > > Peter Maydell writes: > > > >> A handful of QAPI doc comments include lines like > >> "ppcemb: dropped in 3.1". The doc comment parser will just > >> put these into whatever the preceding section was; some

Re: [PATCH] accel/tcg: fix race in cpu_exec_step_atomic (bug 1863025)

On 14/02/20 15:49, Alex Bennée wrote: > The bug describes a race whereby cpu_exec_step_atomic can acquire a TB > which is invalidated by a tb_flush before we execute it. This doesn't > affect the other cpu_exec modes as a tb_flush by it's nature can only > occur on a quiescent system. The race was

Re: [PATCH v6 5/8] multifd: Add zlib compression multifd support

* Juan Quintela (quint...@redhat.com) wrote: > Signed-off-by: Juan Quintela > Acked-by: Markus Armbruster Reviewed-by: Dr. David Alan Gilbert > --- > hw/core/qdev-properties.c| 2 +- > migration/Makefile.objs | 1 + > migration/multifd-zlib.c | 325 +++

Re: [PATCH v2] Report stringified errno in VFIO related errors

On Fri, 14 Feb 2020 10:55:19 +0100 Michal Privoznik wrote: > In a few places we report errno formatted as a negative integer. > This is not as user friendly as it can be. Use strerror() and/or > error_setg_errno() instead. > > Signed-off-by: Michal Privoznik > --- > > v1 posted here: > > http

Re: [PATCH v2 15/30] qapi/{block, misc, tmp, net}.json: Use explicit bulleted lists

Peter Maydell writes: > On Fri, 14 Feb 2020 at 14:23, Markus Armbruster wrote: >> What's the rationale for the split between >> >> [PATCH v2 13/30] qapi/block-core.json: Use explicit bulleted lists >> [PATCH v2 14/30] qapi/ui.json: Use explicit bulleted lists >> [PATCH v2 15/30] qapi

Re: [PATCH] ppc: free 'fdt' after reset the machine

On Fri, 14 Feb 2020 11:32:06 +0800 wrote: > From: Pan Nengyuan > > 'fdt' forgot to clean both e500 and pnv when we call 'system_reset' on ppc, > this patch fix it. The leak stacks are as follow: > > Direct leak of 4194304 byte(s) in 4 object(s) allocated from: > #0 0x7fafe37dd970 in __inte

Re: [PATCH v2 15/30] qapi/{block, misc, tmp, net}.json: Use explicit bulleted lists

On Fri, 14 Feb 2020 at 15:46, Markus Armbruster wrote: > > Peter Maydell writes: > > > On Fri, 14 Feb 2020 at 14:23, Markus Armbruster wrote: > >> What's the rationale for the split between > >> > >> [PATCH v2 13/30] qapi/block-core.json: Use explicit bulleted lists > >> [PATCH v2 14/30]

Re: [PATCH] Report stringified errno in VFIO related errors

On Fri, 14 Feb 2020 10:19:50 +0100 Michal Privoznik wrote: > On 2/14/20 9:47 AM, Michal Privoznik wrote: > > In a few places we report errno formatted as a negative integer. > > This is not as user friendly as it can be. Use strerror() and/or > > error_setg_errno() instead. > > > > Signed-off-by

Re: [PATCH RFC] memory: Don't allow to resize RAM while migrating

On Fri, Feb 14, 2020 at 10:17:07AM +0100, David Hildenbrand wrote: > On 13.02.20 21:56, Peter Xu wrote: > > On Thu, Feb 13, 2020 at 08:42:23PM +0100, David Hildenbrand wrote: > >> On 13.02.20 19:32, Peter Xu wrote: > >>> On Thu, Feb 13, 2020 at 06:20:16PM +0100, David Hildenbrand wrote: > Resi

[PATCH v2] target/ppc: Fix typo in comments

"Deferred" was misspelled as "differed" in some comments, correct this typo, Signed-off-by: BALATON Zoltan --- v2: Found one more where even the typo was misspelled target/ppc/fpu_helper.c| 4 ++-- target/ppc/translate/fp-impl.inc.c | 6 +++--- 2 files changed, 5 insertions(+), 5 del

Re: [PATCH v2 16/30] qapi: Add blank lines before bulleted lists

Markus Armbruster writes: > Peter Maydell writes: > >> rST insists on a blank line before and after a bulleted list, >> but our texinfo doc generator did not. Add some extra blank >> lines in the doc comments so they're acceptable rST input. >> >> Signed-off-by: Peter Maydell >> Reviewed-by: Ph

Re: [PATCH v2 16/30] qapi: Add blank lines before bulleted lists

On Fri, 14 Feb 2020 at 16:02, Markus Armbruster wrote: > > Markus Armbruster writes: > > > Peter Maydell writes: > > > >> rST insists on a blank line before and after a bulleted list, > >> but our texinfo doc generator did not. Add some extra blank > >> lines in the doc comments so they're accep

Re: [PATCH v4 03/20] target/arm: Add isar_feature tests for PAN + ATS1E1

On Fri, 14 Feb 2020 at 11:28, Peter Maydell wrote: > > On Sat, 8 Feb 2020 at 12:58, Richard Henderson > wrote: > > > > Include definitions for all of the bits in ID_MMFR3. > > We already have a definition for ID_AA64MMFR1.PAN. > > > > Reviewed-by: Alex Bennée > > Reviewed-by: Peter Maydell > >

Re: [PATCH] Report stringified errno in VFIO related errors

On 2/14/20 4:49 PM, Alex Williamson wrote: On Fri, 14 Feb 2020 10:19:50 +0100 Michal Privoznik wrote: Do you guys want me to file a bug? Probably a good idea. Thanks, Since I'm reproducing this against upstream, I've reported it here: https://bugs.launchpad.net/qemu/+bug/186 Michal

Re: How do UEFI on Windows host

On 02/12/20 21:23, Jerry Geis wrote: > How do I start a UEFI install (centos 8) for UEFI with 4.2.0 on Windows > host ??? > I can do a regular install just fine. I desire to do UEFI install. What is the list of files contained in the qemu-on-windows installer? I looked for a manifest at

[Bug 1863333] [NEW] Assigning NVMe disk to a domain causes VFIO_MAP_DMA errors

Public bug reported: I'm seeing some errors when assigning my NVMe disk to qemu. This is the full command line: /home/zippy/work/qemu/qemu.git/x86_64-softmmu/qemu-system-x86_64 \ -name guest=fedora,debug-threads=on \ -S \ -object secret,id=masterKey0,format=raw,file=/var/lib/libvirt/qemu/domain

Re: [PATCH RFC 06/14] migration/rdma: Transmit initial packet

* Zhimin Feng (fengzhim...@huawei.com) wrote: > Transmit initial packet through the multifd RDMA channels, > so that we can identify the multifd channels. > > Signed-off-by: Zhimin Feng > --- > migration/multifd.c | 33 + > migration/rdma.c| 2 ++ > 2 files c

Re: [PATCH v3 00/17] s390x: Protected Virtualization support

Patchew URL: https://patchew.org/QEMU/20200214151636.8764-1-fran...@linux.ibm.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v3 00/17] s390x: Protected Virtualization support Message-id: 20200214151636.8764-1-fran...@linux

Re: How do UEFI on Windows host

I dont know how to get all files listing on windows. But, I cd \program files\qemu dir *.fd edk2-x86_64-code.fd edk2-x86_64-secure-code.fd It seems like from other posts these might be the files - but still not sure how to do "boot" a command line for UEFI. Jerry

Re: [PULL 00/46] target-arm queue

On Thu, 13 Feb 2020 at 14:41, Peter Maydell wrote: > > Big pullreq this week, since it's got RTH's PAN/UAO/ATS1E1 > implementation in it, and also Philippe's raspi board model > cleanup patchset, as well as a scattering of smaller stuff. > > -- PMM > > > The following changes since commit 7ce9ce89

Re: [PATCH RFC] memory: Don't allow to resize RAM while migrating

>> a) In precopy during the second migration. >> b) In postcopy during the first migration. > > After reading your reply - even the 1st migration of precopy? Say, > when source QEMU resets and found changed FW during the precopy? I think the FW will only change during migration (depends on the o

Re: [PATCH v2] Report stringified errno in VFIO related errors

Le 14/02/2020 à 16:35, Alex Williamson a écrit : > On Fri, 14 Feb 2020 10:55:19 +0100 > Michal Privoznik wrote: > >> In a few places we report errno formatted as a negative integer. >> This is not as user friendly as it can be. Use strerror() and/or >> error_setg_errno() instead. >> >> Signed-off

Re: [PATCH v1 08/14] tests/vm: Added configuration file support

Robert Foley writes: > Changes to tests/vm/basevm.py to allow accepting a configuration file > as a parameter. Allows for specifying VM options such as > cpu, machine, memory, and arbitrary qemu arguments for specifying options > such as NUMA configuration. > Also added an example conf_example_

Re: [PATCH v2 16/30] qapi: Add blank lines before bulleted lists

Peter Maydell writes: > On Fri, 14 Feb 2020 at 16:02, Markus Armbruster wrote: >> >> Markus Armbruster writes: >> >> > Peter Maydell writes: >> > >> >> rST insists on a blank line before and after a bulleted list, >> >> but our texinfo doc generator did not. Add some extra blank >> >> lines in

[PATCH 0/5] aio-posix: towards an O(1) event loop

This patch series makes AioHandler deletion and dispatch O(1) with respect to the total number of registered handlers. The event loop has scalability problems when many AioHandlers are registered because it is O(n). Linux epoll(7) is used to avoid scanning over all pollfds but parts of the code s

[PATCH 2/5] aio-posix: don't pass ns timeout to epoll_wait()

Don't pass the nanosecond timeout into epoll_wait(), which expects milliseconds. The epoll_wait() timeout value does not matter if qemu_poll_ns() determined that the poll fd is ready, but passing a value in the wrong units is still ugly. Pass a 0 timeout to epoll_wait() instead. Signed-off-by: S

[PATCH 4/5] aio-posix: make AioHandler deletion O(1)

It is not necessary to scan all AioHandlers for deletion. Keep a list of deleted handlers instead of scanning the full list of all handlers. The AioHandler->deleted field can be dropped. Let's check if the handler has been inserted into the deleted list instead. Add a new QLIST_IS_INSERTED() AP

Re: [PATCH v2 01/30] configure: Allow user to specify sphinx-build binary

Peter Maydell writes: > On Fri, 14 Feb 2020 at 12:20, Markus Armbruster wrote: >> >> Peter Maydell writes: >> >> # Default objcc to clang if available, otherwise use CC >> >> @@ -4803,7 +4816,7 @@ has_sphinx_build() { >> >> # sphinx-build doesn't exist at all or if it is too old. >> >>

[PATCH 1/5] aio-posix: fix use after leaving scope in aio_poll()

epoll_handler is a stack variable and must not be accessed after it goes out of scope: if (aio_epoll_check_poll(ctx, pollfds, npfd, timeout)) { AioHandler epoll_handler; ... add_pollfd(&epoll_handler); ret = aio_epoll(ctx, pollfds, npfd, timeout);

[PATCH 3/5] qemu/queue.h: add QLIST_SAFE_REMOVE()

QLIST_REMOVE() assumes the element is in a list. It also leaves the element's linked list pointers dangling. Introduce a safe version of QLIST_REMOVE() and convert open-coded instances of this pattern. Signed-off-by: Stefan Hajnoczi --- block.c | 5 + chardev/spice.c |

[PATCH 5/5] aio-posix: make AioHandler dispatch O(1) with epoll

File descriptor monitoring is O(1) with epoll(7), but aio_dispatch_handlers() still scans all AioHandlers instead of dispatching just those that are ready. This makes aio_poll() O(n) with respect to the total number of registered handlers. Add a local ready_list to aio_poll() so that each nested

Re: [PATCH RFC] memory: Don't allow to resize RAM while migrating

On Fri, Feb 14, 2020 at 01:02:46PM +0100, David Hildenbrand wrote: > From c0049ac2e95d6756037db918852c507fb88297d9 Mon Sep 17 00:00:00 2001 > From: David Hildenbrand > Date: Fri, 14 Feb 2020 13:01:03 +0100 > Subject: [PATCH v1] tmp > > Signed-off-by: David Hildenbrand > --- > migration/migratio

Re: [PATCH RFC] memory: Don't allow to resize RAM while migrating

On 14.02.20 18:29, Peter Xu wrote: > On Fri, Feb 14, 2020 at 01:02:46PM +0100, David Hildenbrand wrote: >> From c0049ac2e95d6756037db918852c507fb88297d9 Mon Sep 17 00:00:00 2001 >> From: David Hildenbrand >> Date: Fri, 14 Feb 2020 13:01:03 +0100 >> Subject: [PATCH v1] tmp >> >> Signed-off-by: Davi

Re: [PATCH v2 01/30] configure: Allow user to specify sphinx-build binary

On Fri, 14 Feb 2020 at 17:18, Markus Armbruster wrote: > I decided I prefer this as a separate patch, between PATCH 01 and 02. > > Hmm, maybe I should squash the last hunk into PATCH 01. > > > From 10d174a9f811708807fb60a610e88084f282c222 Mon Sep 17 00:00:00 2001 > From: Markus Armbruster > Date:

[PATCH v2 00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2

This patchset implements the ARMv8.1-PMU and ARMv8.4-PMU architecture extensions. These are fairly small changes on top of the basic PMUv3 we already implement, and in fact we already had most of the v8.1-PMU functionality implemented but unadvertised. In the course of doing this, I found that o

[PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers

Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As

[PATCH v2 03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions

Our current usage of the isar_feature feature tests almost always uses an _aa32_ test when the code path is known to be AArch32 specific and an _aa64_ test when the code path is known to be AArch64 specific. There is just one exception: in the vfp_set_fpscr helper we check aa64_fp16 to determine wh

[PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists

The AArch32 DBGDIDR defines properties like the number of breakpoints, watchpoints and context-matching comparators. On an AArch64 CPU, the register may not even exist if AArch32 is not supported at EL1. Currently we hard-code use of DBGDIDR to identify the number of breakpoints etc; this works f

[PATCH v2 05/21] target/arm: Factor out PMU register definitions

Pull the code that defines the various PMU registers out into its own function, matching the pattern we have already for the debug registers. Apart from one style fix to a multi-line comment, this is purely movement of code with no changes to it. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by:

[PATCH v2 02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan

In take_aarch32_exception(), we know we are dealing with a CPU that has AArch32, so the right isar_feature test is aa32_pan, not aa64_pan. Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/hel

[PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks

Add the 64-bit version of the "is this a v8.1 PMUv3?" ID register check function, and the _any_ version that checks for either AArch32 or AArch64 support. We'll use this in a later commit. We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1, but we move id_aa64dfr1 into the ARMISARegister

[PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension

The ARMv8.1-PMU extension requires: * the evtCount field in PMETYPER_EL0 is 16 bits, not 10 * MDCR_EL2.HPMD allows event counting to be disabled at EL2 * two new required events, STALL_FRONTEND and STALL_BACKEND * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0 We already implement the 16-bit

[PATCH v2 04/21] target/arm: Define and use any_predinv isar_feature test

Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv", define and use an any_predinv isar_feature test function. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h| 5 + target/arm/helper.c | 9 +-

[PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks

The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions are supposed to be testing fields in ID_MMFR3; but a cut-and-paste error meant we were looking at MVFR0 instead. Fix the functions to look at the right register; this requires us to move at least id_mmfr3 to the ARMISARegisters struc

[PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters

We're going to want to read the DBGDIDR register from KVM in a subsequent commit, which means it needs to be in the ARMISARegisters sub-struct. Move it. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- target/arm/internals.h | 6 +++--- target/arm/cpu.c | 8 target/

[PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field

We already define FIELD macros for ID_DFR0, so use them in the one place where we're doing direct bit value manipulation. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- We have lots of this non-FIELD style in the code, of course; I change thi

[PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM

Now we have isar_feature test functions that look at fields in the ID_AA64DFR0_EL1 and ID_DFR0 ID registers, add the code that reads these register values from KVM so that the checks behave correctly when we're using KVM. No isar_feature function tests ID_AA64DFR1_EL1 or DBGDIDR yet, but we add it

Re: [PULL 0/5] Linux user for 5.0 patches

On Thu, 13 Feb 2020 at 12:22, Laurent Vivier wrote: > > The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730: > > Merge remote-tracking branch > 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging > (2020-02-10 18:09:14 +) > > are available in the Git

[PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1

Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them where we currently have hard-coded bit values. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use FIELD_EX64/FIELD_DP64 for 64-bit ID register --- target/arm/cpu.h| 10

[PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max'

Set the ID register bits to provide ARMv8.4-PMU (and implicitly also ARMv8.1-PMU) in the 'max' CPU. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: use FIELD_DP64 for 64-bit idreg --- target/arm/cpu64.c | 8 1 file changed, 8 insertions(+) diff --git a/target/a

[PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function

Instead of open-coding a check on the ID_DFR0 PerfMon ID register field, create a standardly-named isar_feature for "does AArch32 have a v8.1 PMUv3" and use it. This entails moving the id_dfr0 field into the ARMISARegisters struct. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell ---

[PATCH v2 16/21] target/arm: Correct definition of PMCRDP

The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'. Correct our #define of PMCRDP and add the missing PMCRX. We do have the correct behaviour for handling the DP bit being set, so this fixes a guest-visible bug. Fixes: 033614c47de Reviewed-by: Philippe Mathieu-Daudé Reviewed-by:

[Bug 1863247] Re: AArch64 EXT instruction for V register does not clear MSB side bits

Yep. ** Changed in: qemu Status: New => In Progress ** Changed in: qemu Assignee: (unassigned) => Richard Henderson (rth) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1863247 Title:

Re: [PATCH v1 08/14] tests/vm: Added configuration file support

On Fri, 14 Feb 2020 at 11:54, Alex Bennée wrote: > > from socket_thread import SocketThread > > +import yaml > > So this throws my setup on my Gentoo SynQuacer. Is this meant to be in > the standard library or is this a separate dependency? > This is a separate dependency. On Ubuntu the package

[PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit

The LC bit in the PMCR_EL0 register is supposed to be: * read/write * RES1 on an AArch64-only implementation * an architecturally UNKNOWN value on reset (and use of LC==0 by software is deprecated). We were implementing it incorrectly as read-only always zero, though we do have all the code nee

[PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension

The ARMv8.4-PMU extension adds: * one new required event, STALL * one new system register PMMIR_EL1 (There are also some more L1-cache related events, but since we don't implement any cache we don't provide these, in the same way we don't provide the base-PMUv3 cache events.) The STALL event "c

[PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields

Cut-and-paste errors mean we're using FIELD_EX64() to extract fields from some 32-bit ID register fields. Use FIELD_EX32() instead. (This makes no difference in behaviour, it's just more consistent.) Signed-off-by: Peter Maydell --- target/arm/cpu.h | 18 +- 1 file changed, 9 ins

[PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature

Now we have moved ID_MMFR4 into the ARMISARegisters struct, we can define and use an isar_feature for the presence of the ARMv8.2-AA32HPD feature, rather than open-coding the test. While we're here, correct a comment typo which missed an 'A' from the feature name. Signed-off-by: Peter Maydell --

[PATCH v2 21/21] target/arm: Correctly implement ACTLR2, HACTLR2

The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7 or the original ARMv8. They were later added as optional registers, whose presence is signaled by the ID_MMFR4.AC2 field. From ARMv8.2 they are mandatory (ie ID_MMFR4.AC2 must be non-zero). We implemented HACTLR2 in commit 0e0

Re: [PATCH RFC] memory: Don't allow to resize RAM while migrating

On Fri, Feb 14, 2020 at 06:32:35PM +0100, David Hildenbrand wrote: > On 14.02.20 18:29, Peter Xu wrote: > > On Fri, Feb 14, 2020 at 01:02:46PM +0100, David Hildenbrand wrote: > >> From c0049ac2e95d6756037db918852c507fb88297d9 Mon Sep 17 00:00:00 2001 > >> From: David Hildenbrand > >> Date: Fri, 14

Re: How do UEFI on Windows host

On 2/14/20 5:37 PM, Jerry Geis wrote: I dont know how to get all files listing on windows. But, I cd \program files\qemu dir *.fd edk2-x86_64-code.fd edk2-x86_64-secure-code.fd It seems like from other posts these might be the files - but still not sure how to do "boot" a command line for UEFI

[PATCH 12/19] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn

We now have proper ISA checks within each trans_* function. Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 1 file changed, 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0da780102c..e8c3d4f26f 100644 --- a/target/arm/translate.c +++ b/ta

[PATCH 01/19] target/arm: Fix field extract from MVFR[0-2]

These registers are 32-bits wide. Cut and paste used FIELD_EX64 instead of the more proper FIELD_EX32. In practice all this did was use an unnecessary 64-bit operation, producing correct results. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 18 +- 1 file changed, 9 i

[PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}

We will shortly use these to test for VFPv2 and VFPv3 in different situations. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5f08cbd2d8..4ff28418df 100644 --- a/target/arm/cp

[PATCH 00/19] target/arm: vfp feature and decodetree cleanup

The main goal of the patchset is to move the ARM_FEATURE_VFP test from outside of the disas_vfp_insn() to inside each of the trans_* functions, so that we get the proper ISA check for each case. At the end of that, it is easy to eliminate all of the remaining tests vs ARM_FEATURE_VFP* in favor of

[PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32

The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/translate-vfp.inc.c | 52 +- 2 files changed, 27 insertions(+), 27 deletions(-) diff --

[PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places

Many uses of ARM_FEATURE_VFP3 are testing for the number of simd registers implemented. Use the proper test vs MVCR0.SIMDReg. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 9 - target/arm/helper.c| 13 ++--- target/arm/translate.c | 2 +- 3 files changed, 1

[PATCH 11/19] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac

All remaining tests for VFP4 are for fused multiply-add insns. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/translate-vfp.inc.c | 12 target/arm/translate.c | 2 +- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a

[PATCH 16/19] target/arm: Remove ARM_FEATURE_VFP*

We have converted all tests against these features to ISAR tests. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 --- target/arm/cpu.c | 25 - target/arm/cpu64.c | 3 --- target/arm/kvm32.c | 5 - target/arm/kvm64.c | 1 - 5 files changed, 37 deleti

Re: [PATCH] spapr: Rework hash<->radix transitions at CAS

On Fri, 14 Feb 2020 09:28:35 +1100 David Gibson wrote: > On Thu, Feb 13, 2020 at 04:38:38PM +0100, Greg Kurz wrote: > > Until the CAS negotiation is over, an HPT can be allocated on three > > different paths: > > > > 1) during machine reset if the host doesn't support radix, > > > > 2) during C

[PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus

We are going to convert FEATURE tests to ISAR tests, so FPSP needs to be set for these cpus, like we have already for FPDP. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c ind

[PATCH 08/19] target/arm: Perform fpdp_v2 check first

Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 143 + 1 file changed, 72 insertions(+), 71 deletions(-) diff --git a/targe

[PATCH 15/19] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP

Use isar feature tests instead of feature bit tests. Although none of QEMUs current cpus have VFPv3 without D32, replace the large comment explaining why with one line that sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. Mirror the test sequence used in the linux kernel. Signed-off-by:

[PATCH 13/19] target/arm: Move VLLDM and VLSTM to vfp.decode

Now that we no longer have an early check for ARM_FEATURE_VFP, we can use the proper ISA check in trans_VLLDM_VLSTM. Signed-off-by: Richard Henderson --- target/arm/vfp.decode | 2 ++ target/arm/translate-vfp.inc.c | 35 ++ target/arm/translate.c | 53 ++

[PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2

The old name, isar_feature_aa32_fpdp, does not reflect that the test includes VFPv2. We will introduce another feature tests for VFPv3. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/translate-vfp.inc.c | 40 +- 2 files

Re: [PATCH v2 09/19] tracing: only allow -trace to override -D if set

On Thu, 13 Feb 2020 at 17:51, Alex Bennée wrote: > > Otherwise any -D settings the user may have made get ignored. > > Signed-off-by: Alex Bennée Reviewed-by: Robert Foley

[PATCH 05/19] target/arm: Add isar_feature_aa32_simd_r16

Use this in the places that were checking ARM_FEATURE_VFP, and are obviously testing for the existance of the register set as opposed to testing for some particular instruction extension. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 6 ++ hw/intc/armv7m_nvic.c | 20 +

[PATCH 18/19] target/arm: Split VFM decode

Passing the raw o1 and o2 fields from the manual is less instructive than it might be. Do the full decode and let the trans_* functions pass in booleans to a helper. Signed-off-by: Richard Henderson --- target/arm/vfp.decode | 17 +-- target/arm/translate-vfp.inc.c | 52 +++

[PATCH 17/19] target/arm: Add formats for some vfp 2 and 3-register insns

Those vfp instructions without extra opcode fields can share a common @format for brevity. Signed-off-by: Richard Henderson --- target/arm/vfp.decode | 134 -- 1 file changed, 52 insertions(+), 82 deletions(-) diff --git a/target/arm/vfp.decode b/target/a

[PATCH 09/19] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3

Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 24 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/ta

[PATCH 10/19] target/arm: Add missing checks for fpsp_v2

We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 78 ++ 1 file changed, 69 insertions(+), 9 deletions(

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