On Fri, 14 Feb 2020 at 11:28, Peter Maydell <peter.mayd...@linaro.org> wrote:
>
> On Sat, 8 Feb 2020 at 12:58, Richard Henderson
> <richard.hender...@linaro.org> wrote:
> >
> > Include definitions for all of the bits in ID_MMFR3.
> > We already have a definition for ID_AA64MMFR1.PAN.
> >
> > Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
> > Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
> > Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
>
>
> > @@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const
> > ARMISARegisters *id)
> > return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
> > }
> >
> > +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
> > +{
> > + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
> > +}
> > +
> > +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
> > +{
> > + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
> > +}
>
> Didn't spot this before it hit master, but these feature
> test functions are looking at id->mvfr0, which is MVFR0, not
> MMFR3 !
>
> Also they're using FIELD_EX64 on a 32-bit register: is there
> a reason for that?
I've been fiddling with the ID register stuff anyway,
so I've written a patch that addresses these things.
Due out in v2 of my PMU patchset.
thanks
-- PMM
