On Wed, Jan 15, 2020 at 09:57:04PM -0500, Raphael Norwitz wrote:
> The current vhost_user_set_mem_table_postcopy() implementation
> populates each region of the VHOST_USER_SET_MEM_TABLE message without
> first checking if there are more than VHOST_MEMORY_MAX_NREGIONS already
> populated. This can c
On 06/02/2020 00.20, Laurent Vivier wrote:
> When PHB4 bridge has been added, the dependencies to PCIE_PORT has been
> added to XIVE_SPAPR and indirectly to PSERIES.
> The build of the PowerNV machine is fine while we also build the PSERIES
> machine.
> If we disable the PSERIES machine, the PowerN
On Thu, Feb 06, 2020 at 03:17:04AM -0500, Michael S. Tsirkin wrote:
> On Wed, Jan 15, 2020 at 09:57:04PM -0500, Raphael Norwitz wrote:
> > The current vhost_user_set_mem_table_postcopy() implementation
> > populates each region of the VHOST_USER_SET_MEM_TABLE message without
> > first checking if t
On Wed, Jan 15, 2020 at 09:57:05PM -0500, Raphael Norwitz wrote:
> vhost_user_set_mem_table() and vhost_user_set_mem_table_postcopy() have
> gotten convoluted, and have some identical code.
>
> This change moves the logic populating the VhostUserMemory struct and
> fds array from vhost_user_set_me
On 06/02/2020 05.07, kuhn.chen...@huawei.com wrote:
> From: Chen Qun
>
> Fix warning:
> hw/i2c/aspeed_i2c.c: In function ‘aspeed_i2c_bus_write’:
> glib/glib-autocleanups.h:28:3: warning: ‘cmd_flags’ may be
> used uninitialized in this function [-Wmaybe-uninitialized]
>g_free (*pp);
>^
On Thu, 2020-02-06 at 08:43 +0100, Gerd Hoffmann wrote:
> The only difference to hardware revision 4 is that the device doesn't
> switch to VGA mode in case someone happens to touch a VGA register,
> which should make things more robust in configurations with multiple
> vga devices.
>
> Swtiching
On 05/02/20 07:06, David Gibson wrote:
> On Tue, Feb 04, 2020 at 12:26:32AM +0100, Paolo Bonzini wrote:
>> Il mar 4 feb 2020, 00:20 Alexey Kardashevskiy ha scritto:
>>> Speaking seriously, what would I put into the guest?
>>
>> Only things that would be considered drivers. Ignore the partitions is
On 05/02/20 06:58, David Gibson wrote:
>> Yes, SLOF is big and slow. petitboot is not petit at all either, and
>> has the disadvantage that you have to find a way to run GRUB afterwards.
> Well, not usually. Petitboot parses grub configuration itself, which
> means that generally from the OS / in
On Wed, Jan 15, 2020 at 09:57:06PM -0500, Raphael Norwitz wrote:
> The current vhost-user implementation in Qemu imposes a limit on the
> maximum number of memory slots exposed to a VM using a vhost-user
> device. This change provides a new protocol feature
> VHOST_USER_F_CONFIGURE_SLOTS which, whe
On Wed, Jan 15, 2020 at 09:57:03PM -0500, Raphael Norwitz wrote:
> In QEMU today, a VM with a vhost-user device can hot add memory a
> maximum of 8 times. See these threads, among others:
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg01046.html
> https://lists.gnu.org/archiv
On 06.02.20 00:00, Murilo Opsfelder Araújo wrote:
> Hello, David.
>
> On Monday, February 3, 2020 3:31:20 PM -03 David Hildenbrand wrote:
>> When shrinking a mmap we want to re-reserve the already populated area.
>> When growing a memory region, we want to populate starting with a given
>> fd_offs
On 05.02.20 20:21, Eric Blake wrote:
> On 2/5/20 11:04 AM, Max Reitz wrote:
>> OK, I expected users to come in a separate patch.
>
> I can refactor that better in v2.
>
>>
>>> That's the use case: when copying into a destination file, it's useful
>>> to know if the destination already reads as al
On 05.02.20 19:39, Eric Blake wrote:
> On 2/5/20 11:22 AM, Max Reitz wrote:
>
>>
And thus callers which just want the trivially obtainable
BDRV_ZERO_TRUNCATE info have to wait for the BDRV_ZERO_OPEN inquiry,
even though they don’t care about that flag.
>>>
>>> True, but only to a mi
On 05.02.20 20:56, Murilo Opsfelder Araújo wrote:
> Hello, David.
>
> On 2/3/20 3:31 PM, David Hildenbrand wrote:
>> We want to populate memory within a reserved memory region. Let's factor
>> that out.
>>
>> Cc: "Michael S. Tsirkin"
>> Cc: Greg Kurz
>> Cc: Murilo Opsfelder Araujo
>> Cc: Eduard
On Mon, Feb 03, 2020 at 07:31:12PM +0100, David Hildenbrand wrote:
> We already allow resizable ram blocks for anonymous memory, however, they
> are not actually resized. All memory is mmaped() R/W, including the memory
> exceeding the used_length, up to the max_length.
>
> When resizing, effectiv
From: Chen Qun
According to the glibc function requirements, we need initialise
the variable. Otherwise there will be compilation warnings:
glib-autocleanups.h:28:3: warning: ‘out’ may be
used uninitialized in this function [-Wmaybe-uninitialized]
g_free (*pp);
^~~~
Reported-by:
Le 06/02/2020 à 09:21, Thomas Huth a écrit :
> On 06/02/2020 05.07, kuhn.chen...@huawei.com wrote:
>> From: Chen Qun
>>
>> Fix warning:
>> hw/i2c/aspeed_i2c.c: In function ‘aspeed_i2c_bus_write’:
>> glib/glib-autocleanups.h:28:3: warning: ‘cmd_flags’ may be
>> used uninitialized in this function [
* John Snow (js...@redhat.com) wrote:
>
>
> On 1/28/20 11:47 AM, Dr. David Alan Gilbert wrote:
> > * John Snow (js...@redhat.com) wrote:
> >>
> >>
> >> On 1/27/20 3:43 PM, Peter Krempa wrote:
> >>> On Mon, Jan 27, 2020 at 14:39:02 -0500, John Snow wrote:
>
>
> On 1/27/20 5:36 AM, M
Le 09/01/2020 à 12:25, Philippe Mathieu-Daudé a écrit :
> Nothing from "sysemu/cpus.h" is used by smbios.c, remove the include.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/smbios/smbios.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
>
"Dr. David Alan Gilbert" writes:
> * John Snow (js...@redhat.com) wrote:
>> I'm forking the subject as I believe Markus wanted to focus on the
>> machine interface aspect.
>>
>> I feel that a new human interface is *related* to that goal: the
>> splitting of, and commitment to, separate human an
Le 15/01/2020 à 08:20, kuhn.chen...@huawei.com a écrit :
> From: Chen Qun
>
> When remove dup_fd in monitor_fdset_dup_fd_find_remove function,
> we need to free mon_fdset_fd_dup. ASAN shows memory leak stack:
>
> Direct leak of 96 byte(s) in 3 object(s) allocated from:
> #0 0xfffd37b033b3 in
On 06.02.20 10:27, Michael S. Tsirkin wrote:
> On Mon, Feb 03, 2020 at 07:31:12PM +0100, David Hildenbrand wrote:
>> We already allow resizable ram blocks for anonymous memory, however, they
>> are not actually resized. All memory is mmaped() R/W, including the memory
>> exceeding the used_length,
Le 17/01/2020 à 14:18, Leif Lindholm a écrit :
> On Thu, Jan 16, 2020 at 19:25:52 +0100, Philippe Mathieu-Daudé wrote:
>> On 1/16/20 6:42 PM, Leif Lindholm wrote:
>>> Update address to reflect new employer.
>>>
>>> Signed-off-by: Leif Lindholm
>>> ---
>>> MAINTAINERS | 2 +-
>>> 1 file changed,
Le 17/01/2020 à 17:58, Philippe Mathieu-Daudé a écrit :
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/rtc/m48t59-internal.h | 5 -
> hw/rtc/m48t59.c | 11 +--
> hw/rtc/trace-events | 6 ++
> 3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/
On Tue, 4 Feb 2020 at 18:40, Alex Bennée wrote:
>
> The following changes since commit 7bd9d0a9e26c7a3c67c0f174f0009ba19969b158:
>
> Merge remote-tracking branch
> 'remotes/huth-gitlab/tags/pull-request-2020-02-04' into staging (2020-02-04
> 16:12:31 +)
>
> are available in the Git reposit
On Wed, 5 Feb 2020 13:21:26 -0500
"Jason J. Herne" wrote:
> This fixes vfio-ccw when booting non-Linux operating systems. Without this
> struct being packed, a few extra bytes of low core memory get overwritten when
> we assign a value to memory address 0 in jump_to_IPL_2. This is enough to
> c
On Wed, Feb 05, 2020 at 08:13:19PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/5/20 6:51 PM, Daniel P. Berrangé wrote:
> > On Wed, Feb 05, 2020 at 06:40:31PM +0100, Aleksandar Markovic wrote:
> >> On Sat, Feb 1, 2020 at 7:53 PM Philippe Mathieu-Daudé
> >> wrote:
> >>>
> >> @@ -1151,10 +1150,6
Le 23/01/2020 à 07:45, Thomas Huth a écrit :
> While removing the bluetooth code some weeks ago, I had to leave the
> hw/bt/Kconfig file around. Otherwise some of the builds would have been
> broken since the generated dependency files tried to include it before
> they were rebuilt. Meanwhile, all
Le 29/01/2020 à 12:29, Thomas Huth a écrit :
> QEMU currently crashes when the user tries to use the "vmmouse" on a
> machine without vmport, e.g.:
>
> $ x86_64-softmmu/qemu-system-x86_64 -machine microvm -device vmmouse
> Segmentation fault (core dumped)
>
> or:
>
> $ x86_64-softmmu/qemu-sys
Le 29/01/2020 à 20:03, Philippe Mathieu-Daudé a écrit :
> Modifications to default-configs/hppa-softmmu.mak should be
> reviewed by the hppa-softmmu users (currently a single machine).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
On Thu, Feb 06, 2020 at 10:40:37AM +0100, Markus Armbruster wrote:
> > If the user screwsup, it should give an error that prompts the user
> > to the parameter they got wrong.
> >
> > Output from commands should normally be pretty formatted (with an option
> > to display raw json for those needing
Le 04/02/2020 à 17:56, John Snow a écrit :
> This is the only instance of a non-zero constant not using a symbolic
> constant.
> ---
> qemu-options.hx | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/qemu-options.hx b/qemu-options.hx
> index 224a8e8712..ff3e806977 100644
>
On 05.02.20 16:38, Kevin Wolf wrote:
> Am 30.01.2020 um 22:44 hat Max Reitz geschrieben:
>> We will need this to verify that Quorum can let one of its children be
>> replaced without breaking anything else.
>>
>> Signed-off-by: Max Reitz
>> ---
>> block/quorum.c | 25 +
>>
On 05.02.20 19:21, Jason J. Herne wrote:
> This fixes vfio-ccw when booting non-Linux operating systems. Without this
> struct being packed, a few extra bytes of low core memory get overwritten when
> we assign a value to memory address 0 in jump_to_IPL_2. This is enough to
> cause some non-Lin
Le 05/02/2020 à 18:17, Philippe Mathieu-Daudé a écrit :
> Cc'ing qemu-trivial@
>
> On 2/5/20 5:30 PM, Julia Suvorova wrote:
>> The '-i AIO' option was accidentally placed after '-n' and '-t'. Move it
>> after '--flush-interval'.
>>
>> Signed-off-by: Julia Suvorova
>> ---
>> docs/interop/qemu-im
Le 05/02/2020 à 19:51, Julia Suvorova a écrit :
> Signed-off-by: Julia Suvorova
> ---
> include/hw/pci/pci_bridge.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
> index ba488818d2..99c674e949 100644
> --- a/inc
On 06/02/2020 10.32, kuhn.chen...@huawei.com wrote:
> From: Chen Qun
>
> According to the glibc function requirements, we need initialise
> the variable. Otherwise there will be compilation warnings:
>
> glib-autocleanups.h:28:3: warning: ‘out’ may be
> used uninitialized in this function [-Wma
Le 21/01/2020 à 10:28, mreza...@redhat.com a écrit :
> From: Miroslav Rezanina
>
> Compiler reports uninitialized warning for cmd_flags variable.
>
> Adding NULL initialization to prevent this warning.
>
> Signed-off-by: Miroslav Rezanina
> ---
> hw/i2c/aspeed_i2c.c | 2 +-
> 1 file changed,
> -Original Message-
> From: David Hildenbrand [mailto:da...@redhat.com]
> Sent: 05 February 2020 16:41
> To: Shameerali Kolothum Thodi ;
> Igor Mammedov
> Cc: peter.mayd...@linaro.org; xiaoguangrong.e...@gmail.com;
> m...@redhat.com; shannon.zha...@gmail.com; qemu-devel@nongnu.org;
> xu
On 05.02.20 16:55, Kevin Wolf wrote:
> Am 11.11.2019 um 17:02 hat Max Reitz geschrieben:
>> Signed-off-by: Max Reitz
>> ---
>> block/quorum.c | 62 ++
>> 1 file changed, 62 insertions(+)
>>
>> diff --git a/block/quorum.c b/block/quorum.c
>> index 3a
On 05.02.20 14:51, Eric Blake wrote:
> On 2/4/20 11:08 AM, Max Reitz wrote:
>> We want to unify child_format and child_file at some point. One of the
>> important things that set format drivers apart from other drivers is
>> that they do not expect other format nodes under them (except in the
>> b
On 03.02.2020 12:54, Philippe Mathieu-Daudé wrote:
>> @@ -2029,6 +2072,19 @@ static void qemu_whpx_start_vcpu(CPUState *cpu)
>> #endif
>> }
>>
>> +static void qemu_nvmm_start_vcpu(CPUState *cpu)
>> +{
>> + char thread_name[VCPU_THREAD_NAME_SIZE];
>> +
>> + cpu->thread = g_malloc0(sizeof(Q
On 2/6/20 6:02 AM, Richard Henderson wrote:
> On 2/5/20 10:41 PM, Taylor Simpson wrote:
>> Currently, helpers can only take up to 6 arguments. This patch adds the
>> capability for up to 7 arguments. I have tested it with the Hexagon port
>> that I am preparing for submission.
>
> This is not sa
Alex Bennée writes:
> Richard Henderson writes:
>
>> Version 6 moves vhe_reginfo[] to file scope, and one tweak
>> to the vhe register access masking that Peter asked for.
>>
>> All patches now have reviews.
>
> I was re-testing and I was able to boot my guest Image+buildroot.
> However the bu
QEMU is all about the Python 3 now so lets also hint that to
ReadTheDocs in its config file.
Signed-off-by: Alex Bennée
---
.readthedocs.yml | 17 +
1 file changed, 17 insertions(+)
create mode 100644 .readthedocs.yml
diff --git a/.readthedocs.yml b/.readthedocs.yml
new file mo
On 05.02.20 16:24, Eric Blake wrote:
> On 2/4/20 11:08 AM, Max Reitz wrote:
>> This enum will supplement BdrvChildClass when it comes to what role (or
>> combination of roles) a child takes for its parent.
>>
>> Because empty enums are not allowed, let us just start with it filled.
>>
>> Signed-off
On 06.02.20 11:47, Max Reitz wrote:
> On 05.02.20 16:24, Eric Blake wrote:
>> On 2/4/20 11:08 AM, Max Reitz wrote:
>>> This enum will supplement BdrvChildClass when it comes to what role (or
>>> combination of roles) a child takes for its parent.
>>>
>>> Because empty enums are not allowed, let us
On 05.02.20 16:33, Eric Blake wrote:
> On 2/4/20 11:08 AM, Max Reitz wrote:
>> For now, it is always set to 0. Later patches in this series will
>> ensure that all callers pass an appropriate combination of flags.
>
> Sneaky - this re-adds the field you dropped as part of a rename in 2/33.
> Any
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 608fcbd0b7..2a53f5d09b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3685,6 +3685,1
Version 7 has one more tweak to the vhe tlb flushing
that Peter asked for. All patches have reviews.
r~
Alex Bennée (1):
target/arm: check TGE and E2H flags for EL0 pauth traps
Richard Henderson (40):
target/arm: Define isar_feature_aa64_vh
target/arm: Enable HCR_E2H for VHE
target/ar
At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v5: Do not update TCR_EL2 yet; delay that til we handle ASIDs.
---
target/arm/helper.c | 13 -
1
No functional change, but unify code sequences.
Tested-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v5: Do not confuse things by prefixing "vm".
---
target/arm/helper.c | 86 +
1 f
No functional change, but unify code sequences.
Tested-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 32 +---
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/t
This is part of a reorganization to the set of mmu_idx.
The EL1&0 regime is the only one that uses 2-stage translation.
Spelling out Stage avoids confusion with Secure.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v5: Adjust || indentation (ajb)
---
targ
Not all of the breakpoint types are supported, but those that
only examine contextidr are extended to support the new register.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v6: Move reginfo to file scope.
---
target/arm/debug_helper.c | 50 ++
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 7 ---
target/arm/helper.c | 6 +-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2a53f5d09b..0e68704a90 100644
--- a/targ
This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4
We are about to expand the number of mmuidx to 10, and so need 4 bits.
For the benefit of reading the number out of -d exec, align it to the
penultimate nibble.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 16
1 file c
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.
The ultimate goal is
-- Non-secure regimes:
ARMMMUIdx_E10_0,
ARMMMUIdx_E20_0,
ARMMMUIdx_E10_1,
ARMMMUIdx_E2,
ARMMMUIdx_E20_2,
-- Secure regimes:
ARMMMUIdx_SE10_0
The virtual offset may be 0 depending on EL, E2H and TGE.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 40 +---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b
This is part of a reorganization to the set of mmu_idx.
The EL3 regime only has a single stage translation, and
is always secure.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 2 +-
target/arm/he
Use the correct sctlr for EL2&0 regime. Due to header ordering,
and where arm_mmu_idx_el is declared, we need to move the function
out of line. Use the function in many more places in order to
select the correct control.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard He
We had completely run out of TBFLAG bits.
Split A- and M-profile bits into two overlapping buckets.
This results in 4 free bits.
We used to initialize all of the a32 and m32 fields in DisasContext
by assignment, in arm_tr_init_disas_context. Now we only initialize
either the a32 or m32 by assignm
Rather than call to a separate function and re-compute any
parameters for the flush, simply use the correct flush
function directly.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 52 +
1 fi
Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants.
Keep the definitions short by referencing previous symbols.
Tested-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 16
1 file changed, 8 insertion
For ARMv8.1, op1 == 5 is reserved for EL2 aliases of
EL1 and EL0 registers.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper
The comment that we don't support EL2 is somewhat out of date.
Update to include checks against HCR_EL2.TDZ.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-
The EL1&0 regime is the only one that uses 2-stage translation.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 +--
target/arm/internals.h | 2 +-
target/arm/helper.c| 57 --
Create a predicate to indicate whether the regime has
both positive and negative addresses.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 18 ++
target/arm/helper.c| 23 ++-
target/a
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v5: Flush all EL2 regimes with TLBI ALLE2 (pmm).
v7: Flush all EL2 regimes with TLBI VAE2 (pmm).
---
target/arm/helper.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the Secure EL1&0 regime.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8
target/arm/internals.h | 4 ++--
target/arm/tr
Return the indexes for the EL2&0 regime when the appropriate bits
are set within HCR_EL2.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v4: Consistently check E2H & TGE & ELUsingAArch32(EL2).
Do not apply TGE at EL2.
---
target/arm/helper.c | 11 +
When TGE+E2H are both set, CPACR_EL1 is ignored.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 53 -
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/target/arm/helper.c b/
Define via macro expansion, so that renumbering of the base ARMMMUIdx
symbols is automatically reflected in the bit definitions.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 39 +
The TGE bit routes all asynchronous exceptions to EL2.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3b7b459314..56a62b11d0 100
Update to include checks against HCR_EL2.TID2.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
inde
Prepare for, but do not yet implement, the EL2&0 regime.
This involves adding the new MMUIdx enumerators and adjusting
some of the MMUIdx related predicates to match.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 +-
target/ar
From: Alex Bennée
According to ARM ARM we should only trap from the EL1&0 regime.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/pauth_helper.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 1 +
target/arm/cpu.h | 11 +
target/arm/cpu.c | 3 ++-
target/arm/helper.c | 56
4 files changed, 65 insertions(+), 6 dele
The EL2&0 translation regime is affected by Load Register (unpriv).
The code structure used here will facilitate later changes in this
area for implementing UAO and NV.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 9 -
Hello,
I suggest changing the subject to:
"mailmap: Add entry for Yu-Chen Lin"
On 12/6/19 3:15 PM, Philippe Mathieu-Daudé wrote:
Cc'ing qemu-trivial@
On 12/6/19 3:09 PM, Yu-Chen Lin wrote:
I have two mail address, add entries for
showing author and email correctly.
Signed-off-by: Yu-Chen Lin
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 102 +++-
1 file changed, 81 insertions(+), 21 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 996865a3a2..992ab2a15f 100
When VHE is enabled, the exception level below EL2 is not EL1,
but EL0, and so to identify the entry vector offset for exceptions
targeting EL2 we need to look at the width of EL0, not of EL1.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/hel
This inline function has one user in cpu.c, and need not be exposed
otherwise. Code movement only, with fixups for checkpatch.
Tested-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 111 ---
ta
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 2d97bf45e1..c80fb5fd43 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -672,6 +
Since we only support a single ASID, flush the tlb when it changes.
Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between
the two TTBR* registers for the location of the ASID.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/help
The fall through organization of this function meant that we
would raise an interrupt, then might overwrite that with another.
Since interrupt prioritization is IMPLEMENTATION DEFINED, we
can recognize these in any order we choose.
Unify the code to raise the interrupt in a block at the end.
Test
The value computed is fully boolean; using int8_t is odd.
Tested-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fcee0a2
Several of the EL1/0 registers are redirected to the EL2 version when in
EL2 and HCR_EL2.E2H is set. Many of these registers have side effects.
Link together the two ARMCPRegInfo structures after they have been
properly instantiated. Install common dispatch routines to all of the
relevant registe
On 06/02/2020 11.09, Christian Borntraeger wrote:
>
>
> On 05.02.20 19:21, Jason J. Herne wrote:
>> This fixes vfio-ccw when booting non-Linux operating systems. Without this
>> struct being packed, a few extra bytes of low core memory get overwritten
>> when
>> we assign a value to memory addr
Apart from the wholesale redirection that HCR_EL2.E2H performs
for EL2, there's a separate redirection specific to the timers
that happens for EL0 when running in the EL2&0 regime.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 181
On 05.02.20 17:48, Eric Blake wrote:
> On 2/4/20 11:08 AM, Max Reitz wrote:
>> After the series this patch belongs to, we want to have a common
>> BdrvChildClass that encompasses all of child_file, child_format, and
>> child_backing. Such a single class needs a single .inherit_options()
>> impleme
On 06.02.20 11:20, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-
>> From: David Hildenbrand [mailto:da...@redhat.com]
>> Sent: 05 February 2020 16:41
>> To: Shameerali Kolothum Thodi ;
>> Igor Mammedov
>> Cc: peter.mayd...@linaro.org; xiaoguangrong.e...@gmail.com;
>> m...@re
Avoid redundant computation of cpu state by passing it in
from the caller, which has already computed it for itself.
Tested-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 22 --
1 file changed, 12 insertions(+), 1
On Thu, 6 Feb 2020 at 10:47, Alex Bennée wrote:
>
> QEMU is all about the Python 3 now so lets also hint that to
> ReadTheDocs in its config file.
>
> Signed-off-by: Alex Bennée
> ---
> .readthedocs.yml | 17 +
> 1 file changed, 17 insertions(+)
> create mode 100644 .readthedocs
On 2/5/20 5:10 PM, Alex Bennée wrote:
> -/* with maximum vector length */
> +/* with reasonable vector length */
> env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
> - cpu->sve_max_vq - 1 : 0;
> +MIN(cpu->sve_max_vq - 1, 3) : 0;
On 2/5/20 5:10 PM, Alex Bennée wrote:
> This is cleaner than poking memory directly and will make later
> clean-ups easier.
>
> Signed-off-by: Alex Bennée
> ---
> target/i386/gdbstub.c | 22 --
> 1 file changed, 8 insertions(+), 14 deletions(-)
>
> diff --git a/target/i386/g
On 2/5/20 5:10 PM, Alex Bennée wrote:
> +case 51:
> +return gdb_get_reg32(buf,
> + sve_zcr_len_for_el(env, arm_current_el(env)) +
> 1);
vg = vq * 2. Need the multiplication here.
r~
On 2/5/20 5:10 PM, Alex Bennée wrote:
> @@ -7143,6 +7255,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
> gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
> arm_gen_dynamic_sysreg_xml(cs,
> cs->gdb_num_regs),
>
On 05.02.20 21:56, Eric Blake wrote:
> On 2/4/20 11:08 AM, Max Reitz wrote:
>> Signed-off-by: Max Reitz
>
> Rather light on the commit message. But looks like straightforward
> refactoring (with the previous patch making it easier to follow).
Would this work:
Right now, bdrv_format_default_perm
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