On 15/12/2019 22.15, Joakim Tjernlund wrote:
[...]
>> LOG_EXCP() is not enabled by default, you have to edit source to enable it
>
> LOG_EXCP is enabled on Gentoo, what about other distros?
I don't think that this is enabled by any other distro. Why is this
enabled on Gentoo at all? It really sho
On Fri, Dec 13, 2019 at 09:24:03AM -0500, Michael S. Tsirkin wrote:
> Some guests read back queue size after writing it.
> Update the size immediatly upon write otherwise
> they get confused.
>
> Signed-off-by: Michael S. Tsirkin
> ---
> hw/virtio/virtio-pci.c | 2 ++
> 1 file changed, 2 inserti
On Mon, 2019-12-16 at 09:27 +0100, Thomas Huth wrote:
>
> On 15/12/2019 22.15, Joakim Tjernlund wrote:
> [...]
> > > LOG_EXCP() is not enabled by default, you have to edit source to enable it
> >
> > LOG_EXCP is enabled on Gentoo, what about other distros?
>
> I don't think that this is enabled
On Mon, Dec 16, 2019 at 09:27:13AM +0100, Thomas Huth wrote:
> On 15/12/2019 22.15, Joakim Tjernlund wrote:
> [...]
> >> LOG_EXCP() is not enabled by default, you have to edit source to enable it
> >
> > LOG_EXCP is enabled on Gentoo, what about other distros?
>
> I don't think that this is enabl
Corey Minyard writes:
> On Sat, Nov 30, 2019 at 08:42:30PM +0100, Markus Armbruster wrote:
>> isa_ipmi_bt_realize(), ipmi_isa_realize(), pci_ipmi_bt_realize(), and
>> pci_ipmi_kcs_realize() crash when IPMIInterfaceClass method init()
>> fails and their @errp argument is null. First messed up in
Hi :
Can I get some love for this patch?
thanks
ani
On Dec 4, 2019, 3:06 PM +0530, Ani Sinha , wrote:
CLZERO CPUID should be passed on to the guests that use EPYC or EPYC-IBPB CPU
model when the AMD ZEN based host supports it. This change makes it recognize
this CPUID for guests which use EPYC o
> -Original Message-
[snip]
> >>
> >> This feels like a race condition between the init/free code with
> >> handler. Anthony, does it ring any bell?
> >>
> >
> > From that stack bt it looks like an iothread managed to run after the
> sring was NULLed. This should not be able happen as the
> -Original Message-
> From: Xen-devel On Behalf Of
> Durrant, Paul
> Sent: 16 December 2019 09:34
> To: Julien Grall ; Ian Jackson
> Cc: Jürgen Groß ; Stefano Stabellini
> ; qemu-devel@nongnu.org; osstest service owner
> ; Anthony Perard
> ; xen-de...@lists.xenproject.org
> Subject: Re:
On Fri, Dec 13, 2019 at 06:20:15PM +, Dr. David Alan Gilbert wrote:
> * Marc-André Lureau (marcandre.lur...@redhat.com) wrote:
> > Signed-off-by: Marc-André Lureau
>
> > +static gboolean
> > +vmstate_save(VMState1 *object, GDBusMethodInvocation *invocation,
> > + gpointer user_dat
v4:
* rebased on 4.2 [MST]
v3:
* add property to set in machine type [MST]
* add min queue size check [Stefan]
* add avocado based test [Max, Stefan, Eduardo, Cleber]
v2:
* the standalone patch to make seg_max virtqueue size dependent
* other patches are postponed
v1:
the initial s
It tests proper seg_max_adjust settings for all machine types except
'none', 'isapc', 'microvm'
Signed-off-by: Denis Plotnikov
---
tests/acceptance/virtio_seg_max_adjust.py | 135 ++
1 file changed, 135 insertions(+)
create mode 100755 tests/acceptance/virtio_seg_max_adjust.
Before the patch, seg_max parameter was immutable and hardcoded
to 126 (128 - 2) without respect to queue size. This has two negative effects:
1. when queue size is < 128, we have Virtio 1.1 specfication violation:
(2.6.5.3.1 Driver Requirements) seq_max must be <= queue_size.
This violation
** Description changed:
AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems to
always map Cache ass if it was an 4-Core per CCX CPU, which is
incorrect, and costs upwards 30% performance (more realistically 10%) in
L3 Cache Layout aware applications.
Example on a 4-CC
> -Original Message-
> From: Durrant, Paul
> Sent: 16 December 2019 09:50
> To: Durrant, Paul ; Julien Grall ;
> Ian Jackson
> Cc: Jürgen Groß ; Stefano Stabellini
> ; qemu-devel@nongnu.org; osstest service owner
> ; Anthony Perard
> ; xen-de...@lists.xenproject.org
> Subject: RE: [Xen-de
On Thu, 12 Dec 2019 at 18:54, Thomas Huth wrote:
>
> Hi,
>
> the following changes since commit 52901abf94477b400cf88c1f70bb305e690ba2de:
>
> Update version for v4.2.0-rc5 release (2019-12-10 17:15:21 +)
>
> are available in the Git repository at:
>
> https://gitlab.com/huth/qemu.git tags
On Mon, Dec 16, 2019 at 09:50:13AM +0100, Stefano Garzarella wrote:
> On Fri, Dec 13, 2019 at 09:24:03AM -0500, Michael S. Tsirkin wrote:
> > Some guests read back queue size after writing it.
> > Update the size immediatly upon write otherwise
> > they get confused.
> >
> > Signed-off-by: Michael
On Mon, Dec 16, 2019 at 01:04:49PM +0300, Denis Plotnikov wrote:
> v4:
> * rebased on 4.2 [MST]
Looks good. Can I get some acks from storage guys pls?
> v3:
> * add property to set in machine type [MST]
> * add min queue size check [Stefan]
> * add avocado based test [Max, Stefan, Eduard
Our docker infrastructure isn't quite as multiarch as we would wish so
lets allow the user to disable it if they want. This will allow us to
use still run check-tcg on non-x86 CI setups.
Signed-off-by: Alex Bennée
Reviewed-by: Stefan Weil
---
configure | 8 +++-
tests/tcg/confi
From: Wainer dos Santos Moschetta
By default VM build test use qemu-img from system's PATH to
create the image disk. Due the lack of qemu-img on the system
or the desire to simply use a version built with QEMU, it would
be nice to allow one to set its path. So this patch makes that
possible by re
Hi,
This series will be my first post 4.2 PR this week. It contains a
number of testing related fixes including enabling builds for arm64,
ppc64 and s390x hosts. We also start defaulting to out-of-tree builds
in anticipation of it's deprecation.
As there is no obvious tree for logging changes I'v
From: Thomas Huth
Some tests create huge (but sparse) files, and to be able to run those
tests in certain limited environments (like CI containers), we have to
check for the possibility to create such files first. Thus let's introduce
a common function to check for large files, and replace the al
From: Thomas Huth
So far we only have compile coverage for tci. But since commit
2f160e0f9797c7522bfd0d09218d0c9340a5137c ("tci: Add implementation
for INDEX_op_ld16u_i64") has been included now, we can also run the
"tcg" and "qtest" tests with tci, so let's enable them in Travis now.
Since we do
From: Thomas Huth
Test 060 fails in the arm64, s390x and ppc64le LXD containers on Travis
(which we will hopefully enable in our CI soon). These containers
apparently do not allow large files to be created. The repair process
in test 060 creates a file of 64 GiB, so test first whether such large
From: Thomas Huth
Test 079 fails in the arm64, s390x and ppc64le LXD containers on Travis
(which we will hopefully enable in our CI soon). These containers
apparently do not allow large files to be created. Test 079 tries to
create a 4G sparse file, which is apparently already too big for these
c
From: Thomas Huth
In certain environments like restricted containers, we can not create
huge test images. To be able to use "make check" in such container
environments, too, let's skip the hd-geo-test instead of failing when
the test images could not be created.
Reviewed-by: Philippe Mathieu-Dau
From: Thomas Huth
test-util-filemonitor fails in restricted non-x86 Travis containers
since they apparently blacklisted some required system calls there.
Let's simply skip the test if we detect such an environment.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Tho
From: Thomas Huth
Travis recently added the possibility to test on these architectures,
too, so let's enable them in our travis.yml file to extend our test
coverage.
Unfortunately, the libssh in this Ubuntu version (bionic) is in a pretty
unusable Frankenstein state and libspice-server-dev is no
From: Paolo Bonzini
Most developers are using out-of-tree builds and it was discussed in the past
to only allow those. To prepare for the transition, use out-of-tree builds
in all continuous integration jobs.
Based on a patch by Marc-André Lureau.
Signed-off-by: Paolo Bonzini
Signed-off-by: A
org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20191216-1
for you to fetch changes up to f80741d107673f162e3b097fc76a1590036cc9d1:
target/arm: ensure we use current exception state after SCR update
(2019-12-16 10:52:58 +)
-
From: Robert Foley
After freeing the logfilename, we set logfilename to NULL, in case of an
error which returns without setting logfilename.
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <20191118211528.3221-2-robert.fo...@linaro.org>
---
util/lo
From: Cédric Le Goater
The SRAM must be enabled before using the Buffer Pool mode or the DMA
mode. This is not required on other SoCs.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Tested-by: Jae Hyun Yoo
Signed-off-by: Cédric Le Goater
Message-id: 20191119141211.25716-3-...@kaod
From: Robert Foley
Also added qemu_logfile_init() for initializing the logfile mutex.
Note that inside qemu_set_log() we needed to add a pair of
qemu_mutex_unlock() calls in order to avoid a double lock in
qemu_log_close(). This unavoidable temporary ugliness will be
cleaned up in a later patch
From: Joel Stanley
This models the clock write one to clear registers, and fixes up some
incorrect behavior in all of the write to clear registers.
There was also a typo in one of the register definitions.
Reviewed-by: Cédric Le Goater
Reviewed-by: Alex Bennée
Signed-off-by: Joel Stanley
Sig
From: Cédric Le Goater
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.
A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The r
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Tested-by: Jae Hyun Yoo
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
Message-id: 20191119141211.25716-6-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/i2c/aspeed_i2c.c | 93 +++
From: Christophe Lyon
This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.
Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".
Signed-off-by
From: Cédric Le Goater
AspeedBoardConfig is a redundant way to define class attributes and it
complexifies the machine definition and initialization.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Signed-off-by: Cédric Le Goater
Message-id: 20191119141211.25716-14-...@kaod.org
Sign
From: David Gibson
exynos4210_gic_realize() prints the number of cpus into some temporary
buffers, but it only allows 3 bytes space for it. That's plenty:
existing machines will only ever set this value to EXYNOS4210_NCPUS
(2). But the compiler can't always figure that out, so some[*] gcc9
vers
From: Joel Stanley
Users benefit from knowing which watchdog timer has expired. The address
of the watchdog's registers unambiguously indicates which has expired,
so log that.
Reviewed-by: Cédric Le Goater
Reviewed-by: Alex Bennée
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
M
From: Joel Stanley
Most boards have this much.
Reviewed-by: Cédric Le Goater
Reviewed-by: Alex Bennée
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
Message-id: 20191119141211.25716-7-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/misc/aspeed_sdmc.c | 6 +++---
1 file change
From: Marc Zyngier
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.
Tested with a hac
From: Cédric Le Goater
Currently, we link the DRAM memory region to the FMC model (for DMAs)
through a property alias at the SoC level. The I2C model will need a
similar region for DMA support, add a DRAM region property at the SoC
level for both model to use.
Signed-off-by: Cédric Le Goater
Re
From: Cédric Le Goater
The current model only restores the Segment Register values but leaves
the previous CS mapping behind. Introduce a helper setting the
register value and mapping the region at the requested address. Use
this helper when a Segment register is set and at reset.
Signed-off-by:
From: Joel Stanley
The AST2600 control register sneakily changed the meaning of bit 4
without anyone noticing. It no longer controls the 1MHz vs APB clock
select, and instead always runs at 1MHz.
The AST2500 was always 1MHz too, but it retained bit 4, making it read
only. We can model both using
From: Cédric Le Goater
The Aspeed I2C controller can operate in different transfer modes :
- Byte Buffer mode, using a dedicated register to transfer a
byte. This is what the model supports today.
- Pool Buffer mode, using an internal SRAM to transfer multiple
bytes in the same comm
From: Niek Linnenbank
This change ensures that the FPU can be accessed in Non-Secure mode
when the CPU core is reset using the arm_set_cpu_on() function call.
The NSACR.{CP11,CP10} bits define the exception level required to
access the FPU in Non-Secure mode. Without these bits set, the CPU
will
From: Cédric Le Goater
The Aspeed Watchdog and Timer models have a link pointing to the SCU
controller model of the machine.
Change the "scu" property definition so that it explicitly sets the
pointer. The property isn't optional : not being able to set the link
is a bug and QEMU should rather a
From: Cédric Le Goater
The segments can be disabled on the AST2600 (zero register value).
CS0 is open by default but not the other CS. This is closing the
access to the flash device in user mode and forbids scanning.
In the model, check the segment size and disable the associated region
when the
From: Heyi Guo
After the introduction of generic PCIe root port and PCIe-PCI bridge,
we will also have SHPC controller on ARM, so just enable SHPC native
hot plug.
Also update tests/data/acpi/virt/DSDT* to pass "make check".
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igo
From: Cédric Le Goater
Each CS has its own Read Timing Compensation Register on newer SoCs.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Signed-off-by: Cédric Le Goater
Message-id: 20191119141211.25716-13-...@kaod.org
Signed-off-by: Peter Maydell
---
include/hw/ssi/aspeed_smc.h
From: PanNengyuan
Address Sanitizer shows memory leak in hw/gpio/aspeed_gpio.c:875
Reported-by: Euler Robot
Signed-off-by: PanNengyuan
Reviewed-by: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Message-id: 20191119141211.25716-16-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/gpio/asp
From: Beata Michalska
Switch to ram block writeback for pmem migration.
Signed-off-by: Beata Michalska
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Acked-by: Dr. David Alan Gilbert
Message-id: 20191121000843.24844-4-beata.michal...@linaro.org
Signed-off-by: Peter Maydell
---
mig
From: Philippe Mathieu-Daudé
Make the gic a field in the machine state, and instead of filling
an array of qemu_irq and passing it around, directly call
qdev_get_gpio_in() on the gic field.
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20191206162303.30338-1-phi...@redhat.com
Reviewed-by: P
From: Marc Zyngier
HSTR_EL2 offers a way to trap ranges of CP15 system register
accesses to EL2, and it looks like this register is completely
ignored by QEMU.
To avoid adding extra .accessfn filters all over the place (which
would have a direct performance impact), let's add a new TB flag
that
From: Cédric Le Goater
The Tacoma BMC board is replacement board for the BMC of the OpenPOWER
Witherspoon system. It uses a AST2600 SoC instead of a AST2500 and the
I2C layout is the same as it controls the same main board. Used for HW
bringup.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel
From: Beata Michalska
Add an option to trigger memory writeback to sync given memory region
with the corresponding backing store, case one is available.
This extends the support for persistent memory, allowing syncing on-demand.
Signed-off-by: Beata Michalska
Reviewed-by: Richard Henderson
Mes
From: Beata Michalska
Add probe_read alongside the write probing equivalent.
Signed-off-by: Beata Michalska
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-id: 20191121000843.24844-2-beata.michal...@linaro.org
Signed-off-by: Peter Maydell
---
include/exec/exec-all.h | 6
From: Robert Foley
Also added some explanation of the reasoning behind the branches.
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Signed-off-by: Alex Bennée
Message-Id: <20191118211528.3221-3-robert.fo...@linaro.org>
---
util/log.c | 21 +++--
1 file changed, 15 inser
From: Cédric Le Goater
The Aspeed MII model has a link pointing to its associated FTGMAC100
NIC in the machine.
Change the "nic" property definition so that it explicitly sets the
pointer. The property isn't optional : not being able to set the link
is a bug and QEMU should rather abort than exi
On Mon, Dec 16, 2019 at 7:07 PM Alex Bennée wrote:
>
> From: Paolo Bonzini
>
> Most developers are using out-of-tree builds and it was discussed in the past
> to only allow those. To prepare for the transition, use out-of-tree builds
> in all continuous integration jobs.
>
> Based on a patch by
From: Beata Michalska
ARMv8.2 introduced support for Data Cache Clean instructions
to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
- DV CVADP. Both specify conceptual points in a memory system where all writes
that are to reach them are considered persistent.
The supp
ZIPL adds a "BOOT_IMAGE=x" to the kernel parameters to indicate which
kernel entry has been chosen during the boot process. Apparently some
Linux tools like "dracut" use this setting, so we should provide this
kernel parameter with the s390-ccw bios, too.
However, it's a little bit tricky to get a
From: Marc Zyngier
HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
completely ignores it, making it impossible for hypervisors to
virtualize the cache hierarchy.
Do the right thing by trapping to EL2 if HCR_EL2.TI
From: Alex Bennée
A write to the SCR can change the effective EL by droppping the system
from secure to non-secure mode. However if we use a cached current_el
from before the change we'll rebuild the flags incorrectly. To fix
this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL
shoul
From: Marc Zyngier
HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1
(and their 32bit equivalents) as well as TCMTR, TLBTR are trapped
to EL2. QEMU ignores it, making it harder for a hypervisor to
virtualize the HW (though to be fair, no known hypervisor actually
cares).
Do the
From: Robert Foley
One test ensures that the logfile handle is still valid even if
the logfile is changed during logging.
The other test validates that the logfile handle remains valid under
the logfile lock even if the logfile is closed.
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Si
From: Marc Zyngier
QEMU lacks the minimum Jazelle implementation that is required
by the architecture (everything is RAZ or RAZ/WI). Add it
together with the HCR_EL2.TID0 trapping that goes with it.
Signed-off-by: Marc Zyngier
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Richard Henderson
Mess
From: Heyi Guo
The last argument of AML bit and/or statement is the target variable,
so we don't need to use a NULL target and then an additional store
operation; using just aml_and() or aml_or() statement is enough.
Also update tests/data/acpi/virt/DSDT* to pass "make check".
Cc: Shannon Zhao
From: Robert Foley
This now allows changing the logfile while logging is active,
and also solves the issue of a seg fault while changing the logfile.
Any read access to the qemu_logfile handle will use
the rcu_read_lock()/unlock() around the use of the handle.
To fetch the handle we will use ato
From: Robert Foley
qemu_log_lock() now returns a handle and qemu_log_unlock() receives a
handle to unlock. This allows for changing the handle during logging
and ensures the lock() and unlock() are for the same file.
Also in target/tilegx/translate.c removed the qemu_log_lock()/unlock()
calls (
From: Philippe Mathieu-Daudé
Make the gic a field in the machine state, and instead of filling
an array of qemu_irq and passing it around, directly call
qdev_get_gpio_in() on the gic field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-id: 20191209090306.20433-1-phi...@
On Thu, Oct 17, 2019 at 8:06 PM Carlos Santos wrote:
>
> On Thu, Oct 17, 2019 at 9:47 AM Peter Maydell
> wrote:
> >
> > On Thu, 17 Oct 2019 at 13:39, wrote:
> > >
> > > From: Carlos Santos
> > >
> > > uClibc defines _SC_LEVEL1_ICACHE_LINESIZE and _SC_LEVEL1_DCACHE_LINESIZE
> > > but the corres
Hi David,
On 11/22/2019 10:00 AM, David Gibson wrote:
On Mon, Oct 14, 2019 at 01:37:50PM -0500, Shivaprasad G Bhat wrote:
---
index 62f1a42592..815167e42f 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -708,6 +708,17 @@ static void spapr_drc_phb_class_init(ObjectClass *k, void
*da
Public bug reported:
1.
qemu-4.2.0/hw/misc/mac_via.c:417:27: style: Expression is always false
because 'else if' condition matches previous condition at line 412.
[multiCondition]
} else if ((m->data_out & 0xf3) == 0xa1) {
...
} else if ((m->data_out & 0xf3) == 0x
Am 13.12.2019 um 21:59 hat Eric Blake geschrieben:
> On 12/9/19 10:06 AM, Kevin Wolf wrote:
> > Am 28.11.2019 um 11:41 hat Sergio Lopez geschrieben:
> > > bdrv_try_set_aio_context() requires that the old context is held, and
> > > the new context is not held. Fix all the occurrences where it's not
On 16.12.19 12:24, Thomas Huth wrote:
> Note: I've marked the patch as RFC since I'm not quite sure whether
> this is really the right way to address this issue: It's unfortunate
> that we have to mess with different location in ZIPL which might also
> change again in the future. As suggeste
On Sun, Dec 15, 2019 at 03:27:12PM +, Peter Maydell wrote:
> On Sun, 15 Dec 2019 at 09:51, Michael S. Tsirkin wrote:
> >
> > On Sat, Dec 14, 2019 at 04:28:08PM +, Peter Maydell wrote:
> > > (It doesn't actually assert that it doesn't
> > > overlap because we have some legacy uses, notably
On Mon, 16 Dec 2019 at 11:40, Michael S. Tsirkin wrote:
>
> On Sun, Dec 15, 2019 at 03:27:12PM +, Peter Maydell wrote:
> > On Sun, 15 Dec 2019 at 09:51, Michael S. Tsirkin wrote:
> > >
> > > On Sat, Dec 14, 2019 at 04:28:08PM +, Peter Maydell wrote:
> > > > (It doesn't actually assert tha
Laurent Vivier writes:
> Le 05/12/2019 à 13:25, Alex Bennée a écrit :
>> Convert the final bit of DEBUG_MMAP to a tracepoint and remove the
>> last remanents of the #ifdef hackery.
>>
>> Signed-off-by: Alex Bennée
>> Reviewed-by: Richard Henderson
>> ---
>> linux-user/mmap.c | 9 ++---
gcc compiler flag -Wduplicated-cond will catch this kind of problem.
You might want to switch it on in your builds. It has been available for
over a year.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bug
Le 16/12/2019 à 13:00, Alex Bennée a écrit :
>
> Laurent Vivier writes:
>
>> Le 05/12/2019 à 13:25, Alex Bennée a écrit :
>>> Convert the final bit of DEBUG_MMAP to a tracepoint and remove the
>>> last remanents of the #ifdef hackery.
>>>
>>> Signed-off-by: Alex Bennée
>>> Reviewed-by: Richard
Am 13.12.2019 um 17:28 hat Marc-André Lureau geschrieben:
> On Fri, Dec 13, 2019 at 8:04 PM Kevin Wolf wrote:
> >
> > Am 08.11.2019 um 16:00 hat Marc-André Lureau geschrieben:
> > > The following series implements an internal async command solution
> > > instead. By introducing a session context a
On 16/12/2019 11.27, Peter Maydell wrote:
> On Thu, 12 Dec 2019 at 18:54, Thomas Huth wrote:
>>
>> Hi,
>>
>> the following changes since commit 52901abf94477b400cf88c1f70bb305e690ba2de:
>>
>> Update version for v4.2.0-rc5 release (2019-12-10 17:15:21 +)
>>
>> are available in the Git reposi
On Mon, 16 Dec 2019 12:29:24 +0100
Christian Borntraeger wrote:
> On 16.12.19 12:24, Thomas Huth wrote:
> > Note: I've marked the patch as RFC since I'm not quite sure whether
> > this is really the right way to address this issue: It's unfortunate
> > that we have to mess with different locat
On 16.12.19 13:09, Cornelia Huck wrote:
> On Mon, 16 Dec 2019 12:29:24 +0100
> Christian Borntraeger wrote:
>
>> On 16.12.19 12:24, Thomas Huth wrote:
>>> Note: I've marked the patch as RFC since I'm not quite sure whether
>>> this is really the right way to address this issue: It's unfortun
Hi all!
Here is my proposal, about how to correctly update qcow2 specification
to introduce new field, keeping in mind currently existing images and
downstream Qemu instances.
v9: Merge 01 and 02
Change wordings
Require header alignment
Vladimir Sementsov-Ogievskiy (2):
docs: improve q
The patch add new additional field to qcow2 header: compression_type,
which specifies compression type. If field is absent or zero, default
compression type is set: ZLIB, which corresponds to current behavior.
New compression type (ZSTD) is to be added in further commit.
Suggested-by: Denis Plotn
Make it more obvious how to add new fields to the version 3 header and
how to interpret them.
The specification is adjusted so for new defined optional fields:
1. Software may support some of these optional fields and ignore the
others, which means that features may be backported to downstream
On 16/12/2019 13.15, Christian Borntraeger wrote:
[...]
> I just learned from Peter that booting SCSI also has no BOOT_IMAGE (as
> we have no menu). So Thomas, can you find out the use case for the initial
> bug report. That might give an indication on how to proceed for all cases.
Apparently thi
Fixed in v4.2.0.
** Changed in: qemu
Status: Fix Committed => Fix Released
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https://bugs.launchpad.net/bugs/1844814
Title:
trace: SystemTap documentation out of date
Status in
Fixed in v4.2.0 (commits abc7cf3655 & 10f9f1fbed).
** Changed in: qemu
Status: Fix Committed => Fix Released
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https://bugs.launchpad.net/bugs/1844817
Title:
trace: dynamic widt
On 16/12/19 13:08, Thomas Huth wrote:
>> windows crossbuilds:
>> CC chardev/char-serial.o
>> CC chardev/char-socket.o
>> CC chardev/char-stdio.o
>> CC chardev/char-udp.o
>> CC chardev/char-win.o
>> make: *** No rule to make target
>> '/home/petmay01/qemu-for-merge
On Fri, Dec 6, 2019 at 3:41 PM Filip Bozuta wrote:
>
> The scripts checkpatch.pl located in scripts folder
> was used to check for errors and warnings in fllowing
> mips machines:
>
> Jazz
> Malta
> Mipssim
> R4000
> Fulong 2E
> Boston
>
> All generated errors and warnings
On Tue, Dec 10, 2019 at 1:57 PM Aleksandar Markovic
wrote:
>
> From: Aleksandar Markovic
>
> v2->v3:
>
> - changed patches 2, 3, 4 on Philippe's request
> - add a patch on including acceptance test in MIPS section
>
> v1->v2:
>
> - removed patch on new git infrastructure section
> - added
From: Filip Bozuta
The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
hw/mips/mips_fulong2e.c
hw/isa/vt82c686.c
hw/pci-host/bonito.c
include/hw/isa/vt82c686.h
These mips Fulong 2E machine files were edited and
all the errors a
From: Filip Bozuta
The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
hw/mips/mips_mipssim.c
hw/net/mipsnet.c
All these mips mipssim machine files were edited and
all the errors and warrings generated by the checkpatch.pl
script were
From: Aleksandar Markovic
File tests/acceptance/linux_ssh_mips_malta.py is crucial for
entire MIPS platform, so add it to the MIPS section. The
maintainership will be shared with others.
Signed-off-by: Aleksandar Markovic
Message-Id: <1575982519-29852-6-git-send-email-aleksandar.marko...@rt-rk.
From: Filip Bozuta
The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
hw/mips/mips_jazz.c
hw/display/jazz_led.c
hw/dma/rc4030.c
All these mips jazz machine files were edited and
all the errors and warrings generated by the checkpa
From: Filip Bozuta
The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
hw/mips/mips_malta.c
hw/mips/gt64xxx_pci.c
tests/acceptance/linux_ssh_mips_malta.py
All these mips malta machine files were edited and
all the errors and warrin
From: Filip Bozuta
The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in file:
hw/mips/mips_r4k.c
This mips r4000 machine file was edited and
all the errors and warrings generated by the checkpatch.pl
script were corrected and then the script was
r
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