From: Suraj Jitindar Singh
The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.
This register can only be written by the hypervisor, and cannot be read.
Signed-off-by: Suraj Jitindar Singh
Reviewed-by: David Gibson
Signed-off-by: Cé
The privileged message send and clear instructions (msgsndp & msgclrp)
are privileged, but will generate a hypervisor facility unavailable
exception if not enabled in the HFSCR and executed in privileged
non-hypervisor state.
Add checks when accessing the DPDES register and when using the
msgsndp
Hello,
This is a resend of Suraj's series adding KVM support to the QEMU
PowerNV machine under TCG :
http://patchwork.ozlabs.org/cover/1094658/
I have addressed the comments and kept for later the final patch
adding partition scoped radix tree translation. I need to educate
myself a bit more
From: Suraj Jitindar Singh
Privileged message send facilities exist on POWER8 processors and
later and include a register and instructions which can be used to
generate, observe/modify the state of and clear privileged doorbell
exceptions as described below.
The Directed Privileged Doorbell Exce
From: Suraj Jitindar Singh
According to the ISA the root page directory size of a radix tree for
either process or partition scoped translation must be >= 5.
Thus add this to the list of conditions checked when validating the
partition table entry in validate_pate();
Signed-off-by: Suraj Jitind
On 11/28/19 13:45, Daniel P. Berrangé wrote:
> On Thu, Nov 28, 2019 at 01:36:58PM +0100, Cornelia Huck wrote:
>> The Posix implementation of guest-set-time invokes hwclock to
>> set/retrieve the time to/from the hardware clock. If hwclock
>> is not available, the user is currently informed that "hw
On 28/11/19 06:57, Cameron Esfahani wrote:
>
> What we were seeing was, under heavy loads, running many concurrent
macOS VMs, that we would get spurious interrupts. Tracking it down, we
discovered that VMCS_INTR_T_SWINTR was getting injected when
VMCS_INTR_T_HWINTR was expected.
>
> If I take ou
I will rename them.
On Thu, Nov 28, 2019 at 3:41 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Thursday, November 28, 2019, Philippe Mathieu-Daudé
> wrote:
>
>> On 11/28/19 2:25 PM, Michael Rolnik wrote:
>>
>>> I don't see why you say that the peripherals are inside the c
On 28.11.19 12:24, Vladimir Sementsov-Ogievskiy wrote:
> 28.11.2019 13:52, Max Reitz wrote:
>> On 28.11.19 10:31, Vladimir Sementsov-Ogievskiy wrote:
>>> 27.11.2019 16:15, Max Reitz wrote:
This enum will supplement BdrvChildClass when it comes to what role (or
combination of roles) a chil
I do have a ARM HPC compiler license which I assume includes the armpl
blobs that came with it. You can email me directly at my Linaro email
(alex.ben...@linaro.org) if you don't want to upload the test case here.
--
You received this bug notification because you are a member of qemu-
devel-ml, w
On 26/11/19 21:04, Cameron Esfahani wrote:
> Our test case was booting many concurrent macOS VMs under heavy
> system load. I don't know if I could create one to replicate that.
Does this work?
diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c
index 1485b95776..26c6c3a49f 100644
-
On 28/11/19 14:56, Paolo Bonzini wrote:
> On 26/11/19 21:04, Cameron Esfahani wrote:
>> Our test case was booting many concurrent macOS VMs under heavy
>> system load. I don't know if I could create one to replicate that.
>
> Does this work?
>
> diff --git a/target/i386/hvf/x86hvf.c b/target/i38
On Thu, 28 Nov 2019 12:50:36 +0100
Markus Armbruster wrote:
> Tao Xu writes:
>
> > From: Liu Jingqi
> >
> > Add -numa hmat-cache option to provide Memory Side Cache Information.
> > These memory attributes help to build Memory Side Cache Information
> > Structure(s) in ACPI Heterogeneous Memor
Signed-off-by: Boris Fiuczynski
Reviewed-by: Eric Farman
---
hw/vfio/ccw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c
index 6863f6c69f..3b5520ae75 100644
--- a/hw/vfio/ccw.c
+++ b/hw/vfio/ccw.c
@@ -102,7 +102,7 @@ again:
if (errno =
On 11/28/19 2:46 PM, Michael Rolnik wrote:
I will rename them.
Please wait comments from Richard before a version respin.
On Thu, Nov 28, 2019 at 3:41 PM Aleksandar Markovic
mailto:aleksandar.m.m...@gmail.com>> wrote:
[...]
If I understand Aleksandar correctly, the naming is incor
On 20/11/2019 12.43, Janosch Frank wrote:
> Handling of CPU reset and setting of the IPL psw from guest storage at
> offset 0 is done by a Ultravisor call. Let's only fetch it if
> necessary.
>
> Signed-off-by: Janosch Frank
> ---
> hw/s390x/pv.c | 5 +
> hw/s390x/pv.h
On Thu, Nov 28, 2019 at 01:33 PM +0100, Claudio Imbrenda
wrote:
> The existing s390 bios gets the LOADPARM information from the system using
> an SCLP call that specifies a buffer length too small to contain all the
> output.
>
> The recent fixes in the SCLP code have exposed this bug, since now
Am 27.11.2019 um 14:15 hat Max Reitz geschrieben:
> This enum will supplement BdrvChildClass when it comes to what role (or
> combination of roles) a child takes for its parent.
>
> Because empty enums are not allowed, let us just start with it filled.
>
> Signed-off-by: Max Reitz
> ---
> inclu
On Wed, Nov 27, 2019 at 03:51:56PM +0400, Marc-André Lureau wrote:
> Add a function to be called when a graphic update is done.
>
> Declare the QXL renderer as async: render_update_cookie_num counts the
> number of outstanding updates, and graphic_hw_update_done() is called
> when it reaches none.
Vladimir Sementsov-Ogievskiy writes:
> Error **errp is almost always OUT-argument: it's assumed to be NULL, or
> pointer to NULL-initialized pointer, or pointer to error_abort or
> error_fatal, for callee to report error.
>
> But very few functions instead get Error **errp as IN-argument:
> it's
On 20/11/2019 12.43, Janosch Frank wrote:
> When a guest has saved a ipib of type 5 and call diagnose308 with
> subcode 10, we have to setup the protected processing environment via
> Ultravisor calls. The calls are done by KVM and are exposed via an API.
>
> The following steps are necessary:
> 1
Hi,
Setting up shared memory for vhost-user is a bit complicated from
command line, as it requires NUMA setup such as: m 4G -object
memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on -numa
node,memdev=mem.
Instead, I suggest to add a -mem-shared option for non-numa setups,
that will ma
On 20/11/2019 12.43, Janosch Frank wrote:
> For protected guests the IPIB is written/read to/from the sattelite
satellite
> block, so we need to make those accesses virtual to make them go
> through KBM mem ops.
What's KBM ?
> Signed-off-by: Janosch Frank
> ---
> target/s390x/diag.c | 26
Refactor qemu_memfd_alloc() to simply return the opened fd.
mmap() can be done later by the caller.
Signed-off-by: Marc-André Lureau
---
include/qemu/memfd.h | 3 +++
util/memfd.c | 39 +--
2 files changed, 28 insertions(+), 14 deletions(-)
diff --g
On Thu, Nov 28, 2019 at 01:49:32PM +0100, Cornelia Huck wrote:
> On Thu, 28 Nov 2019 12:45:32 +
> Daniel P. Berrangé wrote:
>
> > On Thu, Nov 28, 2019 at 01:36:58PM +0100, Cornelia Huck wrote:
> > > The Posix implementation of guest-set-time invokes hwclock to
> > > set/retrieve the time to/f
On 11/28/19 3:07 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> When a guest has saved a ipib of type 5 and call diagnose308 with
>> subcode 10, we have to setup the protected processing environment via
>> Ultravisor calls. The calls are done by KVM and are exposed via an API
28.11.2019 17:23, Markus Armbruster wrote:
> Vladimir Sementsov-Ogievskiy writes:
>
>> Error **errp is almost always OUT-argument: it's assumed to be NULL, or
>> pointer to NULL-initialized pointer, or pointer to error_abort or
>> error_fatal, for callee to report error.
>>
>> But very few functi
FWIW -p 65536 doesn't trigger anything although I wouldn't trust -p too
much:
env
LD_LIBRARY_PATH=/opt/arm/armpl-19.3.0_ThunderX2CN99_Ubuntu-16.04_arm-hpc-compiler_19.3_aarch64-linux/lib/:/opt/arm/arm-hpc-compiler-19.3_Generic-AArch64_Ubuntu-16.04_aarch64-linux/lib/
~/lsrc/qemu.git/aarch64-linux
Add an option to simplify shared memory / vhost-user setup.
Currently, using vhost-user requires NUMA setup such as:
-m 4G -object memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on
-numa node,memdev=mem
As there is no other way to allocate shareable RAM, afaik.
-mem-shared aims to h
On Wednesday, November 27, 2019, Michael Rolnik wrote:
> This series of patches adds 8bit AVR cores to QEMU.
> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
> tested yet.
> However I was able to execute simple code with functions. e.g fibonacci
> calculation.
> This serie
On 28.11.19 14:16, Cornelia Huck wrote:
> On Thu, 28 Nov 2019 14:11:38 +0100
> Thomas Huth wrote:
>
>> On 28/11/2019 13.35, Christian Borntraeger wrote:
>>> Ack.
>>>
>>> Conny, I think this would be really nice to have for 4.2 (together with a
>>> bios rebuild)
>>> as this fixes a regression.
28.11.2019 12:36, Andrey Shinkevich wrote:
> Allow writing all the data compressed through the filter driver.
> The written data will be aligned by the cluster size.
> Based on the QEMU current implementation, that data can be written to
> unallocated clusters only. May be used for a backup job.
>
On 11/28/19 3:30 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> Handling of CPU reset and setting of the IPL psw from guest storage at
>> offset 0 is done by a Ultravisor call. Let's only fetch it if
>> necessary.
>>
>> Signed-off-by: Janosch Frank
>> ---
>> hw/s390x/pv.c
On Thursday, November 28, 2019, Philippe Mathieu-Daudé
wrote:
> On 11/28/19 2:46 PM, Michael Rolnik wrote:
>
>> I will rename them.
>>
>
>>
Renaming alone won't solve anything.
> Please wait comments from Richard before a version respin.
>
> On Thu, Nov 28, 2019 at 3:41 PM Aleksandar Markovic <
On Thu, Nov 28, 2019 at 03:10:16PM +, Wasim, Bilal wrote:
> [PATCH] Updating the GEM MAC IP to properly filter out the multicast
> addresses. The current code makes a bad assumption that the most-significant
> byte of the MAC address is used to determine if the address is multicast or
> unicast
Hi Laszlo,
Do you have a particular reason to update the submodule *after* the v4.2.0
release?
I'd rather see QEMU 4.2 released with edk2-stable201911, as it fixes various
CVE (therefore a patch for 4.2-rc4 seems acceptable to me).
--
You received this bug notification because you are a member
On 11/28/19 3:30 PM, Boris Fiuczynski wrote:
Signed-off-by: Boris Fiuczynski
Reviewed-by: Eric Farman
---
hw/vfio/ccw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c
index 6863f6c69f..3b5520ae75 100644
--- a/hw/vfio/ccw.c
+++ b/hw/vfio/ccw.
Hi; this is a question which came up in Damien's reset series
which I don't know the answer to:
What is the interaction of the QOM device lifecycle (instance_init/realize/
unrealize/instance_finalize) with hotplug and hot-unplug ? I couldn't
find any documentation of this but maybe I was looking i
On Thu, 28 Nov 2019 at 12:48, Christian Borntraeger
wrote:
>
>
>
> On 28.11.19 13:45, Cornelia Huck wrote:
> > On Thu, 28 Nov 2019 13:35:29 +0100
> > Christian Borntraeger wrote:
> >
> >> Ack.
> >>
> >> Conny, I think this would be really nice to have for 4.2 (together with a
> >> bios rebuild)
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and that HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.
Tested with a hacked-up version o
It's now possible to run some TCG-based tests with our Tiny Code
Generator Interpreter (TCI), too. These two patches enable the
testing on Travis.
Alex Bennée (1):
configure: allow disable of cross compilation containers
Thomas Huth (1):
travis.yml: Run tcg tests with tci
.travis.yml
> On Nov 27, 2019, at 11:58 PM, Alexey Kardashevskiy wrote:
>
>
>
> On 26/11/2019 20:39, Felipe Franciosi wrote:
>>
>>
>>> On Nov 26, 2019, at 8:39 AM, Marc-André Lureau
>>> wrote:
>>>
>>> Hi
>>
>> Heya, thanks for the review.
>>
>>>
>>> On Mon, Nov 25, 2019 at 7:37 PM Felipe Francios
[PATCH] Updating the GEM MAC IP to properly filter out the multicast
addresses. The current code makes a bad assumption that the most-significant
byte of the MAC address is used to determine if the address is multicast or
unicast, but in reality only a single bit is used to determine this. This
cau
If you objdump the binary and the offending library what do they seem to
have been built for ?
Certainly this:
0040-00401000 1000 ---
looks like a 4K page when we're trying to load things, so either we got
the loading wrong or the binary is 4K.
--
You received t
On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
>
> I started looking the rest of the missing TIDx handling,
> and this resulted in the following patches.
>
> There is still one thing I'm a bit puzzled by though:
>
> HCR_EL2.TID0 mandates trapping of the AArch32 JIDR
> register, but I couldn't f
On 20/11/2019 12.43, Janosch Frank wrote:
> IO instruction data is routed through SIDAD for protected guests, so
> adresses do not need to be checked, as this is kernel memory.
>
> Signed-off-by: Janosch Frank
> ---
> target/s390x/ioinst.c | 46 +++
> 1 fi
I started looking the rest of the missing TIDx handling,
and this resulted in the following patches.
There is still one thing I'm a bit puzzled by though:
HCR_EL2.TID0 mandates trapping of the AArch32 JIDR
register, but I couldn't find a trace of it in the QEMU
code, and trying to read it seems t
On 11/28/19 3:40 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> For protected guests the IPIB is written/read to/from the sattelite
>
> satellite
>
>> block, so we need to make those accesses virtual to make them go
>> through KBM mem ops.
>
> What's KBM ?
A totally new h
On 20/11/2019 12.43, Janosch Frank wrote:
> Status storing is obviously not done by qemu anymore.
>
> Signed-off-by: Janosch Frank
> ---
> target/s390x/sigp.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
> index 2ce22d
On 11/28/19 5:18 PM, Cornelia Huck wrote:
> On Thu, 28 Nov 2019 17:10:38 +0100
> Janosch Frank wrote:
>
>> On 11/28/19 4:28 PM, Thomas Huth wrote:
>
>>> Would it make sense to hide all these changes in decode_basedisp_s()
>>> instead? ... so that decode_basedisp_s() returns 0 if env->pv == true
On Thu, Nov 28, 2019 at 06:15:16PM +0400, Marc-André Lureau wrote:
> Hi,
>
> Setting up shared memory for vhost-user is a bit complicated from
> command line, as it requires NUMA setup such as: m 4G -object
> memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on -numa
> node,memdev=mem.
>
Several objects implemented their own uint property getters and setters,
despite them being straightforward (without any checks/validations on
the values themselves) and identical across objects. This makes use of
an enhanced API for object_property_add_uintXX_ptr() which offers
default setters.
S
From: Alex Bennée
Our docker infrastructure isn't quite as multiarch as we would wish so
lets allow the user to disable it if they want. This will allow us to
use still run check-tcg on non-x86 CI setups.
Signed-off-by: Alex Bennée
---
configure | 8 +++-
tests/tcg/configure.s
On 28.11.19 17:08, Janosch Frank wrote:
> On 11/28/19 3:40 PM, Thomas Huth wrote:
>> On 20/11/2019 12.43, Janosch Frank wrote:
>>> For protected guests the IPIB is written/read to/from the sattelite
>>
>> satellite
>>
>>> block, so we need to make those accesses virtual to make them go
>>> through
On 28.11.19 15:12, Kevin Wolf wrote:
> Am 27.11.2019 um 14:15 hat Max Reitz geschrieben:
>> This enum will supplement BdrvChildClass when it comes to what role (or
>> combination of roles) a child takes for its parent.
>>
>> Because empty enums are not allowed, let us just start with it filled.
>>
So far we only have compile coverage for tci. But since commit
2f160e0f9797c7522bfd0d09218d0c9340a5137c ("tci: Add implementation
for INDEX_op_ld16u_i64") has been included now, we can also run the
"tcg" and "qtest" tests with tci, so let's enable them in Travis now.
Since we don't gain much additi
+Igor
On Thu, Nov 28, 2019 at 06:15:18PM +0400, Marc-André Lureau wrote:
> Add an option to simplify shared memory / vhost-user setup.
>
> Currently, using vhost-user requires NUMA setup such as:
> -m 4G -object memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on
> -numa node,memdev=me
Traditionally, the uint-specific property helpers only offer getters.
When adding object (or class) uint types, one must therefore use the
generic property helper if a setter is needed (and probably duplicate
some code writing their own getters/setters).
This enhances the uint-specific property he
On 11/28/19 4:28 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> IO instruction data is routed through SIDAD for protected guests, so
>> adresses do not need to be checked, as this is kernel memory.
>>
>> Signed-off-by: Janosch Frank
>> ---
>> target/s390x/ioinst.c | 46
On Thu, 28 Nov 2019 18:15:18 +0400
Marc-André Lureau wrote:
> Add an option to simplify shared memory / vhost-user setup.
>
> Currently, using vhost-user requires NUMA setup such as:
> -m 4G -object memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on
> -numa node,memdev=mem
>
> As th
On Thu, 28 Nov 2019 16:00:06 +
Peter Maydell wrote:
> Hi; this is a question which came up in Damien's reset series
> which I don't know the answer to:
>
> What is the interaction of the QOM device lifecycle (instance_init/realize/
> unrealize/instance_finalize) with hotplug and hot-unplug ?
On Thu, Nov 28, 2019 at 04:00:06PM +, Peter Maydell wrote:
> Hi; this is a question which came up in Damien's reset series
> which I don't know the answer to:
>
> What is the interaction of the QOM device lifecycle (instance_init/realize/
> unrealize/instance_finalize) with hotplug and hot-unp
On 11/28/19 4:28 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> IO instruction data is routed through SIDAD for protected guests, so
>> adresses do not need to be checked, as this is kernel memory.
>>
>> Signed-off-by: Janosch Frank
>> ---
>> target/s390x/ioinst.c | 46
On Thu, Nov 28, 2019 at 05:02:00PM +, Wasim, Bilal wrote:
> This was one of my first attempts, and so I was sure to miss something.. I've
> incorporated all the updates in this patch.. Let me know what you think about
> this..
>
> net/cadence_gem: Updating the GEM MAC IP to properly filter
On 2019-11-28 16:30, Peter Maydell wrote:
On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
I started looking the rest of the missing TIDx handling,
and this resulted in the following patches.
There is still one thing I'm a bit puzzled by though:
HCR_EL2.TID0 mandates trapping of the AArch32
HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
completely ignores it, making impossible for hypervisors to
virtualize the cache hierarchy.
Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set.
Signed-off-b
On Tue, 12 Nov 2019 11:48:11 +0100
Cornelia Huck wrote:
> Add 5.0 machine types for arm/i440fx/q35/s390x/spapr.
>
> For i440fx and q35, unversioned cpu models are still translated
> to -v1; I'll leave changing this (if desired) to the respective
> maintainers.
>
> Signed-off-by: Cornelia Huck
On 11/21/19 4:11 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> Secure guests no longer intercept with code 4 for an instruction
>> interception. Instead they have codes 104 and 108 for secure
>> instruction interception and secure instruction notification
>> respectively.
>>
HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1
(and their 32bit equivalents) as well as TCMTR, TLBTR are trapped
to EL2. QEMU ignores it, naking it harder for a hypervisor to
virtualize the HW (though to be fair, no known hypervisor actually
cares).
Do the right thing by trappi
On Thu, 28 Nov 2019 07:32:53 +0100
Thomas Huth wrote:
> On 27/11/2019 18.50, Janosch Frank wrote:
> > Let's start moving the cpu reset functions into a single function with
> > a switch/case, so we can use fallthroughs and share more code between
> > resets.
>
> Nit: I'd add a "later" in above
On Thu, 28 Nov 2019 17:10:38 +0100
Janosch Frank wrote:
> On 11/28/19 4:28 PM, Thomas Huth wrote:
> > Would it make sense to hide all these changes in decode_basedisp_s()
> > instead? ... so that decode_basedisp_s() returns 0 if env->pv == true ?
> > ... or are there still cases where we need re
This improves the family of object_property_add_uintXX_ptr helpers by enabling
a default getter/setter only when desired. To prevent an API behavioural change
(from clients that already used these helpers and did not want a setter), we
add a OBJ_PROP_FLAG_RD flag that allow clients to only have a g
Patchew URL:
https://patchew.org/QEMU/20191128064350.20727-1-aaron.zakh...@gmail.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
Yes, I do have a reason for delaying this LP until after 4.2.0 is out.
When I filed this ticket (on 2019-Nov-12), QEMU had already entered the
4.2.0 soft feature freeze (on 2019-Oct-29). Despite possible
appearances, this LP is actually a feature addition -- that's why I also
set "Tags: feature-re
Currently, ich9_lpc_initfn simply serves as a caller to
ich9_lpc_add_properties. This simplifies the code a bit by eliminating
ich9_lpc_add_properties altogether and executing its logic in the parent
object initialiser function.
Signed-off-by: Felipe Franciosi
---
hw/isa/lpc_ich9.c | 15 +---
Aleksandar Markovic writes:
> On Thursday, November 28, 2019, Michael Rolnik wrote:
>
>> I don't see why you say that the peripherals are inside the chip, there is
>> CPU within target/avr directory and then there are some peripherals in hw
>> directory, CPU does not depend on them. what am I
Do binaries have to be page size aware? I thought it was a runtime thing.
However if the aarch64-linux-user is hardwired to 4k it might explain it's
confusion on a 64k machine.
On Thu, 28 Nov 2019, 16:33 Peter Maydell, wrote:
> If you objdump the binary and the offending library what do they see
Hi Peter,
Thanks for having a look at this.
On 2019-11-28 16:43, Peter Maydell wrote:
On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and that HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, i
On Thu, 28 Nov 2019 at 17:49, Marc Zyngier wrote:
>
> Hi Peter,
>
> Thanks for having a look at this.
>
> On 2019-11-28 16:43, Peter Maydell wrote:
> > On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
> >>
> >> HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
> >> EL2, and th
On Thu, Nov 28, 2019 at 05:48:00PM +0100, Halil Pasic wrote:
> On Tue, 19 Nov 2019 18:50:03 -0600
> Michael Roth wrote:
>
> [..]
> > I.e. the calling code is only scheduling a one-shot BH for
> > virtio_blk_data_plane_stop_bh, but somehow we end up trying to process
> > an additional virtqueue en
The Posix implementation of guest-set-time invokes hwclock to
set/retrieve the time to/from the hardware clock. If hwclock
is not available, the user is currently informed that "hwclock
failed to set hardware clock to system time", which is quite
misleading. This may happen e.g. on s390x, which has
On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
>
> HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
> EL2, and that HCR_EL2.TID0 does the same for reads of FPSID.
> In order to handle this, introduce a new TCG helper function that
> checks for these control bits before execu
On Thu, 28 Nov 2019 15:30:14 +0100
Boris Fiuczynski wrote:
> Signed-off-by: Boris Fiuczynski
> Reviewed-by: Eric Farman
> ---
> hw/vfio/ccw.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c
> index 6863f6c69f..3b5520ae75 100644
> --- a/hw
On Thu, 28 Nov 2019 17:38:19 +0100
Janosch Frank wrote:
> On 11/21/19 4:11 PM, Thomas Huth wrote:
> > On 20/11/2019 12.43, Janosch Frank wrote:
> >> Secure guests no longer intercept with code 4 for an instruction
> >> interception. Instead they have codes 104 and 108 for secure
> >> instructio
Hi Cornelia,
On 11/28/19 19:11, Cornelia Huck wrote:
> The Posix implementation of guest-set-time invokes hwclock to
> set/retrieve the time to/from the hardware clock. If hwclock
> is not available, the user is currently informed that "hwclock
> failed to set hardware clock to system time", which
On Wed, 27 Nov 2019 19:38:06 +0100
Janosch Frank wrote:
> On 11/27/19 7:25 PM, Janosch Frank wrote:
> >
> > There's 0 (initiated), busy and operational and as far as I know we
> > implement neither.
>
> That came out wrong...
> s/operational/not operational/
>
> We only implement "command in
On Tue, 19 Nov 2019 18:50:03 -0600
Michael Roth wrote:
[..]
> I.e. the calling code is only scheduling a one-shot BH for
> virtio_blk_data_plane_stop_bh, but somehow we end up trying to process
> an additional virtqueue entry before we get there. This is likely due
> to the following check in vir
Thanks for the pointers.. I will incorporate all these changes and post an
updated thread asap..
-Original Message-
From: Edgar E. Iglesias [mailto:edgar.igles...@gmail.com]
Sent: Thursday, November 28, 2019 10:32 PM
To: Wasim, Bilal
Cc: qemu-devel@nongnu.org; alist...@alistair23.me; p
When QOM APIs were added to ich9 in 6f1426ab, the getter for sci_int was
written using uint32_t. However, the object property is uint8_t. This
fixes the getter for correctness.
Signed-off-by: Felipe Franciosi
---
hw/isa/lpc_ich9.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff
On Thursday, November 28, 2019, Alex Bennée wrote:
>
> Aleksandar Markovic writes:
>
> > On Thursday, November 28, 2019, Michael Rolnik
> wrote:
> >
> >> I don't see why you say that the peripherals are inside the chip, there
> is
> >> CPU within target/avr directory and then there are some per
On Thu, 28 Nov 2019 at 17:27, Igor Mammedov wrote:
>
> On Thu, 28 Nov 2019 16:00:06 +
> Peter Maydell wrote:
> > Once a device is hot-unplugged (and thus unrealized) is it valid
> > for it to be re-hot-plugged, or is the assumption that it's then
> > destroyed and a fresh device is created if
The CPU_LOG_PAGE flag is woefully underused and could stand to do
extra duty tracking page changes. If the user doesn't want to see the
details as things change they still have the tracepoints available.
Signed-off-by: Alex Bennée
---
linux-user/mmap.c | 11 +++
1 file changed, 7 inserti
For full details we also want to see where the mmaps end up.
Signed-off-by: Alex Bennée
---
linux-user/mmap.c | 2 +-
linux-user/trace-events | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index c81fd85fbd2..a2c7037f1b6 100644
---
This was one of my first attempts, and so I was sure to miss something.. I've
incorporated all the updates in this patch.. Let me know what you think about
this..
net/cadence_gem: Updating the GEM MAC IP to properly filter out the multicast
addresses.
The current code makes a bad assumption t
On Thursday, November 28, 2019, Philippe Mathieu-Daudé
wrote:
> On 11/28/19 2:46 PM, Michael Rolnik wrote:
>
>> I will rename them.
>>
>
> Please wait comments from Richard before a version respin.
>
>
Everything went well last 10 or so days, Michael and Sarah were responsive,
the code and series
On 28/11/2019 17.10, Janosch Frank wrote:
> On 11/28/19 4:28 PM, Thomas Huth wrote:
>> On 20/11/2019 12.43, Janosch Frank wrote:
>>> IO instruction data is routed through SIDAD for protected guests, so
>>> adresses do not need to be checked, as this is kernel memory.
>>>
>>> Signed-off-by: Janosch
* Marc-André Lureau (marcandre.lur...@redhat.com) wrote:
> Hi,
>
> Setting up shared memory for vhost-user is a bit complicated from
> command line, as it requires NUMA setup such as: m 4G -object
> memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on -numa
> node,memdev=mem.
>
> Instead
On 11/28/19 5:45 PM, Cornelia Huck wrote:
> On Thu, 28 Nov 2019 17:38:19 +0100
> Janosch Frank wrote:
>
>> On 11/21/19 4:11 PM, Thomas Huth wrote:
>>> On 20/11/2019 12.43, Janosch Frank wrote:
Secure guests no longer intercept with code 4 for an instruction
interception. Instead they
Hi
On Thu, Nov 28, 2019 at 9:25 PM Igor Mammedov wrote:
>
> On Thu, 28 Nov 2019 18:15:18 +0400
> Marc-André Lureau wrote:
>
> > Add an option to simplify shared memory / vhost-user setup.
> >
> > Currently, using vhost-user requires NUMA setup such as:
> > -m 4G -object memory-backend-file,id=me
Am 28.11.19 um 16:35 schrieb Thomas Huth:
> From: Alex Bennée
>
> Our docker infrastructure isn't quite as multiarch as we would wish so
> lets allow the user to disable it if they want. This will allow us to
s/lets/let's/ ?
Otherwise fine, thank you.
Reviewed-by: Stefan Weil
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