The TILE-Gx architecture was missing its section, add it.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ca814850e..a3be0a4a31 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -299,6 +299,11 @@ F: hw/sp
On 10/11/19 6:05 PM, Vladimir Sementsov-Ogievskiy wrote:
If we want to add some info to errp (by error_prepend() or
error_append_hint()), we must use the ERRP_AUTO_PROPAGATE macro.
Otherwise, this info will not be added when errp == &fatal_err
(the program will exit prior to the error_append_hint
The Status description has a mix of tabs and spaces and displays
unaligned. Unify using spaces.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ca814850e..b9093e4dac 1006
Hi Pavel,
On 8/27/19 11:29 AM, Pavel Dovgalyuk wrote:
From: Alex Bennée [mailto:alex.ben...@linaro.org]
Richard Henderson writes:
On 8/26/19 2:23 AM, Alex Bennée wrote:
Are there any compilers available so we can add the multiarch tests to
"check-tcg"?
Debian has a gcc-avr package.
Look
On 8/27/19 12:59 PM, Sarah Harris wrote:
I don't mind if you want to drop my signed-off-by for commits that were based
on Michael's work.
You probably want to keep my sign-off for the USART/timer commit though as that
was new code.
Linux offers a Co-developed-by, some QEMU developers started
Hi Sarah,
On 5/10/19 1:17 PM, Sarah Harris wrote:
Hi Richard,
Having discussed with my colleagues, we don't have the resources to maintain
this.
If you wanted to take up Michael's offer then I'm happy to respond to queries
and provide minor fixes.
Otherwise, we will make our repository public
Patchew URL:
https://patchew.org/QEMU/20191012024748.127135-1-xiaoyao...@intel.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN =
On Sat, Sep 14, 2019 at 03:40:41PM -0400, Michael S. Tsirkin wrote:
>On Fri, Sep 13, 2019 at 11:47:46PM +, Wei Yang wrote:
>> On Tue, Jul 30, 2019 at 08:37:38AM +0800, Wei Yang wrote:
>> >When we iterate the memory-device list to get the available range, it is not
>> >necessary to iterate the w
Philippe introduced a series of helpers to make the
device class_init() easier to understand when a
device class change the parent hooks, device pc87312
missed helper, so convert it.
Cc: hpous...@reactos.org
Cc: f4...@amsat.org
Signed-off-by: Mao Zhongyi
---
hw/isa/pc87312.c | 3 +--
1 file chan
Philippe introduced a series of helpers to make the
device class_init() easier to understand when a device
class change the parent hooks, some devices in the
source tree missed helper, so convert it.
Cc: eric.au...@redhat.com
Cc: peter.mayd...@linaro.org
Cc: hpous...@reactos.org
Cc: f4...@amsat.or
Philippe introduced a series of helpers to make the
device class_init() easier to understand when a
device class change the parent hooks, device smmuv3
missed helper, so convert it.
Cc: eric.au...@redhat.com
Cc: peter.mayd...@linaro.org
Cc: f4...@amsat.org
Signed-off-by: Mao Zhongyi
---
hw/arm/s
u-openbios-20191012
for you to fetch changes up to 25bf1811cffc2772fedaa9345026cb5375ae11b4:
Update OpenBIOS images to f28e16f9 built from submodule. (2019-10-12 10:18:18
+0100)
qemu-open
On Sat, 2019-10-12 at 01:56 -0700, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20191012024748.127135-1-xiaoyao...@intel.com/
>
>
>
> Hi,
>
> This series failed the docker-mingw@fedora build test. Please find the testing
> commands and
> their output below. If you have
12.10.2019. 09.16, "Philippe Mathieu-Daudé" је
написао/ла:
>
> The Status description has a mix of tabs and spaces and displays
> unaligned. Unify using spaces.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-
Cooper Lake is intel's successor to Cascade Lake, the new
CPU model inherits features from Cascadelake-Server, while
add one platform associated new feature: AVX512_BF16, and
STIBP for speculative execution.
Signed-off-by: Cathy Zhang
---
target/i386/cpu.c | 59 ++
This patchset is to add CPU model for intel processor Cooper Lake. It
will inherit features from the existing CPU model Cascadelake-Server,
meanwhile, add the platform associated new instruction and feature
for speculative execution which the host supports. There are associated
feature bit and ma
stibp feature is already added through the following commit.
https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955
Add a macro for it to allow CPU models report it when host supports.
Signed-off-by: Cathy Zhang
---
target/i386/cpu.h | 1 +
1 file changed, 1 insertion(+)
Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow
CPU models to report the feature when host supports it.
Signed-off-by: Cathy Zhang
---
target/i386/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index eaa5395..e757149 100644
-
12.10.2019. 09.31, "Philippe Mathieu-Daudé" је
написао/ла:
>
> Hi Sarah,
>
>
> On 5/10/19 1:17 PM, Sarah Harris wrote:
>>
>> Hi Richard,
>>
>> Having discussed with my colleagues, we don't have the resources to
maintain this.
>> If you wanted to take up Michael's offer then I'm happy to respond to
12.10.2019. 09.12, "Philippe Mathieu-Daudé" је
написао/ла:
>
> The TILE-Gx architecture was missing its section, add it.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 5 +
> 1 file changed, 5 insertions(+)
>
It is certainly good that there is a maintainer for each QEMU com
On Sat, Oct 12, 2019 at 07:40:30PM +0800, Xiaoyao Li wrote:
> On Sat, 2019-10-12 at 01:56 -0700, no-re...@patchew.org wrote:
> > Patchew URL:
> > https://patchew.org/QEMU/20191012024748.127135-1-xiaoyao...@intel.com/
> >
> >
> >
> > Hi,
> >
> > This series failed the docker-mingw@fedora build
On Thu, Sep 19, 2019 at 04:39:00PM +0100, Peter Maydell wrote:
> On Thu, 19 Sep 2019 at 16:37, Eric Blake wrote:
> >
> > On 9/19/19 10:22 AM, Peter Maydell wrote:
> >
> > > Alex looked at this and suggests the problem is probably because
> > > you're doing an in-tree build.
> >
> > Bingo. I thoug
On 12.10.2019 10:17, Philippe Mathieu-Daudé wrote:
Hi Pavel,
On 8/27/19 11:29 AM, Pavel Dovgalyuk wrote:
From: Alex Bennée [mailto:alex.ben...@linaro.org]
Richard Henderson writes:
On 8/26/19 2:23 AM, Alex Bennée wrote:
Are there any compilers available so we can add the multiarch
tests to
On Fri, 11 Oct 2019 19:03:55 +0300
Vladimir Sementsov-Ogievskiy wrote:
> Make error_append_security_model_hint and
> error_append_socket_sockfd_hint hint append helpers well formed:
> rename errp to errp_in, as it is IN-parameter here (which is unusual
> for errp).
>
> Signed-off-by: Vladimir Se
Patchew URL:
https://patchew.org/QEMU/1570863638-22272-1-git-send-email-cathy.zh...@intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/3] Add CPU model for intel processor Cooper Lake
Type: series
Message-id: 157086363
You can find my libvirt XML attached. Here is the full qemu command
(taken from the ps output):
/usr/bin/qemu-system-x86_64 -name guest=win10,debug-threads=on -S
-object
secret,id=masterKey0,format=raw,file=/var/lib/libvirt/qemu/domain-7-win10
/master-key.aes -machine pc-q35-3.1,accel=kvm,usb=off,
** Description changed:
Performing io intensive tasks on virtualized Windows causes the system
to visually stutter. I can often reproduce the problem by running fio on
windows:
fio --randrepeat=1 --ioengine=windowsaio --direct=1 --gtod_reduce=1
--name=test --filename=\\.\PhysicalDrive
I ran into the same problem on threadripper 1900X. I was using cpu type
"host-passthough" and it crashed. I fixed the crash by disabling the MSR
with
kvm.ignore_msrs=1
as describe in https://forum.level1techs.com/t/windows-10-1803-as-guest-
with-qemu-kvm-bsod-under-install/127425/10
--
You rece
Public bug reported:
Performing io intensive tasks on virtualized Windows causes the system
to visually stutter. I can often reproduce the problem by running fio on
windows:
fio --randrepeat=1 --ioengine=windowsaio --direct=1 --gtod_reduce=1
--name=test --filename=\\.\PhysicalDrive0 --bs=4k --iod
On Fri, Oct 11, 2019 at 11:56 PM Philippe Mathieu-Daudé
wrote:
>
> Not all ARM machines sections Cc the qemu-...@nongnu.org list,
> fix this.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> MAINTAINERS | 5 +
> 1 file changed, 5 insertions(+)
>
>
Hi Aleksandar.
If I break it to multiple patches, does every patch have to compile?
On Fri, Oct 11, 2019 at 5:13 PM Aleksandar Markovic
wrote:
>
>
>
> On Monday, September 2, 2019, Michael Rolnik wrote:
>>
>> This includes:
>> - TCG translations for each instruction
>>
>> Signed-off-by: Michael
On Wed, 25 Sep 2019 17:14:21 PDT (-0700), guo...@kernel.org wrote:
From: Guo Ren
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Pag
From: Aleksandar Markovic
Mostly cosmetic changes.
v2->v3:
- removed all patches that were already integrated
- patches 1 and 2 are improved from v2
- added patches 3-6
v1->v2:
- minor corrections to satisfy reviews
- added several more patches
Aleksandar Markovic (6):
target/mip
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 20 ++-
target/mips/msa_helper.c | 320 ++-
target/mips/translate.c | 76 +--
3 files change
From: Aleksandar Markovic
Aleksandar Rikalo wishes to change his primary mail address for QEMU.
Some minor line order is corrected in .mailmap to be alphabetical,
too.
Signed-off-by: Aleksandar Markovic
---
.mailmap| 5 +++--
MAINTAINERS | 18 +-
2 files changed, 12 insert
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 11 +++-
target/mips/msa_helper.c | 163 ++-
target/mips/translate.c | 38 +--
3 files chang
From: Aleksandar Markovic
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic
---
target/mips/op_helper.c | 1010 +++
1 file changed, 663 insertions(+), 347 deletions(-)
diff --git a/target/mips/op_helpe
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 21 +-
target/mips/msa_helper.c | 768 +--
target/mips/translate.c | 76 -
3 files changed, 496
From: Aleksandar Markovic
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.c | 128 +++
1 file changed, 78 insertions(+), 50 deletions(-)
diff --git a/target/mips/helper.c b
On Sat, Oct 12, 2019 at 6:34 PM Michael Rolnik wrote:
>
> Hi Aleksandar.
>
> If I break it to multiple patches, does every patch have to compile?
>
Micheal,
Well, it does. This is because people are using various automated or
semi-automated
"bisect" scripts when they want to find what commit cau
Patchew URL:
https://patchew.org/QEMU/1570901866-9548-1-git-send-email-aleksandar.marko...@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v3 0/6] target/mips: Misc cleanups for September/October 2019
Type: series
Me
No it doesn't mean that.
But the following code will make the size TARGET_PAGE_SIZE - (page offset)
if the address is not aligned.
pmp_size = -(address | TARGET_PAGE_MASK)
On Fri, Oct 11, 2019, 7:37 PM Jonathan Behrens wrote:
> How do you know that the access won't straddle a page boundary? Is
The patch didn't wrap the physical address space directly, just follow the spec.
I admit that I am trying to use the compliance specification to allow
qemu to support some non-standard software.
But compliance specification and wrapping the physical address space
are different things.
I'm preparing
There is nowhere in the spec that ever says what hardware has to do if
any of those reserved bits are non-zero. Hardware is certainly not
required to ignore them and treat the PTE as being valid (which is
what this patch does). I'd argue that since only buggy code would ever
set these bits, QEMU sh
Patch 1 simplify the definition of xxx_PAGE_ALIGN.
Patch 2 replaces getpagesize() with qemu_real_host_page_size. This one touch a
volume of code. If some point is not correct, I'd appreciate your
notification.
Wei Yang (2):
cpu: use ROUND_UP() to define xxx_PAGE_ALIGN
core: replace getpagesize
There are three page size in qemu:
real host page size
host page size
target page size
All of them have dedicate variable to represent. For the last two, we
use the same form in the whole qemu project, while for the first one we
use two forms: qemu_real_host_page_size and getpagesize().
qe
Use ROUND_UP() to define, which is a little bit easy to read.
Signed-off-by: Wei Yang
---
include/exec/cpu-all.h | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index ad9ab85eb3..255bb186ac 100644
--- a/include/exec/cpu-a
On Sun, Oct 13, 2019 at 10:11:44AM +0800, Wei Yang wrote:
> Use ROUND_UP() to define, which is a little bit easy to read.
>
> Signed-off-by: Wei Yang
Reviewed-by: Michael S. Tsirkin
> ---
> include/exec/cpu-all.h | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a
On Sun, Oct 13, 2019 at 10:11:45AM +0800, Wei Yang wrote:
> There are three page size in qemu:
>
> real host page size
> host page size
> target page size
>
> All of them have dedicate variable to represent. For the last two, we
> use the same form in the whole qemu project, while for the f
On Sun, Oct 13, 2019 at 10:11:43AM +0800, Wei Yang wrote:
> Patch 1 simplify the definition of xxx_PAGE_ALIGN.
> Patch 2 replaces getpagesize() with qemu_real_host_page_size. This one touch a
> volume of code. If some point is not correct, I'd appreciate your
> notification.
Pls queue at the triv
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