The patch allows to provide a pattern file for write
command. There was no similar ability before.
Signed-off-by: Denis Plotnikov
---
v8: fix according to Max's comments
* get rid of unnecessary buffer for the pattern
* buffer allocation just in bytes
* take into account the missalign offse
Ping!
On Jul 30 2019, at 5:45 pm, Denis Plotnikov wrote:
Hi all! Is there any other comments besides Markus's one about adding zlib/zstd
links to compressed cluster layout description?
On Jul 4 2019, at 4:09 pm, Denis Plotnikov wrote:
change log:
v2:
* relax the compression type setting restr
Adds scripting interface with python library to call functions in
python modules from Qemu that can be used to feed input externally
and without recompiling Qemu that can be used for early development,
testing and can be extended to abstract some of Qemu code out to a
python script to ease maintena
Existing xscom access emulation for read/write can be
extended with the python interface to support feeding
data externally.
Signed-off-by: Balamuruhan S
---
hw/ppc/pnv_xscom.c | 31 ---
include/sysemu/sysemu.h | 4
qemu-options.hx | 14
Hi All,
This is a proposal to extend mmio callbacks in Qemu with scripting interface
that is prototyped with python in this implementation. It gives ability to
feed runtime data through callbacks without recompiling Qemu in generic way.
This patchset adds library that provides APIs for Qemu to tal
homer and occ common area region base address are initialized
to create device tree and realized to map the address with
mmio callbacks during `pnv_chip_realize()`.
`SysBusNum` enum is introduced to set sysbus for XSCOM, ICP,
HOMER and OCC appropriately and chip_num to initialize and
retrieve base
Add mmio callback functions to enable homer/occ common area
to emulate pstate table, occ-sensors, slw, occ static and
dynamic values for Power8 and Power9 chips. It also works for
multiple chips as offset remains the same whereas the base
address are handled appropriately while initializing device
use python interface APIs in homer/occ common area emulation to
interact with scripts if provided else fallback to normal flow,
it shows how simple to use the interface to call python methods
with any number of arguments in any script placed in common
-module-path provided in qemu commandline.
Sig
During PowerNV boot skiboot populates the device tree by retrieving
base address of homer/occ common area from PBA BARs and prd ipoll
mask by accessing xscom read/write accesses.
Signed-off-by: Balamuruhan S
---
hw/ppc/pnv_xscom.c | 27 +++
1 file changed, 23 insertions(+
Patchew URL:
https://patchew.org/QEMU/20190807071445.4109-1-bal...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [RFC PATCH 0/6] Enhancing Qemu MMIO emulation with
scripting interface
Message
Ping
23.07.2019, 16:42, "Yury Kotov" :
> Hi,
>
> V4:
> * The test was simplified to prevent false fails.
>
> V3:
> * Rebase fixes (migrate_set_parameter -> migrate_set_parameter_int)
>
> V2:
> * Added a test
> * Fixed qemu_cond_timedwait for qsp
>
> I wrote a test for migration auto converge and f
As of today, the QEMU 'sifive_u' machine is a special target that does
not boot the upstream OpenSBI/U-Boot firmware images built for the real
SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
"qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced
in the OpenSB
Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create symmetric harts. Exact the
hart realize to a separate routine in preparation for supporting
heterogeneous hart arrays.
Signed-off-by: Bin Me
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
include/hw/riscv/sifive_cpu.h | 31 +++
include/hw/riscv/sifive_e.h | 7 +--
include/hw/riscv/sifive_u.h | 7 +--
"linux,phandle" property is optional. Remove all instances in the
sifive_u and virt machine device tree.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_u.c | 3 ---
hw/riscv/virt.c | 3 ---
2 files changed, 6 deletions(-)
diff --git a/hw/ris
This updates the UART base address to match the hardware.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Acked-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive
It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN
for hfxosccfg register programming.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_e_prci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_pr
At present we only allow symmetric harts to be created. In order to
support heterogeneous harts like SiFive FU540, update hart array's
"cpu-type" property to allow cpu type to be set per hart, separated
by delimiter ",". The frist cpu type before the delimiter is assigned
to hart 0, and the second
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_u.c | 16
hw/riscv/virt.c | 24
2 f
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
and pass "cpu-type" to populate heterogeneous harts.
The cpu nodes in the generated DTS have be
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/sifive_e_prci.c | 2 +-
include/hw/riscv/sifive_e_prci.h | 2 ++
2 files changed, 3 insertions(+), 1 delet
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
---
Changes in v2:
- update the file header to indicate at least 2 harts are created
hw/riscv/sifive_u.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/Makefile.objs | 2 +-
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ea45e77..75570
This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/Makefile.
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_u.c | 7 ---
1 file changed, 4 insertions
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to f
At present the GEM support in sifive_u machine is seriously broken.
- The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.
- The generated DT node for GEM has a "clocks-names" which is an
invalid property name.
Not
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/Makefile.objs | 1 +
hw/riscv/sifive_u_prci.c | 163 +
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/sifive_u.c | 23 +++
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 25 i
Now that we have added PRCI nodes, update existing UART and ethernet
nodes to use PRCI as their clock sources, to keep in sync with the
Linux kernel device tree.
With above changes, the previously handcrafted "/soc/ethclk" node is
no longer needed. Remove it.
Signed-off-by: Bin Meng
---
Changes
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
---
Changes in v2:
- keep the PLIC compatible string unchanged as OpenSBI uses that
for DT fix up
hw/riscv/sifive_u.c | 2 --
hw/riscv/virt.
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/sifive_u.c | 21 -
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 21 insertions(+), 1 de
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/sifive_u.c | 5 +
include/hw/riscv/sifive_u.h |
The Linux kernel SiFive UART driver expects an aliases node to be
present in the device tree, from which the driver extracts the port
number from "serial#" in the aliases node.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/sifive_u.c | 2 ++
1 file changed, 2 insertions(+)
diff --g
On 8/6/19 2:35 AM, David Gibson wrote:
> On Wed, Jul 31, 2019 at 11:09:05AM +0200, Damien Hedde wrote:
>>
>>
>> On 7/31/19 7:56 AM, David Gibson wrote:
>>> On Mon, Jul 29, 2019 at 04:56:25PM +0200, Damien Hedde wrote:
This add Resettable interface implementation for both Bus and Device.
>>>
The loading of initramfs is currently not supported on 'sifive_u'.
Add the support to make '-initrd' command line parameter useful.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/sifive_u.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sif
On 07/08/2019 09:14, Balamuruhan S wrote:
> Add mmio callback functions to enable homer/occ common area
> to emulate pstate table, occ-sensors, slw, occ static and
> dynamic values for Power8 and Power9 chips. It also works for
> multiple chips as offset remains the same whereas the base
> address
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt. Other machines (sifive_u, spike)
don't do it neither.
Signed-off-by: Bin Meng
---
Changes in v2: None
hw/riscv/virt.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
On 06.08.19 11:48, Igor Mammedov wrote:
> Max memslot size supported by kvm on s390 is 8Tb,
> move logic of splitting RAM in chunks upto 8T to KVM code.
>
> This way it will hide KVM specific restrictions in KVM code
> and won't affect baord level design decisions. Which would allow
> us to avoid
On 07/08/2019 09:14, Balamuruhan S wrote:
> homer and occ common area region base address are initialized
> to create device tree and realized to map the address with
> mmio callbacks during `pnv_chip_realize()`.
>
> `SysBusNum` enum is introduced to set sysbus for XSCOM, ICP,
> HOMER and OCC appr
On 07/08/2019 09:14, Balamuruhan S wrote:
> During PowerNV boot skiboot populates the device tree by retrieving
> base address of homer/occ common area from PBA BARs and prd ipoll
> mask by accessing xscom read/write accesses.
This looks good. If you could add defines it would be better.
Our comm
Hi all!
There are some fixes and refactorings I need on my way to resend
my backup-top series. It's obvious now that I need to share copying
code between backup and backup-top, as backup copying code becomes
smarter and more complicated. So the goal of the series is to make copying
code more share
backup_cow_with_offload can transfer more than on cluster. Let
backup_cow_with_bounce_buffer behave similarly. It reduces number
of IO and there are no needs to copy cluster by cluster.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/backup.c | 30 +++---
1 file cha
write flags are constant, let's store it in BackupBlockJob instead of
recalculating. It also makes two boolean fields to be unused, so,
drop them.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: John Snow
---
block/backup.c | 24
1 file changed, 12 insertions(+
Limit block_status querying to request bounds on write notifier to
avoid extra seeking.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/backup.c | 38 +-
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/block/backup.c b/block/backup.c
inde
We shouldn't try to copy bytes beyond EOF. Fix it.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/backup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/backup.c b/block/backup.c
index a4d37d2d62..eb41e4af4f 100644
--- a/block/backup.c
+++ b/block/backup.c
@@ -
We have detect_zeroes option, so at least for blockdev-backup user
should define it if zero-detection is needed. For drive-backup leave
detection enabled by default but do it through existing option instead
of open-coding.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Max Reitz
---
b
Use effective bdrv_dirty_bitmap_next_dirty_area interface.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/backup.c | 56 ++
1 file changed, 24 insertions(+), 32 deletions(-)
diff --git a/block/backup.c b/block/backup.c
index f19c9195fe..5ed
backup_cow_with_offload and backup_cow_with_bounce_buffer contains a
lot of duplicated logic. Move it into backup_do_cow.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/backup.c | 83 +++---
1 file changed, 31 insertions(+), 52 deletions(-)
dif
copy_range ignores these limitations, let's improve it. block/backup
code handles max_transfer for copy_range by itself, now it's not needed
more, drop it.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/backup.c | 11 ++-
block/io.c | 41 +--
On 07/08/2019 09:14, Balamuruhan S wrote:
> Hi All,
>
> This is a proposal to extend mmio callbacks in Qemu with scripting interface
> that is prototyped with python in this implementation. It gives ability to
> feed runtime data through callbacks without recompiling Qemu in generic way.
> This pa
Hi Igor,
> -Original Message-
> From: Igor Mammedov [mailto:imamm...@redhat.com]
> Sent: 06 August 2019 14:09
> To: Shameerali Kolothum Thodi
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; sa...@linux.intel.com;
> ard.biesheu...@linaro
Using FLR becomes convenient in cases where resetting the bus is
impractical, for example, when debugging the behavior of individual
functions.
Signed-off-by: Julia Suvorova
---
hw/virtio/virtio-pci.c | 10 ++
hw/virtio/virtio-pci.h | 1 +
2 files changed, 11 insertions(+)
diff --git a
This patchset implements the IE (Invert Endian) bit in SPARCv9 MMU TTE.
It is an attempt of the instructions outlined by Richard Henderson to Mark
Cave-Ayland.
Tested with OpenBSD on sun4u. Solaris 10 is my actual goal, but unfortunately a
separate keyboard issue remains in the way.
On 01/11/17
Rename ALIGNED_ONLY to TARGET_ALIGNED_ONLY for clarity and move
defines out of target/foo/cpu.h into configure, as we do with
TARGET_WORDS_BIGENDIAN, so that it is always defined early.
Poisoned TARGET_ALIGNED_ONLY to prevent use in common code.
Signed-off-by: Tony Nguyen
Reviewed-by: Philippe M
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Introduce no-op size_memop to aid preparatory conversion of
interfaces.
Once interfaces are converted, size_memop will be implemented to
return a MemOp from size in bytes.
Signed-off-by: Tony Ng
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.
Target dependant attributes are conditionalize upon NEED_CPU_H.
Signed-off-by: Tony Nguyen
Acked-by: David Gibson
Reviewed-by: Richard Henderson
---
MAINTAINERS |
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be conver
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be conver
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be conver
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be conver
Convert memory_region_dispatch_{read|write} operand "unsigned size"
into a "MemOp op".
Signed-off-by: Tony Nguyen
---
include/exec/memop.h | 18 +-
include/exec/memory.h | 9 +
memory.c | 7 +--
3 files changed, 23 insertions(+), 11 deletions(-)
diff
Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".
Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoid size_memop calls.
Signed-off-by: Tony
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be conver
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be conver
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".
Convert interfaces by using no-op size_memop.
After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be conver
Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".
Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoid size_memop calls.
Signed-off-by: Tony
DEVICE_HOST_ENDIAN is conditional upon HOST_WORDS_BIGENDIAN.
Code is cleaner if the single use of DEVICE_HOST_ENDIAN is instead
directly conditional upon HOST_WORDS_BIGENDIAN.
Signed-off-by: Tony Nguyen
---
include/exec/cpu-common.h | 8
memory.c | 6 +-
2 files ch
Preparation to replace device_endian with MemOp.
Mapping device_endian onto MemOp limits behaviour changes to this
relatively smaller patch.
The next patch will replace all device_endian usages with the
equivalent MemOp. That patch will be large but have no behaviour
changes.
A subsequent patch
Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.
Call memory_region_dispatch_{read|write} with endianness encoded into
the "MemOp op" operand.
This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endi
Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".
Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoid size_memop calls.
Signed-off-by: Tony
Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Henderson
---
target/sparc/mmu_helper.c | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/
The fast path is taken when TLB_FLAGS_MASK is all zero.
TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,
there are no other side effects.
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Henderson
---
include/exec/cpu-all.h | 10 --
1 file changed, 8 insertions(+),
Notice new attribute, byte swap, and force the transaction through the
memory slow path.
Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.
Suggested-by: Richard Henderson
Signed-off-by: Tony Nguyen
Reviewed-by: Richard Hender
device_endian has been made redundant by MemOp.
Signed-off-by: Tony Nguyen
---
include/exec/cpu-common.h | 8
1 file changed, 8 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 01a29ba..7eeb78c 100644
--- a/include/exec/cpu-common.h
+++ b/include/ex
This bit configures endianness of PCI MMIO devices. It is used by
Solaris and OpenBSD sunhme drivers.
Tested working on OpenBSD.
Unfortunately Solaris 10 had a unrelated keyboard issue blocking
testing... another inch towards Solaris 10 on SPARC64 =)
Signed-off-by: Tony Nguyen
Reviewed-by: Rich
Now that MemOp has been pushed down into the memory API, and
callers are encoding endianness, we can collapse byte swaps
along the I/O path into the accelerator and target independent
adjust_endianness.
Collapsing byte swaps along the I/O path enables additional endian
inversion logic, e.g. SPARC6
Preparation for replacing device_endian with MemOp.
Device realizing code with MemorRegionOps endianness as
DEVICE_NATIVE_ENDIAN is not common code.
Corrected devices were identified by making the declaration of
DEVICE_NATIVE_ENDIAN conditional upon NEED_CPU_H and then listing
what failed to comp
Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.
Signed-off-by: Tony Nguyen
---
accel/tcg/cputlb.c | 170 +--
include/exec/memop.h | 6 ++
memory.c | 11 +---
3 files changed, 90 ins
If interface_count is NO_INTERFACE_INFO, let's not access the arrays
out-of-bounds.
==994==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x625000243930
at pc 0x5642068086a8 bp 0x7f0b6f9ffa50 sp 0x7f0b6f9ffa40
READ of size 1 at 0x625000243930 thread T0
#0 0x5642068086a7 in usbredir_
Ivan Ren wrote:
> From: Ivan Ren
>
> Add qemu_file_update_transfer for just update bytes_xfer for speed
> limitation. This will be used for further migration feature such as
> multifd migration.
>
> Signed-off-by: Ivan Ren
> Reviewed-by: Wei Yang
Reviewed-by: Juan Quintela
Ivan Ren wrote:
> From: Ivan Ren
>
> Limit the speed of multifd migration through common speed limitation
> qemu file.
>
> Signed-off-by: Ivan Ren
Reviewed-by: Juan Quintela
Ivan Ren wrote:
> From: Ivan Ren
>
> Multifd sync will send MULTIFD_FLAG_SYNC flag info to destination, add
> these bytes to ram_counters record.
>
> Signed-off-by: Ivan Ren
> Suggested-by: Wei Yang
Reviewed-by: Juan Quintela
Patchew URL:
https://patchew.org/QEMU/20190807071445.4109-1-bal...@linux.ibm.com/
Hi,
This series failed build test on s390x host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit that
On Wed, Aug 7, 2019 at 3:49 PM Bin Meng wrote:
> Current SiFive PRCI model only works with sifive_e machine, as it
> only emulates registers or PRCI block in the FE310 SoC.
>
> Rename the file name to make it clear that it is for sifive_e.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: Non
On Wed, Aug 7, 2019 at 3:48 PM Bin Meng wrote:
> It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN
> for hfxosccfg register programming.
>
> Signed-off-by: Bin Meng
> Acked-by: Alistair Francis
> ---
>
> Changes in v2: None
>
> hw/riscv/sifive_e_prci.c | 2 +-
> 1 file chang
On Wed, Aug 7, 2019 at 3:49 PM Bin Meng wrote:
> Currently the PRCI register block size is set to 0x8000, but in fact
> 0x1000 is enough, which is also what the manual says.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> hw/riscv/sifive_e_prci.c | 2 +-
> include/hw/riscv
On Wed, Aug 7, 2019 at 3:56 PM Bin Meng wrote:
> The loading of initramfs is currently not supported on 'sifive_u'.
> Add the support to make '-initrd' command line parameter useful.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> hw/riscv/sifive_u.c | 13 -
> 1 file c
On Wed, Aug 7, 2019 at 3:54 PM Bin Meng wrote:
> There is no need to return fdt at the end of create_fdt() because
> it's already saved in s->fdt. Other machines (sifive_u, spike)
> don't do it neither.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> hw/riscv/virt.c | 11 -
On Wed, 7 Aug 2019 08:19:16 +
Shameerali Kolothum Thodi wrote:
> Hi Igor,
>
> > -Original Message-
> > From: Igor Mammedov [mailto:imamm...@redhat.com]
> > Sent: 06 August 2019 14:09
> > To: Shameerali Kolothum Thodi
> > Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> > eric.au...
On Tue, Aug 06, 2019 at 04:43:35AM -0400, Michael S. Tsirkin wrote:
On Mon, Aug 05, 2019 at 08:49:49PM +0200, Jens Freimann wrote:
On Mon, Aug 05, 2019 at 10:22:25AM -0400, Michael S. Tsirkin wrote:
> On Mon, Aug 05, 2019 at 03:12:15PM +0200, Jens Freimann wrote:
> > On Fri, Aug 02, 2019 at 11:2
Peter Maydell writes:
> Factor out code to 'generate a singlestep exception', which is
> currently repeated in four places.
>
> To do this we need to also pull the identical copies of the
> gen-exception() function out of translate-a64.c and translate.c
> into translate.h.
>
> (There is a bug i
Patchew URL:
https://patchew.org/QEMU/20190807071445.4109-1-bal...@linux.ibm.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
mak
On Wed, Aug 7, 2019 at 3:48 PM Bin Meng wrote:
> This updates the UART base address to match the hardware.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Jonathan Behrens
> Acked-by: Alistair Francis
> ---
>
> Changes in v2: None
>
> hw/riscv/sifive_u.c | 4 ++--
> 1 file changed, 2 insertions(+)
On Tue, Aug 06, 2019 at 05:14:33PM +0200, Markus Armbruster wrote:
> diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
> index e5b62dd2fc..de70b7a19a 100644
> --- a/include/hw/qdev-core.h
> +++ b/include/hw/qdev-core.h
> @@ -5,7 +5,6 @@
> #include "qemu/bitmap.h"
> #include "qom/object
On Tue, Aug 06, 2019 at 05:14:12PM +0200, Markus Armbruster wrote:
> hw/tpm/trace-events uses TARGET_FMT_plx formats with uint64_t
> arguments. That's wrong, TARGET_FMT_plx takes hwaddr. Since hwaddr
> happens to be uint64_t, it works anyway. Messed up in commit
> ec427498da5, v2.12.0. Clean up
On Tue, Aug 06, 2019 at 05:14:13PM +0200, Markus Armbruster wrote:
> docs/devel/tracing.txt explains "since many source files include
> trace.h, [the generated trace.h use] a minimum of types and other
> header files included to keep the namespace clean and compile times
> and dependencies down."
>
On Tue, 6 Aug 2019 at 23:12, Eddie James wrote:
>
>
> On 8/5/19 9:31 AM, Peter Maydell wrote:
> > On Wed, 26 Jun 2019 at 19:43, Eddie James wrote:
> >> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> >> index 7b80b1d..51a733b 100644
> >> --- a/hw/sd/sdhci.c
> >> +++ b/hw/sd/sdhci.c
> >> @@ -213,7 +
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