It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
---
Changes in v2:
- update the file header to indicate at least 2 harts are created
hw/riscv/sifive_u.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 821f1d5..91f3c76 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,8 +10,8 @@
* 1) CLINT (Core Level Interruptor)
* 2) PLIC (Platform Level Interrupt Controller)
*
- * This board currently generates devicetree dynamically that indicates at most
- * five harts.
+ * This board currently generates devicetree dynamically that indicates at
least
+ * two harts and up to five harts.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -429,6 +429,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
* management CPU.
*/
mc->max_cpus = 5;
+ /* It is not useful if we only have one management CPU */
+ mc->min_cpus = 2;
}
DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
--
2.7.4
