From: Georg Hofstetter
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/tricore/translate.c b/targ
From: David Brenken
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
Reviewed-by: Bastian Koppelmann
---
target/tricore/fpu_helper.c | 16
target/tricore/helper.h |
From: David Brenken
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
Reviewed-by: Bastian Koppelmann
---
target/tricore/fpu_helper.c | 25 +
target/tricore/helper.
From: David Brenken
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/t
From: Andreas Konopik
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/fpu_helper.c | 85 +
target/tricore/helper.h | 1 +
targe
Le 19/06/2019 à 00:32, Jim Wilson a écrit :
> 32-bit RISC-V uses _llseek instead of lseek as syscall number 62.
> Update syscall list from open-embedded build, primarily because
> 32-bit RISC-V requires statx support.
>
> Tested with cross gcc testsuite runs for rv32 and rv64, with the
> pending s
Hi Eric,
> -Original Message-
> From: Auger Eric [mailto:eric.au...@redhat.com]
> Sent: 18 June 2019 13:41
> To: Shameerali Kolothum Thodi ;
> qemu-devel@nongnu.org; qemu-...@nongnu.org; imamm...@redhat.com
> Cc: peter.mayd...@linaro.org; shannon.zha...@gmail.com;
> sa...@linux.intel.com;
Hi Eric,
> -Original Message-
> From: Auger Eric [mailto:eric.au...@redhat.com]
> Sent: 18 June 2019 13:42
> To: Shameerali Kolothum Thodi ;
> qemu-devel@nongnu.org; qemu-...@nongnu.org; imamm...@redhat.com
> Cc: peter.mayd...@linaro.org; shannon.zha...@gmail.com;
> sa...@linux.intel.com;
Hi Eric,
> -Original Message-
> From: Auger Eric [mailto:eric.au...@redhat.com]
> Sent: 18 June 2019 14:45
> To: Peter Maydell
> Cc: Shameerali Kolothum Thodi ;
> QEMU Developers ; qemu-arm
> ; Igor Mammedov ;
> Shannon Zhao ; Samuel Ortiz
> ; sebastien.bo...@intel.com; xuwei (O)
> ; Lasz
From: David Brenken
Hello everyone,
as discussed here is the second version of the patchset.
- We changed the implementation of the RRPW_INSERT to make use of
tcg_gen_deposit_tl.
- We added more information of the implementation of QSEED in the code
and changed parts of the implementation.
- We
On Thu, 13 Jun 2019 11:25:42 +0200
Cornelia Huck wrote:
> A vfio-ccw device may provide an async command subregion for
> issuing halt/clear subchannel requests. If it is present, use
> it for sending halt/clear request to the device; if not, fall
> back to emulation (as done today).
>
> Reviewed
Patchew URL:
https://patchew.org/QEMU/20190619075643.10048-1-david.bren...@efs-auto.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2 0/5] tricore: adding new instructions and
fixing issues
Type: series
Messa
Patchew URL:
https://patchew.org/QEMU/20190619075643.10048-1-david.bren...@efs-auto.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2 0/5] tricore: adding new instructions and
fixing issues
Type: series
Messa
Hi all,
should I rebase and resend or these ones are still good?
Regards,
Michael
On Fri, Jun 14, 2019 at 5:21 PM wrote:
> Patchew URL:
> https://patchew.org/QEMU/20190614131724.33928-1-mrol...@gmail.com/
>
>
>
> Hi,
>
> This series seems to have some coding style problems. See output below fo
even if an entry overlaps with notifier's range, should not map/unmap
out of bound part in the entry.
This would cause problem in below case:
1. initially there are two notifiers with ranges
0-0xfedf, 0xfef0-0x,
IOVAs from 0x3c00 - 0x3c1f is in shadow page table.
2
On Wed, 19 Jun 2019 14:20:50 +0800
Wei Yang wrote:
> On Tue, Jun 18, 2019 at 05:59:56PM +0200, Igor Mammedov wrote:
> >
> >On Mon, 13 May 2019 14:19:04 +0800
> >Wei Yang wrote:
> >
> >> Now MADT is highly depend in architecture and machine type and leaves
> >> duplicated code in different arch
On 6/19/19 9:56 AM, David Brenken wrote:
From: David Brenken
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+)
13.06.2019 1:09, Max Reitz wrote:
> This changes iotest 204's output, because blkdebug on top of a COW node
> used to make qemu-img map disregard the rest of the backing chain (the
> backing chain was broken by the filter). With this patch, the
> allocation in the base image is reported correctly.
13.06.2019 1:09, Max Reitz wrote:
> We want to make it explicit where bs->backing is used, and we have done
> so. The old role of backing_bs() is now effectively taken by
> bdrv_filtered_cow_bs().
>
> Signed-off-by: Max Reitz
Reviewed-by: Vladimir Sementsov-Ogievskiy
> ---
> include/block
13.06.2019 1:09, Max Reitz wrote:
> This is useful in other files like blockdev.c to determine for example
> whether a node can be written to or not.
>
> Signed-off-by: Max Reitz
Reviewed-by: Vladimir Sementsov-Ogievskiy
> ---
> include/block/block_int.h | 3 +++
> block.c
Am 19.06.2019 um 08:42 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Am 18.06.2019 um 11:01 hat Daniel P. Berrangé geschrieben:
> >> On Mon, Jun 17, 2019 at 08:49:03PM +0200, Markus Armbruster wrote:
> >> > From: Kevin Wolf
> >> >
> >> > The -mon pretty=on|off switch of the -mon
On Wed, Jun 19, 2019 at 11:18:52AM +0200, Kevin Wolf wrote:
> Am 19.06.2019 um 08:42 hat Markus Armbruster geschrieben:
> > Kevin Wolf writes:
> >
> > > Am 18.06.2019 um 11:01 hat Daniel P. Berrangé geschrieben:
> > >> On Mon, Jun 17, 2019 at 08:49:03PM +0200, Markus Armbruster wrote:
> > >> > Fr
Read bios geometry for boot devices from fw_cfg.
By receiving LCHS values directly from QEMU through fw_cfg we will be
able to support logical geometries which can not be inferred by SeaBIOS
itself.
(For instance: A 8GB virtio-blk hard drive which was originally created
as an IDE and must report L
Adding the following utility functions:
* boot_lchs_find_pci_device
* boot_lchs_find_scsi_device
* boot_lchs_find_ata_device
These will be used to apply LCHS values received through fw_cfg.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Signed-off-by: Sam Eiderman
---
src/Kco
v1:
Non-standard logical geometries break under QEMU.
A virtual disk which contains an operating system which depends on
logical geometries (consistent values being reported from BIOS INT13
AH=08) will most likely break under QEMU/SeaBIOS if it has non-standard
logical geometries - for example 56
Currently glob_prefix() and build_pci_path() are under the "Boot
priority ordering" section.
Move them to a new "Helper search functions" section since we will reuse
them in the next commit.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Signed-off-by: Sam Eiderman
---
src/boot.c | 94
Boot devices which use overriden LCHS values are:
* ata
* ahci
* scsi
* esp
* lsi
* megasas
* mpt
* pvscsi
* virtio
* virtio-blk
We use these values in get_translation() and setup_translation() by
introducing a new translation type:
Move device name construction to a separate function.
We will reuse this function in the following commit to pass logical CHS
parameters through fw_cfg much like we currently pass bootindex.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Signed-off-by: Sam Eiderman
---
bootdevice.c | 61 +
Add logical geometry variables to BlockConf.
A user can now supply "lcyls", "lheads" & "lsecs" for any HD device
that supports CHS ("cyls", "heads", "secs").
These devices include:
* ide-hd
* scsi-hd
* virtio-blk-pci
In future commits we will use the provided LCHS and pass it to the
Fixing tabbing in block related macros.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Signed-off-by: Sam Eiderman
---
hw/ide/qdev.c| 2 +-
include/hw/block/block.h | 16
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/ide/qdev.c b/hw/ide/qde
Add an interface to provide direct logical CHS values for boot devices.
We will use this interface in the next commits.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Signed-off-by: Sam Eiderman
---
bootdevice.c| 55 +
include/sys
Add QTest tests to check the logical geometry override option.
The tests in hd-geo-test are out of date - they only test IDE and do not
test interesting MBRs.
I added a few helper functions which will make adding more tests easier.
QTest's fw_cfg helper functions support only legacy fw_cfg, so I
Gentle ping
> On 5 Jun 2019, at 15:17, Sam Eiderman wrote:
>
> v1:
>
> VMware introduced a new snapshot format in VMFS6 - seSparse (Space
> Efficient Sparse) which is the default format available in ESXi 6.7.
> Add read-only support for the new snapshot format.
>
> v2:
>
> Fixed after Max's r
Relevant devices are:
* ide-hd (and ide-cd, ide-drive)
* scsi-hd (and scsi-cd, scsi-disk, scsi-block)
* virtio-blk-pci
We do not call del_boot_device_lchs() for ide-* since we don't need to -
IDE block devices do not support unplugging.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Mo
13.06.2019 1:09, Max Reitz wrote:
> We have to perform an active commit whenever the top node has a parent
> that has taken the WRITE permission on it.
>
> Signed-off-by: Max Reitz
> ---
> blockdev.c | 24 +---
> 1 file changed, 21 insertions(+), 3 deletions(-)
>
> diff --
We will need to add LCHS removal logic to scsi-hd's unrealize() in the
next commit.
Reviewed-by: Karl Heubaum
Reviewed-by: Arbel Moshe
Signed-off-by: Sam Eiderman
---
hw/scsi/scsi-bus.c | 15 +++
include/hw/scsi/scsi.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/hw/
On Mon, Jun 17, 2019 at 10:00:10PM -0700, Richard Henderson wrote:
> Ping. Otherwise I'll include it in my next tcg pull.
Uh.. I'm not sure who this ping is directed at. I'm afraid this
series has dropped off my radar.
>
>
> r~
>
> On 5/18/19 9:15 PM, Richard Henderson wrote:
> > Based-on: <
Using fw_cfg, supply logical CHS values directly from QEMU to the BIOS.
Non-standard logical geometries break under QEMU.
A virtual disk which contains an operating system which depends on
logical geometries (consistent values being reported from BIOS INT13
AH=08) will most likely break under QEM
Patchew URL:
https://patchew.org/QEMU/20190619092905.24029-1-shmuel.eider...@oracle.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [SeaBIOS] [QEMU] [PATCH v4 0/8] Add Qemu to SeaBIOS LCHS interface
Type: series
Message-id: 201906
13.06.2019 1:09, Max Reitz wrote:
> With bdrv_filtered_rw_bs(), we can easily handle this default filter
> behavior in bdrv_co_block_status().
>
> blkdebug wants to have an additional assertion, so it keeps its own
> implementation, except bdrv_co_block_status_from_file() needs to be
> inlined the
v1:
Non-standard logical geometries break under QEMU.
A virtual disk which contains an operating system which depends on
logical geometries (consistent values being reported from BIOS INT13
AH=08) will most likely break under QEMU/SeaBIOS if it has non-standard
logical geometries - for example 56
From: David Hildenbrand
Let's allow to specify additional interfaces for the base type (e.g.
later TYPE_MEMORY_DEVICE), something that was possible before the
rework of virtio PCI device instantiation.
Reviewed-by: Cornelia Huck
Signed-off-by: David Hildenbrand
---
hw/virtio/virtio-pci.c | 1
This is the implementation of virtio-pmem device. Support will require
machine changes for the architectures that will support it, so it will
not yet be compiled. It can be unlocked with VIRTIO_PMEM_SUPPORTED per
machine and disabled globally via VIRTIO_PMEM.
We cannot use the "addr" property as t
From: David Hildenbrand
Print the memory device info just like for PCDIMM/NVDIMM.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: David Hildenbrand
---
hmp.c | 27 +++
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/hmp.c b/hmp.c
index 92941142af..e1
On Fri, Jun 14, 2019 at 06:11:37PM +0100, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> Signed-off-by: Emilio G. Cota
Acked-by: David Gibson
> ---
> target/ppc/translate.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/
We need a proxy device for virtio-pmem, and this device has to be the
actual memory device so we can cleanly hotplug it.
Forward memory device class functions either to the actual device or use
properties of the virtio-pmem device to implement these in the proxy.
virtio-pmem will only be compiled
From: David Hildenbrand
Override the device hotplug handler to properly handle the memory device
part via virtio-pmem-pci callbacks from the machine hotplug handler and
forward to the actual PCI bus hotplug handler.
As PCI hotplug has not been properly factored out into hotplug handlers,
most ma
On Sun, Jun 16, 2019 at 07:22:23PM +0200, Greg Kurz wrote:
> Make kvmppc_xive_disconnect() able to undo the changes of a partial
> execution of kvmppc_xive_connect() and use it to perform rollback.
>
> Based-on: <20190614165920.12670-2-...@kaod.org>
> Signed-off-by: Greg Kurz
I'm afraid this doe
From: David Hildenbrand
Account the memory to node 0 for now. Once (if ever) virtio-pmem
supports NUMA, we can account it to the right node.
Signed-off-by: David Hildenbrand
---
numa.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/numa.c b/numa.
Hello,
On 19/06/2019 11:36, David Gibson wrote:
> On Sun, Jun 16, 2019 at 07:22:23PM +0200, Greg Kurz wrote:
>> Make kvmppc_xive_disconnect() able to undo the changes of a partial
>> execution of kvmppc_xive_connect() and use it to perform rollback.
>>
>> Based-on: <20190614165920.12670-2-...@kaod
This patch series has implementation for "virtio pmem"
device. "virtio pmem" is persistent memory(nvdimm) device in
guest which allows to bypass the guest page cache. This
also implements a VIRTIO based asynchronous flush mechanism.
Details of project idea for 'virtio pmem' flushing interfa
Sync linux headers for virtio pmem.
Signed-off-by: Pankaj Gupta
---
include/standard-headers/linux/virtio_ids.h | 1 +
include/standard-headers/linux/virtio_pmem.h | 35
2 files changed, 36 insertions(+)
create mode 100644 include/standard-headers/linux/virtio_pme
Patchew URL:
https://patchew.org/QEMU/20190619092905.24029-1-shmuel.eider...@oracle.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [SeaBIOS] [QEMU] [PATCH v4 0/8] Add Qemu to SeaBIOS LCHS interface
Type: series
Message-id: 201906
10.06.2019 16:21, Denis Plotnikov wrote:
> The patch allows to provide a pattern file for write
> command. There was no similar ability before.
>
> Signed-off-by: Denis Plotnikov
> ---
> v6:
>* the pattern file is read once to reduce io
>
> v5:
>* file name initiated with null to make co
On Mon, Jun 17, 2019 at 03:26:50PM +0300, Maxim Levitsky wrote:
> On Mon, 2019-06-10 at 19:18 +0530, Aarushi Mehta wrote:
> > +if (!cqes) {
> > +break;
> > +}
> > +LuringAIOCB *luringcb = io_uring_cqe_get_data(cqes);
> > +ret = cqes->res;
> > +
> > +
Le 19/06/2019 à 01:53, Jim Wilson a écrit :
> All of the flags need to be conditional as old systems don't have statx
> support. Otherwise it works the same as other stat family syscalls.
> This requires the pending patch to add statx support.
>
> Tested on Ubuntu 16.04 (no host statx) and Ubuntu
On Mon, Jun 17, 2019 at 04:01:45PM +0300, Maxim Levitsky wrote:
> On Mon, 2019-06-10 at 19:19 +0530, Aarushi Mehta wrote:
> > Signed-off-by: Aarushi Mehta
> > Reviewed-by: Stefan Hajnoczi
> > ---
> > blockdev.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/bl
On Mon, Jun 17, 2019 at 03:33:01PM +0300, Maxim Levitsky wrote:
> On Mon, 2019-06-10 at 19:18 +0530, Aarushi Mehta wrote:
> > diff --git a/stubs/io_uring.c b/stubs/io_uring.c
> > new file mode 100644
> > index 00..622d1e4648
> > --- /dev/null
> > +++ b/stubs/io_uring.c
> > @@ -0,0 +1,32 @@
On Wed, 2019-06-19 at 11:24 +0100, Stefan Hajnoczi wrote:
> On Mon, Jun 17, 2019 at 04:01:45PM +0300, Maxim Levitsky wrote:
> > On Mon, 2019-06-10 at 19:19 +0530, Aarushi Mehta wrote:
> > > Signed-off-by: Aarushi Mehta
> > > Reviewed-by: Stefan Hajnoczi
> > > ---
> > > blockdev.c | 4 +++-
> > >
On Mon, 17 Jun 2019 15:38:45 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/14/19 10:11 AM, Alex Bennée wrote:
+++ b/target/riscv/translate.c
@@ -793,7 +793,7 @@ static void riscv_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
DisasContext *ctx = container_of(dcbase, Dis
On Wed, 2019-06-19 at 11:14 +0100, Stefan Hajnoczi wrote:
> On Mon, Jun 17, 2019 at 03:26:50PM +0300, Maxim Levitsky wrote:
> > On Mon, 2019-06-10 at 19:18 +0530, Aarushi Mehta wrote:
> > > +if (!cqes) {
> > > +break;
> > > +}
> > > +LuringAIOCB *luringcb = io_ur
On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
Based-on:
Now that the RISC-V spec has started to be ratified let's update our
QEMU implementation. There are a few things going on here:
- Add priv version 1.11.0 to QEMU
- This is the ratified version of the Privledge spec
Adding simple macro that is calling tcg implementation of appropriate
instruction if altivec support is active.
Optimization of altivec instruction lvsl (Load Vector for Shift Left).
Place bytes sh:sh+15 of value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F
in destination register. Sh is calculated
Optimize Altivec instruction vclzd (Vector Count Leading Zeros Doubleword).
This instruction counts the number of leading zeros of each doubleword element
in source register and places result in the appropriate doubleword element of
destination register.
Using tcg-s count leading zeros instruction
Since I found this two instructions implemented with tcg, I refactored
them so they are consistent with other similar implementations that
I introduced in this patch.
Also, a new dual macro GEN_VXFORM_TRANS_DUAL is added. This macro is
used if one instruction is realized with direct translation, a
Optimize altivec instruction vpkpx (Vector Pack Pixel).
Rearranges 8 pixels coded in 6-5-5 pattern (4 from each source register)
into contigous array of bits in the destination register.
In each iteration of outer loop, the instruction is to be done with
the 6-5-5 pack for 2 pixels of each doublew
Optimize altivec instruction vgbbd (Vector Gather Bits by Bytes by Doubleword)
All ith bits (i in range 1 to 8) of each byte of doubleword element in
source register are concatenated and placed into ith byte of appropriate
doubleword element in destination register.
Following solution is done for
Optimization of altivec instructions vsl and vsr(Vector Shift Left/Rigt).
Perform shift operation (left and right respectively) on 128 bit value of
register vA by value specified in bits 125-127 of register vB. Lowest 3
bits in each byte element of register vB must be identical or result is
undefin
Optimize Altivec instruction vclzh (Vector Count Leading Zeros Halfword).
This instruction counts the number of leading zeros of each halfword element
in source register and places result in the appropriate halfword element of
destination register.
In each iteration of outer for loop count operati
Optimize emulation of ten Altivec instructions: lvsl, lvsr, vsl, vsr, vpkpx,
vgbbd, vclzb, vclzh, vclzw and vclzd.
This series buils up on and complements recent work of Thomas Murta, Mark
Cave-Ayland and Richard Henderson in the same area. It is based on devising TCG
translation implementation fo
Optimize Altivec instruction vclzw (Vector Count Leading Zeros Word).
This instruction counts the number of leading zeros of each word element
in source register and places result in the appropriate word element of
destination register.
Counting is to be performed in four iterations of for loop(on
Patchew URL:
https://patchew.org/QEMU/20190619092905.24029-1-shmuel.eider...@oracle.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [SeaBIOS] [QEMU] [PATCH v4 0/8] Add Qemu to SeaBIOS LCHS interface
Type: series
Message-id: 201906
Pranith Kumar writes:
> On Fri, Jun 14, 2019 at 10:24 AM Alex Bennée wrote:
>>
>> From: "Emilio G. Cota"
>>
>> Add the API first to ease review.
>>
>> Signed-off-by: Emilio G. Cota
>> Signed-off-by: Alex Bennée
>>
>> ---
>> v3
>> - merge in changes to plugin install/reset/uninstall
>> -
Pranith Kumar writes:
> On Fri, Jun 14, 2019 at 10:30 AM Alex Bennée wrote:
>>
>> From: "Emilio G. Cota"
>>
>> Signed-off-by: Emilio G. Cota
>> [AJB: moved directory and merged various fixes]
>> Signed-off-by: Alex Bennée
>>
>> ---
>> v3
>> - moved to plugins/
>> - merged
>> plugin:
On Fri, Jun 14, 2019 at 01:08:44PM +0200, Greg Kurz wrote:
> There are several places where CONFIG_KVM is used to guard code that
> should only be built when KVM is supported. It is generally preferable
> to avoid that and leave such guards in header files for improved
> readability.
>
> In many c
Hi Laurent,
> s/arhitecture/architecture/
Done.
> You should define sys_statx() using _syscall5() macro and use it.
Done.
> ret != -TARGET_ENOSYS
Done.
> You already checked above p is not NULL and exited with -TARGET_EFAULT.
Done.
> BTW, do we really need to emulate the syscall if it is n
On 6/19/19 9:56 AM, David Brenken wrote:
+
+result = 0;
+result = deposit32(result, 31, 1, new_S);
+result = deposit32(result, 23, 8, new_E);
+result = deposit32(result, 15, 8, new_M);
+}
+
+if (float32_is_any_nan(arg1) || result == float32_sqrt_nan) {
On 6/19/19 9:56 AM, David Brenken wrote:
From: Georg Hofstetter
Signed-off-by: Andreas Konopik
Signed-off-by: David Brenken
Signed-off-by: Georg Hofstetter
Signed-off-by: Robert Rasche
Signed-off-by: Lars Biermanski
---
target/tricore/translate.c | 1 +
1 file changed, 1 insertion(+)
Hello,
we're investigating the possibility to set some spice properties at
runtime, through the QMP interface, but we're not sure what's the best
way to proceed.
I've prepared the patch below, that adds a new QMP
command, but is there another way like with a QOM object, that could
reuse an existin
Patchew URL:
https://patchew.org/QEMU/1560942225-24728-1-git-send-email-stefan.branko...@rt-rk.com/
Hi,
This series failed build test on s390x host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointin
Patchew URL: https://patchew.org/QEMU/20190619123042.4822-1-kpou...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [RFC] spice-core: allow setting properties from QMP
Type: series
Message-id: 20190619123042.482
Ah. You are right.
I will fix this one within the third version.
Best regards
David
-Ursprüngliche Nachricht-
Von: Bastian Koppelmann [mailto:kbast...@mail.uni-paderborn.de]
Gesendet: Mittwoch, 19. Juni 2019 14:26
An: David Brenken ; qemu-devel@nongnu.org
Cc: Biermanski, Lars (EFS-GH3)
Le 19/06/2019 à 14:12, Aleksandar Rikalo a écrit :
> Hi Laurent,
...
>> BTW, do we really need to emulate the syscall if it is not available?
>>
>> I think the user-space application calling statx() should be ready to
>> receive ENOSYS and define some kinds of fallback (like you do below). So
>> it
Hi Yan,
[+ Peter]
On 6/19/19 10:49 AM, Yan Zhao wrote:
> even if an entry overlaps with notifier's range, should not map/unmap
> out of bound part in the entry.
I don't think the patch was based on the master as the trace at the very
end if not part of the upstream code.
>
> This would cause pr
On Tue, Jun 18, 2019 at 10:29:31AM -0400, Igor Mammedov wrote:
> python3 doesn't have raw_input(), so qmp-shell breaks.
> Use input() instead and override it with raw_input()
> if running on python2.
>
> Signed-off-by: Igor Mammedov
> ---
> scripts/qmp/qmp-shell | 6 +-
> 1 file changed, 5 i
Hi Alistair,
On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis wrote:
>
> On Fri, Jun 14, 2019 at 8:30 AM Bin Meng wrote:
> >
> > This adds a reset opcode for sifive_test device to trigger a system
> > reset for testing purpose.
> >
> > Signed-off-by: Bin Meng
> > ---
> >
> > hw/riscv/sifive_te
From: Aleksandar Markovic
This is a collection of misc patches for Linux user that I recently
accumulated from variuous sources. All of them originate from problems
observed on mips target. However, most of these changes actually
affect and fix linux-user problems on multiple targets.
v10->v11:
From: Yunqiang Su
Add support for options SOL_ALG of the syscall setsockopt(). This
option is used in relation to Linux kernel Crypto API, and allows
a user to set additional information for the cipher operation via
syscall setsockopt(). The field "optname" must be one of the
following:
- ALG_
From: Aleksandar Rikalo
Implement support for translation of system call statx().
The implementation is based on "best effort" approach: if host is
capable of executing statx(), host statx() is used. If not, the
implementation includes invoking other (more mature) system calls
(from the same 'st
From: Neng Chen
Add support for the option IPV6__MEMBERSHIP of the syscall
setsockopt(). This option controls membership in multicast groups.
Argument is a pointer to a struct ipv6_mreq.
The glibc header defines the ipv6_mreq structure,
which includes the following members:
struct in6_addr
From: Aleksandar Markovic
Only MIPS O32 and N32 have special (different than other
architectures) definition of structure flock in kernel.
Bring flock definition for MIPS O64 ABI to the correct state.
Reported-by: Dragan Mladjenovic
Signed-off-by: Aleksandar Markovic
---
linux-user/generic/f
From: Jim Wilson
All of the flags need to be conditional as old systems don't have statx
support. Otherwise it works the same as other stat family syscalls.
This requires the pending patch to add statx support.
Tested on Ubuntu 16.04 (no host statx) and Ubuntu 19.04 (with host statx)
using a ri
From: Neng Chen
Add support for the option IPV6__MEMBERSHIP of the syscall
setsockopt(). This option controls membership in multicast groups.
Argument is a pointer to a struct ipv6_mreq.
The glibc header defines the ipv6_mreq structure,
which includes the following members:
struct in6_addr
From: Aleksandar Rikalo
Implement support for translation of system call statx().
The implementation is based on "best effort" approach: if host is
capable of executing statx(), host statx() is used. If not, the
implementation includes invoking other (more mature) system calls
(from the same 'st
From: Aleksandar Markovic
Only MIPS O32 and N32 have special (different than other
architectures) definition of structure flock in kernel.
Bring flock definition for MIPS O64 ABI to the correct state.
Reported-by: Dragan Mladjenovic
Signed-off-by: Aleksandar Markovic
---
linux-user/generic/f
From: Aleksandar Markovic
This is a collection of misc patches for Linux user that I recently
accumulated from variuous sources. All of them originate from problems
observed on mips target. However, most of these changes actually
affect and fix linux-user problems on multiple targets.
There are
From: Jim Wilson
All of the flags need to be conditional as old systems don't have statx
support. Otherwise it works the same as other stat family syscalls.
This requires the pending patch to add statx support.
Tested on Ubuntu 16.04 (no host statx) and Ubuntu 19.04 (with host statx)
using a ri
On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt wrote:
>
> On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
> > Based-on:
> >
> > Now that the RISC-V spec has started to be ratified let's update our
> > QEMU implementation. There are a few things going on here:
> > - Add priv ver
From: Yunqiang Su
Add support for options SOL_ALG of the syscall setsockopt(). This
option is used in relation to Linux kernel Crypto API, and allows
a user to set additional information for the cipher operation via
syscall setsockopt(). The field "optname" must be one of the
following:
- ALG_
Patchew URL:
https://patchew.org/QEMU/1560953429-29203-1-git-send-email-aleksandar.marko...@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v11 0/5] linux-user: A set of miscellaneous patches
Type: series
1 - 100 of 281 matches
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