On 12/06/2019 02:04, David Gibson wrote:
> On Sun, Jun 02, 2019 at 12:08:50PM +0100, Mark Cave-Ayland wrote:
>> Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
>> registers are in host endian order" functions getVSR() and putVSR() which
>> used
>> to convert the VSR regi
On 12/06/2019 20:47, Richard Henderson wrote:
> On 6/2/19 4:08 AM, Mark Cave-Ayland wrote:
>> -getVSR(xt_num, &xt, env); \
>> + \
>> nb = (nb >= 16) ? 16 : nb;
On 12/06/2019 20:45, Richard Henderson wrote:
> On 6/2/19 4:08 AM, Mark Cave-Ayland wrote:
>> void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
>> {
>> -ppc_vsr_t xt, xb;
>> +ppc_vsr_t *xt = &env->vsr[xT(opcode)];
>> +ppc_vsr_t *xb = &env->vsr[xB(opcode)];
>> +ppc_vsr_t t =
On Fri, 14 Jun 2019 05:25:50 PDT (-0700), phi...@redhat.com wrote:
On 6/14/19 2:08 PM, Palmer Dabbelt wrote:
Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(),
where a pair of recently added MemoryRegion instances would not be freed
if there were errors elsewhere in the function
> On 15 Jun 2019, at 3:42, Paolo Bonzini wrote:
>
> This patch improves the KVM_GET/SET_NESTED_STATE structs by detailing
> the format of VMX nested state in a struct. The VMX nested state is
> accessible through struct kvm_vmx_nested_state though, to avoid
> changing the size of the structs,
On Mon, 3 Jun 2019 at 18:54, Philippe Mathieu-Daudé wrote:
>
> Hi Hongbo, Ard.
>
> On 4/18/19 6:04 AM, Hongbo Zhang wrote:
> > Following the previous patch, this patch adds peripheral devices to the
> > newly introduced SBSA-ref machine.
> >
> > Signed-off-by: Hongbo Zhang
> > ---
> > hw/arm/sbs
Hi Stefan and thank you for your review.
I am sorry for my late response, I have updated the specification
according to your review (and Eduardo's review) and sent it to the
virtio-comment mailing list.
On 5/15/19 12:43 PM, Stefan Hajnoczi wrote:
On Sun, Apr 28, 2019 at 04:26:31PM +0300, Yon
With the conversion of PPC VSX registers to host endian during the 4.0
development
cycle, the VSX helpers getVSR() and putVSR() which were used to convert between
big
endian and host endian (and are currently just a no-op) can now be removed. This
eliminates an extra copy for each VSX source regi
Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.
Signed-off-by: Mark Cave-Ayland
---
target/ppc/mem_helper.c | 23 ++
Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.
Now that there are now no more users of getVSR()/putVSR() these funct
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X3 macro which performs the decode based
upon xT, xA and xB at translation time.
With the previous changes to the VSX_CMP generator and helper macros the
opcode parameter is no longer required in
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X1 macro which performs the decode based
upon xB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
---
target/ppc/fpu_helper.c | 6 ++
target
Rather than perform the VSR register decoding within the helper itself,
introduce a new generator and helper function which perform the decode based
upon xT and xB at translation time.
The xscvqpdp helper is the only 2 parameter xT/xB implementation that requires
the opcode to be passed as an addi
Rather than perform the VSR register decoding within the helper itself,
introduce a new VSX_CMP macro which performs the decode based upon xT, xA
and xB at translation time.
Subsequent commits will make the same changes for other instructions however
the xvcmp* instructions are different in that t
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X2_AB macro which performs the decode based
upon xA and xB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
---
target/ppc/fpu_helper.c | 15
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X2 macro which performs the decode based
upon xT and xB at translation time.
With the previous change to the xscvqpdp generator and helper functions the
opcode parameter is no longer required in
> On 15 Jun 2019, at 3:57, Liran Alon wrote:
>
>> On 15 Jun 2019, at 3:42, Paolo Bonzini wrote:
>>
>> From: Liran Alon
>>
>> +static bool is_vmx_enabled(CPUX86State *env)
>> +{
>> +return (IS_INTEL_CPU(env) && (env->cr[4] & CR4_VMXE_MASK));
>> +}
>> +
>> +static bool is_svm_enabled(CPU
Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.
Signed-off-by: Mark Cave-Ayland
---
target/ppc/fpu_helper.c | 762 +
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R2 macro which performs the decode based
upon rD and rB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
---
target/ppc/fpu_helper.c | 30 +++
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R2_AB macro which performs the decode based
upon rA and rB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
---
target/ppc/fpu_helper.c | 10
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
---
target/ppc/helper.h | 8 +++
target/ppc/mem_helper.c | 6 ++---
target/ppc/translate/vsx-impl.inc.c | 47 +++--
3 files changed, 30 insertions(+), 31 deletions(-)
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
---
target/ppc/helper.h | 4 ++--
target/ppc/int_helper.c | 12
target/ppc/translate/vsx-impl.inc.c | 10 +-
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/pp
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R3 macro which performs the decode based
upon rD, rA and rB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
---
target/ppc/fpu_helper.c | 36 +++
Introduce a new GEN_VSX_HELPER_VSX_MADD macro for the generator function which
enables the source and destination registers to be decoded at translation time.
This enables the determination of a or m form to be made at translation time so
that a single helper function can now be used for both vari
Patchew URL:
https://patchew.org/QEMU/20190616123751.781-1-mark.cave-ayl...@ilande.co.uk/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v3 00/15] target/ppc: remove getVSR()/putVSR() and
further tidy-up
Type: ser
Hello,
I am interested in understanding on how QEMU maps the user and kernel
pages of a guest OS to the host OS memory (working on 3.1.0 but any
version is acceptable with target x86-64 arch).
Since QEMU runs on user space, these pages will be also mapped on the
user space of the host machine. S
Improvement in comments for the instantiation functions.
This is to highlight what each cpu class, in the 68000 series, contains
in terms of instructions/features.
Signed-off-by: Lucien Murray-Pitts
---
target/m68k/cpu.c | 47 +++
target/m68k/cpu.h | 4
The 68000 does not support the MOVEC instruction, it was added with the 68010.
A new 68010 CPU class was created, and the MOVEC instruction moved to that
class.
Futher on the 68010, 68060 and CPU32 the ISP doesnt exist.
These CPUs only have SSP/USP.
(NOTE: ColdFire has a different MOVEC helper, t
The m680XX_cpu_initfn functions have been rearranged to cascade starting from
the base 68000, so that the 68010 then inherits from this, and so on until the
68060.
This makes it simpler to track features since in most cases the m68k were
product enhancements on each other, with only a few instruct
Added "CPU class" m68k_feature to each CPU init func so MOVEC can detect wrong
CR (Control Register) access.
Added CPU class detection for each CR type in the m68k_move_to/from helpers,
so that it throws and exception if an unsupported register is requested
for that CPU class.
Reclassified MOVEC
Added more detailed comments to each case of m68k_move_to/from helpers to list
the supported CPUs for that CR as they were wrong in some cases, and
missing some cpu classes in other cases.
Signed-off-by: Lucien Murray-Pitts
---
target/m68k/helper.c | 41 +++--
The BUSCR/PCR CR defines were missing for 68060, and the move_to/from helper
functions were also missing a decode for the 68060 M68K_CR_CAAR CR register.
Added missing defines, and respective decodes for all three CR registers to
the helpers.
Although this patch defines them, the implementation i
Signed-off-by: Yoshinori Sato
---
target/rx/cpu.c | 20 +++-
1 file changed, 3 insertions(+), 17 deletions(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index a6dde613ab..e3d76af55d 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -72,9 +72,8 @@ static void rx_cpu_reset(
From: Philippe Mathieu-Daudé
While the VIRT machine can use different microcontrollers,
the RX62N microcontroller is tied to the RX62N CPU core.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-virt.c | 8
1 file changed, 8 insertions(+)
diff --git a/
On m68k there are two varities of stack pointers, USP with SSP or ISP/MSP.
Only the 68020/30/40 support the MSP register the stack swap helpers dont
support this feature.
This patch adds this support, as well as comments to CPUM68KState to
make it clear how stacks are handled
Signed-off-by: Luc
From: Richard Henderson
There are so many different forms of each RX instruction
that it will be very useful to be able to look at the bytes
to see on which path a bug may lie.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <201906070
From: Richard Henderson
Many of the multi-part prints have been eliminated by previous
patches. Eliminate the rest of them.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-22-ys...@users.sourceforge.jp>
Tested-by
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-18-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 19 +++
1 file changed, 19 insertions(+)
diff --git a/MAINTAINER
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-virt.c | 22 ++
target/rx/cpu.c | 22 --
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c
index ed0a3a1da0..4cfe2e3123 100644
--- a/hw/rx/rx-virt.c
+++ b/hw/rx/rx-v
From: Richard Henderson
Issue an error if no kernel, no bios, and not qtest'ing.
Fixes make check-qtest-rx: test/qom-test.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-16-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signe
From: Richard Henderson
We were eliding all zero indexes. It is only ld==0 that does
not have an index in the instruction. This also allows us to
avoid breaking the final print into multiple pieces.
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-1
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-4-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
[PMD: Use newer QOM style, split cpu-qom.h, restrict access to
extable array, use rx_cpu_tlb_fill() extracted from patch of
Yoshinori Sa
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-10-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/bitops.h | 38 +
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-17-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
pick ed65c02993 target/rx: Add RX to SysEmuTarget
pick 01372568ae tests: Add rx to machine-none-t
This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-8-ys...@users.sourcef
Hello.
This patch series is added Renesas RX target emulation.
Changes for v19.
Follow tcg changes.
Cleanup cpu.c.
simplify rx_cpu_class_by_name and rx_load_image move to rx-virt.
My git repository is bellow.
git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190616
Testing binaries
renesas_tmr: 8bit timer modules.
renesas_cmt: 16bit compare match timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philip
From: Richard Henderson
Note that the ld == 3 case handled by prt_ldmi is decoded as
XCHG_rr and cannot appear here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-21-ys...@users.sourceforge.jp>
Tested-by: Philip
From: Richard Henderson
Collected, to be used in the next patch.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-23-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
From: Philippe Mathieu-Daudé
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-11-ys...@users.sourceforge.jp>
Tested-by: Philippe Math
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-5-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
include/disas/dis-asm.h |5 +
target/rx/disas.c | 1480 +
From: Richard Henderson
This has consistency with prt_ri(). It loads all data before
beginning output. It uses exactly one call to prt() to emit
the full instruction.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49
From: Philippe Mathieu-Daudé
Add two tests for the rx-virt machine, based on the recommended test
setup from Yoshinori Sato:
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03586.html
- U-Boot prompt
- Linux kernel with Sash shell
These are very quick tests:
$ avocado run -t arch:rx
rx62n - RX62N cpu.
rx-virt - RX QEMU virtual target.
Signed-off-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-9-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
[PMD: Use TYPE_RX62N_CPU, use #define for RX
This part only supported RXv1 instructions.
Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-2-ys...@users
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-3-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
[PMD: Removed tlb_fill, extracted from patch of Yoshinori Sato
'Convert to CPUClass::tlb_fill']
Signed
This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-6-ys...@users.sourcefo
Add cpu-param.h
Remove CPU_COMMON
Use env_cpu
Signed-off-by: Yoshinori Sato
---
target/rx/cpu-param.h | 31 +++
target/rx/cpu.h | 21 +
target/rx/cpu.c | 1 +
target/rx/op_helper.c | 6 +++---
4 files changed, 36 insertions(+), 23 del
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Type: series
Message-id: 20190616142836.
> Aleksandar: Can we use SEMIHOSTING on KVM MIPS?
>
You can assume the answer is no, we can't. But James Hogan, who maintains
MIPS KVM, may have different view, and his answer would override mine.
Yours,
Aleksandar
> For ARM Peter said:
>
> "semihosting hooks either SVC or HLT instructions, and
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
This patch adds support for user wait instructions in KVM. Availability
of the user wait instructions is indicated by the presence of the CPUID
feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. User wait instructions may
be executed at any
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
UMONITOR arms address monitoring hardware using an address. A store
to an address within the specified address range triggers the
monitoring hardware to wake up the processor waiting in umwait.
UMWAIT instructs the processor to ente
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index
E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.
This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
guest.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingq
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Message-id: 20190616142836.10614-1-ys...
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Type: series
Message-id: 20190616142836.
Make kvmppc_xive_disconnect() able to undo the changes of a partial
execution of kvmppc_xive_connect() and use it to perform rollback.
Based-on: <20190614165920.12670-2-...@kaod.org>
Signed-off-by: Greg Kurz
---
hw/intc/spapr_xive_kvm.c | 48 --
1 fi
On Fri, 14 Jun 2019 17:31:18 +0800
elohi...@gmail.com wrote:
> From: Xie Yongji
>
> Besides virtio 1.0 transitional devices, we should also
> set "start_on_kick" flag for legacy devices (virtio 0.9).
>
> Signed-off-by: Xie Yongji
> ---
Reviewed-by: Greg Kurz
> hw/virtio/virtio.c |
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Message-id: 20190616142836.10614-1-ys...
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Type: series
Message-id: 20190616142836.
It turns out we can't fix this without also fixing
our implementation of signal trampolines.
** Changed in: qemu
Status: New => Confirmed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1832916
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190616142836.10614-1-ys...@users.sourceforge.jp
Type: series
Subject: [Qemu-devel] [PATCH v20
On Sun, 16 Jun 2019 23:28:15 +0900
Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato
> Reviewed-by: Richard Henderson
> Message-Id: <20190607091116.49044-4-ys...@users.sourceforge.jp>
> Signed-off-by: Richard Henderson
> [PMD: Use newer QOM style, split cpu-qom.h, restrict access to
> ext
Patchew URL:
https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support
Type: series
Message-id: 20190616142836.
On Sun, 16 Jun 2019 23:28:17 +0900
Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato
THere is no point in sending it as separate patch,
If you'd merged this patch into 3/24 I'd ack it.
So pls merge it there.
> ---
> target/rx/cpu.c | 20 +++-
> 1 file changed, 3 insertions(
On Sun, 16 Jun 2019 23:28:29 +0900
Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato
> ---
> hw/rx/rx-virt.c | 22 ++
> target/rx/cpu.c | 22 --
> 2 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c
>
On Sun, 16 Jun 2019 23:28:33 +0900
Yoshinori Sato wrote:
> From: Philippe Mathieu-Daudé
>
> Some RX peripheral using 8bit and 16bit registers.
> Added 8bit and 16bit APIs.
probably should go before 13/24 (i.e. before actual users start using it)
this patch causes checkpatch errors but it uses
On Sun, 16 Jun 2019 08:18:18 -0700 (PDT)
no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20190616142836.10614-1-ys...@users.sourceforge.jp/
>
>
to fix MAINTAINERS warning, you can add new entry there at
the first patch that introduces new directory/file and get rid of 23/2
On Mon, 10 Jun 2019 21:39:12 +0800
Tao Xu wrote:
> On 6/7/2019 12:45 AM, Igor Mammedov wrote:
> > On Thu, 6 Jun 2019 11:00:33 +0800
> > Tao Xu wrote:
> >
> ...
> >>
> >> But the kernel HMAT can read othe Memory Side Cache Information except
> >> SMBIOS entries and the host HMAT tables also ha
On Wed, 8 May 2019 14:17:24 +0800
Tao Xu wrote:
> From: Liu Jingqi
>
> Add -numa hmat-cache option to provide Memory Side Cache Information.
> These memory attributes help to build Memory Side Cache Information
> Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).
>
> Signed-off
On Wed, 8 May 2019 14:17:26 +0800
Tao Xu wrote:
> From: Liu Jingqi
>
> OSPM evaluates HMAT only during system initialization.
> Any changes to the HMAT state at runtime or information
> regarding HMAT for hot plug are communicated using _HMA method.
>
> _HMA is an optional object that enables
While working on a Go (www.golang.org) port for riscv, I've run
into issues with atomics (namely LR/SC) on qemu-system-riscv64.
There are several reproducers for this problem including one
using gcc builtin atomics:
https://gist.github.com/4a6f656c/8433032a3f70893a278259f8108aad90
And a version
Patchew URL: https://patchew.org/QEMU/20190616191900.gh61...@hippo.sing.id.au/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
Type: series
Message-id: 20190616191900.gh61...@h
Check page flags before letting an invalid pc cause a SIGSEGV.
Prepare for eventially validating PROT_EXEC. The current wrinkle being
that we have a problem with our implementation of signals. We should
be using a vdso like the kernel, but we instead put the trampoline on
the stack. In the mean
These functions are not used, and are not usable in the
context of code generation, because we never have a helper
return address to pass in to them.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst_useronly_template.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --
At present we have a potential error in that helper_retaddr contains
data for handle_cpu_signal, but we have not ensured that those stores
will be scheduled properly before the operation that may fault.
The "proper" C11 function from for this is
atomic_signal_fence(). This expands to a compiler
The following changes since commit f3d0bec9f80e4ed7796fffa834ba0a53f2094f7f:
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2019-06-14'
into staging (2019-06-14 14:46:13 +0100)
are available in the Git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/fo
From: Li Hangjing
When a guest which doesn't support multiqueue is migrated with a multi queues
vhost-user-blk deivce, a crash will occur like:
0 qemu_memfd_alloc (name=, size=562949953421312,
seals=, fd=0x7f87171fe8b4, errp=0x7f87171fe8a8) at
util/memfd.c:153
1 0x7f883559d7cf in vhost_log
update expected files and drop them from allowed diff list.
Fixes: 4a4418369d6 ("q35: fix mmconfig and PCI0._CRS")
Signed-off-by: Michael S. Tsirkin
---
tests/bios-tables-test-allowed-diff.h | 8
tests/data/acpi/q35/DSDT | Bin 7815 -> 7841 bytes
tests/data/acpi/q35/DSDT.
As expected files have been updated, make sure we
do not forget to remove them from the allowed
diff list.
Signed-off-by: Michael S. Tsirkin
---
tests/data/acpi/rebuild-expected-aml.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/data/acpi/rebuild-expected-aml.sh
b/tests/data/ac
On 6/16/19 5:37 AM, Mark Cave-Ayland wrote:
> Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
> registers are in host endian order" functions getVSR() and putVSR() which used
> to convert the VSR registers into host endian order are no longer required.
>
> Signed-off-by:
On 14/06/2019 19:33, Stefan Hajnoczi wrote:
> On Fri, Jun 14, 2019 at 10:13:04AM +1000, Alexey Kardashevskiy wrote:
>>
>>
>> On 13/06/2019 23:08, Philippe Mathieu-Daudé wrote:
>>> Hi Alexey,
>>>
>>> On 6/13/19 7:09 AM, Alexey Kardashevskiy wrote:
This adds a trace point which prints every l
On 6/16/19 5:37 AM, Mark Cave-Ayland wrote:
> Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
> registers are in host endian order" functions getVSR() and putVSR() which used
> to convert the VSR registers into host endian order are no longer required.
>
> Signed-off-by:
On 6/14/19 10:11 AM, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> Afterwise is "wise after the fact", as in "hindsight".
> Here we meant "afterwards" (as in "subsequently"). Fix it.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
> ---
> tcg/README | 2 +-
> 1 file changed, 1
On 6/14/19 10:11 AM, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> This will allow us to trace 16B-long memory accesses.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
> ---
> trace-events | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/trace-events b
On Fri, 14 Jun 2019 at 19:45, Greg Kurz wrote:
>
> On Fri, 14 Jun 2019 17:31:17 +0800
> elohi...@gmail.com wrote:
>
> > From: Xie Yongji
> >
> > In order to avoid migration issues, we introduce a "use-started"
> > property to the base virtio device to indicate whether use
> > "started" flag or no
On 6/14/19 10:11 AM, Alex Bennée wrote:
> start_exclusive();
> +cpu->in_exclusive_work_context = true;
> wi->func(cpu, wi->data);
> +cpu->in_exclusive_work_context = false;
> end_exclusive();
Is there a reason not to put those into sta
On 6/14/19 6:53 AM, vandersonmr wrote:
> +void HELPER(inc_exec_freq)(void *ptr)
> +{
> +TranslationBlock* tb = (TranslationBlock*) ptr;
> +atomic_inc(&tb->exec_freq);
> +}
...
> +DEF_HELPER_FLAGS_1(inc_exec_freq, TCG_CALL_NO_RWG, void, ptr)
...
> uint32_t flags; /* flags defining in wh
On Mon, 3 Jun 2019 at 18:54, Philippe Mathieu-Daudé wrote:
>
> Hi Hongbo, Ard.
>
> On 4/18/19 6:04 AM, Hongbo Zhang wrote:
> > Following the previous patch, this patch adds peripheral devices to the
> > newly introduced SBSA-ref machine.
> >
> > Signed-off-by: Hongbo Zhang
> > ---
> > hw/arm/sbs
On 6/14/19 6:53 AM, vandersonmr wrote:
> A new hash map was added to store the accumulated execution
> frequency of the TBs even after tb_flush events. A dump
> function was also added as a way to visualize these frequencies.
>
> Signed-off-by: vandersonmr
> ---
> accel/tcg/translate-all.c | 59
On 6/14/19 6:53 AM, vandersonmr wrote:
> Added -execfreq to enable execution frequency counting and dump
> all the TB's addresses and their execution frequency at the end
> of the execution.
>
> Signed-off-by: vandersonmr
> ---
> linux-user/exit.c | 5 +
> linux-user/main.c | 7 +++
> 2
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