Add instruction patterns to cover the "transfer between
Arm core and extension register" spaces (A7.8 and A7.9
in DDI0406C.c). We omit VMSR/VMRS because they might
have side effects (for stores to special regs) or give
results dependent on previous execution (for loads).
Signed-off-by: Peter Mayde
On Thu, 6 Jun 2019 at 09:51, Alex Bennée wrote:
>
> As I've been reviewing a lot of this recently and I'm going to put
> together a pull request I'd better keep an eye on it.
>
> Signed-off-by: Alex Bennée
> ---
> MAINTAINERS | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --g
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> Stefan Brankovic (8):
> target/ppc: Optimize emulation of lvsl and lvsr instructions
> target/ppc: Optimize emulation of vsl and vsr instructions
> target/ppc: Optimize emulation of vpkpx instruction
> target/ppc: Optimize emulation of vgbbd inst
When scripts/get_maintainer.pl reports something like
John Doe (maintainer:Overall)
the user is left to wonder *which* of our three "Overall" sections
applies: the one under "Guest CPU cores (TCG)", or the one under
"Guest CPU Cores (KVM)", or the one under "Usermode emulation".
Rename sect
v2:
* PATCH 2:
- Commit message cleaned up [Eric]
- Several headlines improved further [Philippe, Aleksandar, Cornelia]
- "Common code" improved, too
Markus Armbruster (3):
MAINTAINERS: Drop redundant L: qemu-devel@nongnu.org
MAINTAINERS: Improve section headlines
MAINTAINERS: Polish h
Signed-off-by: Markus Armbruster
---
MAINTAINERS | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index bdc82c5735..6dc5b5cb67 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -65,7 +65,7 @@ F: *
F: */
Responsible Disclosure
Redundant since commit c9a19d5b95 "MAINTAINERS: add all-match entry
for qemu-devel@".
Signed-off-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 11 ---
1 file changed, 11 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a96829ea83..8d0d8c09cc 10064
On 06/06/2019 19:08, Greg Kurz wrote:
> If KVM is too old to support XIVE native exploitation mode, we might end
> up using the emulated XIVE after CAS. This is sub-optimal if KVM in-kernel
> XICS is available, which is the case most of the time.
>
> Also, an old KVM may not allow to destroy and r
From: Benjamin Herrenschmidt
It should be generic Hypervisor Virtualization interrupts for HV
directed rings and traditional External Interrupts for the OS directed
ring.
Don't generate anything for the user ring as it isn't actually
supported.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-
This patchset converts the Arm VFP instructions to use decodetree
instead of the current hand-written decode.
We gain:
* a more maintainable decoder which doesn't live in one big function
* correct prioritization of UNDEF exceptions against "VFP disabled"
exceptions and "M-profile lazy FP sta
Convert the VFP load/store multiple insns to decodetree.
This includes tightening up the UNDEF checking for pre-VFPv3
CPUs which only have D0-D15 : they now UNDEF for any access
to D16-D31, not merely when the smallest register in the
transfer list is in D16-D31.
This conversion does not try to sh
Convert the VFP single load/store insns VLDR and VSTR to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 73 ++
target/arm/translate.c | 22 +-
target/arm/vfp.decode | 7
3 files changed, 82 insertions(+
From: Richard Henderson
Typo comparing the sign of the field, twice, instead of also comparing
the mask of the field (which itself encodes both position and length).
Reported-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20190604154225.26992-1-richard.hender...@linaro.org
Sign
Convert the VRINTA/VRINTN/VRINTP/VRINTM instructions to decodetree.
Again, trans_VRINT() is temporarily left in translate.c.
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 60 +++-
target/arm/vfp-uncond.decode | 5 +++
2 files changed, 43 inserti
Convert the VDIV instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 21 +
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 20 deletions(-)
diff --git a/targ
Convert the VCVT integer-to-float instructions to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 58 ++
target/arm/translate.c | 12 +--
target/arm/vfp.decode | 6
3 files changed, 65 insertions(+), 11 dele
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase
Convert the VFP two-register transfer instructions to decodetree
(in the v8 Arm ARM these are the "Advanced SIMD and floating-point
64-bit move" encoding group).
Again, we expand out the sequences involving gen_vfp_msr() and
gen_msr_vfp().
Signed-off-by: Peter Maydell
---
target/arm/translate-v
Convert the VFP VNMLA instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 34 ++
target/arm/translate.c | 19 +--
target/arm/vfp.decode | 5 +
3 files changed, 40 insertions(+), 18 dele
Move the trans_*() functions we've just created from translate.c
to translate-vfp.inc.c. This is pure code motion with no textual
changes (this can be checked with 'git show --color-moved').
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 337 +
Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 VFP encodings. At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.
We need to have one decoder for the unconditional insns and one for
the conditional insns,
Convert the VFP VABS instruction to decodetree.
Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or
VFPGen2OpDPFn because none of the operations which use this format
and support short vectors will need it.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 167 +
Convert the VADD instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 6 +-
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate
Convert the VCVTA/VCVTN/VCVTP/VCVTM instructions to decodetree.
trans_VCVT() is temporarily left in translate.c.
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 72 +---
target/arm/vfp-uncond.decode | 6 +++
2 files changed, 39 insertions(+), 39 d
Factor out the VFP access checking code so that we can use it in the
leaf functions of the decodetree decoder.
We call the function full_vfp_access_check() so we can keep
the more natural vfp_access_check() for a version which doesn't
have the 'ignore_vfp_enabled' flag -- that way almost all VFP
i
Convert the "double-precision" register moves to decodetree:
this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP.
Note that the conversion process has tightened up a few of the
UNDEF encoding checks: we now correctly forbid:
* VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10
* VMOV-fro
At the moment our -cpu max for AArch32 supports VFP short-vectors
because we always implement them, even for CPUs which should
not have them. The following commits are going to switch to
using the correct ID-register-check to enable or disable short
vector support, so we need to turn it on explicit
Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans
functions which perform the memory accesses by going via the TCG
globals cpu_F0s and cpu_F0d, to use local TCG temps instead.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 46 +--
Convert the VNMUL instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 24
target/arm/translate.c | 7 +--
target/arm/vfp.decode | 5 +
3 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/targ
Convert the VFP VMLS instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 38 ++
target/arm/translate.c | 8 +--
target/arm/vfp.decode | 5 +
3 files changed, 44 insertions(+), 7 deletions(-)
diff
Convert the VSUB instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 6 +-
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate
The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.
Signed-off-by: Peter Maydell
---
target/arm/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tar
Convert the VNEG instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 6 +-
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate
Convert the VCVT (between floating-point and fixed-point) instructions
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 124 +
target/arm/translate.c | 57 +--
target/arm/vfp.decode | 10 +++
3 files c
Convert the VFP VNMLS instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 42 ++
target/arm/translate.c | 24 +--
target/arm/vfp.decode | 5
3 files changed, 48 insertions(+), 23 delet
Convert the VSQRT instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 20
target/arm/translate.c | 14 +-
target/arm/vfp.decode | 5 +
3 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/
Convert the VMUL instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 5 +
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-
Convert the VCVTT, VCVTB instructions that deal with conversion
from half-precision floats to f32 or 64 to decodetree.
Since we're no longer constrained to the old decoder's style
using cpu_F0s and cpu_F0d we can perform a direct 16 bit
load of the right half of the input single-precision register
Convert the VCVT double/single precision conversion insns to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 48 ++
target/arm/translate.c | 13 +
target/arm/vfp.decode | 6 +
3 files changed, 55 insertio
Convert the VFP round-to-integer instructions VRINTR, VRINTZ and
VRINTX to decodetree.
These instructions were only introduced as part of the "VFP misc"
additions in v8A, so we check this. The old decoder's implementation
was incorrectly providing them even for v7A CPUs.
Signed-off-by: Peter Mayd
Convert the VMINNM and VMAXNM instructions to decodetree.
As with VSEL, we leave the trans_VMINMAXNM() function
in translate.c for the moment.
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 41
target/arm/vfp-uncond.decode | 5 +
2 files
Convert the VFP comparison instructions to decodetree.
Note that comparison instructions should not honour the VFP
short-vector length and stride information: they are scalar-only
operations. This applies to all the 2-operand instructions except
for VMOV, VABS, VNEG and VSQRT. (In the old decode
Convert the VCVTT and VCVTB instructions which convert from
f32 and f64 to f16 to decodetree.
Since we're no longer constrained to the old decoder's style
using cpu_F0s and cpu_F0d we can perform a direct 16 bit
store of the right half of the input single-precision register
rather than doing a loa
Convert the VSEL instructions to decodetree.
We leave trans_VSEL() in translate.c for now as this allows
the patch to show just the changes from the old handle_vsel().
In the old code the check for "do D16-D31 exist" was hidden in
the VFP_DREG macro, and assumed that VFPv3 always implied that
D16-
Convert the VJCVT instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 24
target/arm/translate.c | 12 +---
target/arm/vfp.decode | 4
3 files changed, 29 insertions(+), 11 deletions(-)
diff --git a
For VFP short vectors, the VFP registers are divided into a
series of banks: for single-precision these are s0-s7, s8-s15,
s16-s23 and s24-s31; for double-precision they are d0-d3,
d4-d7, ... d28-d31. Some banks are "scalar" meaning that
use of a register within them triggers a pure-scalar or
mixed
Convert the VFP fused multiply-add instructions (VFNMA, VFNMS,
VFMA, VFMS) to decodetree.
Note that in the old decode structure we were implementing
these to honour the VFP vector stride/length. These instructions
were introduced in VFPv4, and in the v7A architecture they
are UNPREDICTABLE if the
Convert the VFP VMLA instruction to decodetree.
This is the first of the VFP 3-operand data processing instructions,
so we include in this patch the code which loops over the elements
for an old-style VFP vector operation. The existing code to do this
looping uses the deprecated cpu_F0s/F0d/F1s/F1
Convert the "single-precision" register moves to decodetree:
* VMSR
* VMRS
* VMOV between general purpose register and single precision
Note that the VMSR/VMRS conversions make our handling of
the "should this UNDEF?" checks consistent between the two
instructions:
* VMSR to MVFR0, MVFR1, MVFR
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 10 ++
target/arm/translate.c | 8 +---
target/arm/vfp.decode | 5 +
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
This is a good way to debug the DT creation for current PowerNV
machines and new ones to come.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 046f0a83c8e5..ed6892466793 100644
--- a/hw/ppc/pnv.c
+++ b/hw/pp
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> Optimize altivec instruction vgbbd (Vector Gather Bits by Bytes by Doubleword)
> All ith bits (i in range 1 to 8) of each byte of doubleword element in
> source register are concatenated and placed into ith byte of appropriate
> doubleword element in des
Convert the VFP VMOV (immediate) instruction to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 129 +
target/arm/translate.c | 27 +--
target/arm/vfp.decode | 5 ++
3 files changed, 136 insertions(+), 25 delet
Convert the float-to-integer VCVT instructions to decodetree.
Since these are the last unconverted instructions, we can
delete the old decoder structure entirely now.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 72 ++
target/arm/translate.c | 241 +-
On Thu, Jun 06, 2019 at 06:19:43PM +0200, Kashyap Chamarthy wrote:
> Hi folks,
>
> Today I learnt about some obscure PCIe-related properties, in context of
> the adding PCIe root ports to a guest, namely:
>
> io-reserve
> mem-reserve
> bus-reserve
> pref32-reserve
> pref64-res
On Thursday, 6 June 2019 13:12:32 CEST Daniel P. Berrangé wrote:
> On Wed, Jun 05, 2019 at 11:36:54PM +0200, Pino Toscano wrote:
> > Rewrite the implementation of the ssh block driver to use libssh instead
> > of libssh2. The libssh library has various advantages over libssh2:
> > - easier API for
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> Optimize Altivec instruction vclzd (Vector Count Leading Zeros Doubleword).
> This instruction counts the number of leading zeros of each doubleword element
> in source register and places result in the appropriate doubleword element of
> destination reg
On Wed, Jun 05, 2019 at 05:43:23PM -0300, Eduardo Habkost wrote:
> On Wed, Jun 05, 2019 at 12:06:59PM -0400, Cleber Rosa wrote:
> > On Tue, May 21, 2019 at 12:06:35AM +0200, Philippe Mathieu-Daudé wrote:
> > > Similar to the x86_64/pc test, it boots a Linux kernel on an
> > > Emcraft board and veri
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> +for (i = 0; i < 2; i++) {
> +if (i == 0) {
> +/* Get high doubleword element of vB in avr. */
> +get_avr64(avr, VB, true);
> +} else {
> +/* Get low doubleword element of vB in avr. */
> +
Instead of bdrv_can_store_new_bitmap, rework this as
bdrv_add_persistent_dirty_bitmap. This makes a more obvious symmetry
with bdrv_remove_persistent_dirty_bitmap. Most importantly, we are free
to modify the driver state because we know we ARE adding a bitmap
instead of simply being asked if we CAN
On Thu, 6 Jun 2019 19:47:32 +0200
Cédric Le Goater wrote:
> This is a good way to debug the DT creation for current PowerNV
> machines and new ones to come.
>
> Signed-off-by: Cédric Le Goater
> ---
Reviewed-by: Greg Kurz
> hw/ppc/pnv.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff -
On Thu, Jun 6, 2019 at 5:55 AM Bin Meng wrote:
>
> On Thu, May 30, 2019 at 11:36 AM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Thu, May 30, 2019 at 11:14 AM Alistair Francis
> > wrote:
> > >
> > > On Wed, May 29, 2019 at 1:52 AM Bin Meng wrote:
> > > >
> > > > The largest pci bus number s
On Fri, May 17, 2019 at 3:12 PM Alistair Francis
wrote:
>
> This should be the last series bringing the patches from the RISC-V fork
> into mainline QEMU.
>
> Dayeol Lee (1):
> target/riscv: Fix PMP range boundary address bug
>
> Michael Clark (3):
> disas/riscv: Disassemble reserved compresse
When adding new persistent dirty bitmaps, we only check constraints
against currently stored bitmaps, and ignore the pending number and size
of any bitmaps yet to be stored.
Rework the "can_store" and "remove" interface to explicit "add" and "remove",
and begin keeping track of the queued burden w
Allow propagating error code information from
bdrv_remove_persistent_dirty_bitmap as well.
Give it an interface that matches the newly revised
bdrv_add_persistent_dirty_bitmap, including removing the persistent flag
when the operation succeeds and refusing to operate on bitmaps that are
not persis
When we check to see if we can store a bitmap, we don't check how many
we've queued up. This can cause a problem saving bitmaps on close
instead of when we request them to be added. With the stricter add
interface, prohibit these bitmaps specifically.
To match, make the remove interface more stric
This simply makes this function a little more convenient to call, and in
a forthcoming patch gives us a return code we can report to the
caller. (Which in turn makes THOSE functions easier to call.)
While we're here, remove the offset+size arguments which are only ever
called with the same values
Similarly to the previous commit, we need to also keep a ledger of the
additional directory size burden that we've not yet committed so we can
reject new additions sooner instead of later.
Signed-off-by: John Snow
---
block/qcow2.h| 1 +
block/qcow2-bitmap.c | 13 -
2 files
From: Sarah Harris
This includes:
- TCG translations for each instruction
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 2937
1 file changed, 2937 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c
From: Sarah Harris
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Signed-off-by: Michael Rolnik
---
target/avr/cpu-qom.h | 83 +++
target/avr/cpu.c | 558 +++
target/avr/cpu.h | 24
From: Sarah Harris
A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs
include a lot of on-board peripherals.
Signed-off-by: Michael Rolnik
---
hw/Kconfig | 1 +
hw/avr/Kconf
On 05/06/2019 09:43, Laurent Vivier wrote:
> On 05/06/2019 08:32, Mark Cave-Ayland wrote:
>> On 04/06/2019 22:23, Laurent Vivier wrote:
>>
>>> This patch breaks something in the libcrypto.
>>>
>>> I've been able to reproduce the problem with Fedora 29:
>>>
>>> dnf install 'dnf-command(download)'
>>
From: Sarah Harris
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
Signed-o
From: Sarah Harris
Stubs for unimplemented instructions and helpers for instructions that need to
interact with QEMU.
SPM and WDR are unimplemented because they require emulation of complex
peripherals.
The implementation of SLEEP is very limited due to the lack of peripherals to
generate wake
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
---
target/avr/insn.decode | 176 +
1 file changed, 176 insertions(+)
create mode 100644 target/avr/insn.decode
diff --git a/target/a
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet
From: Sarah Harris
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 6 ++
arch_init.c | 2 ++
configure | 6 ++
default-configs/avr-softmmu.mak | 5 +
include/disas/dis-asm.h | 6 ++
include/sysemu/arch_in
On 06/06/2019 20:24, Laurent Vivier wrote:
> On 05/06/2019 09:43, Laurent Vivier wrote:
>> On 05/06/2019 08:32, Mark Cave-Ayland wrote:
>>> On 04/06/2019 22:23, Laurent Vivier wrote:
>>>
This patch breaks something in the libcrypto.
I've been able to reproduce the problem with Fedor
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> Optimize Altivec instruction vclzh (Vector Count Leading Zeros Halfword).
> This instruction counts the number of leading zeros of each halfword element
> in source register and places result in the appropriate halfword element of
> destination register.
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> +/*
> + * We use this macro if one instruction is realized with direct
> + * translation, and second one with helper.
> + */
> +#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
> +static void glue(gen_, name0##_##name1)(DisasConte
On Thu, Jun 06, 2019 at 07:01:49PM +0200, Markus Armbruster wrote:
Stafford Horne writes:
On Mon, Jun 03, 2019 at 10:45:14AM +0200, Philippe Mathieu-Daudé wrote:
On 5/31/19 5:36 AM, Stafford Horne wrote:
> On Wed, May 29, 2019 at 05:08:52PM +0200, Markus Armbruster wrote:
>> When scripts/get_
On 6/5/19 3:47 AM, Maxim Levitsky wrote:
> On Mon, 2019-06-03 at 18:25 -0400, John Snow wrote:
>>
>> On 4/17/19 3:53 PM, Maxim Levitsky wrote:
>>> Phase bits are only set by the hardware to indicate new completions
>>> and not by the device driver.
>>>
>>> Signed-off-by: Maxim Levitsky
>>> ---
This adds an acceptance test that validates that a full blown Linux
guest can successfully boot in QEMU.
Changes from v5:
* Added explicit "--enable-slirp=git" to Travis CI configure line, as
these tests depend on "-netdev user" like networking.
* Bumped Fedora to most rece
This boots a Fedora 30 guest using edk2.
During the first Fedora 30 boot on aarch64, there's a filesystem
resize operation. The typical output is similar to:
[ 203.798938] EXT4-fs (sda2): resizing filesystem from 999168 to 999675
blocks
[ 203.823032] EXT4-fs (sda2): resized filesystem t
This is related to the the differences in in-tree and out-of-tree
builds in QEMU. For simplification, means my build directory.
Currently, by running a `make check-acceptance` one gets (in
tests/acceptance/avocado_qemu/__init__.py):
SRC_ROOT_DIR: /tests/acceptance/avocado_qemu/../../..
This
This depends on a proposed feature to Avocado, a new module that
"drains" data and processes it. In this case, a drainer for the
console socket file descriptor is used, and the data is sent to the
"console" logger.
This allows for a much better feedback of the test process, showing
boot data from
So that when binaries such as qemu-img are searched for, those in the
build tree will be favored. As a clarification, SRC_ROOT_DIR is
dependent on the location from where tests are executed, so they are
equal to the build directory if one is being used.
The original motivation is that Avocado lib
An Avocado Test ID[1] is composed by a number of components, but it
starts with the Test Name, usually a file system location that was
given to the loader.
Because the source directory is being given as a prefix to the
"tests/acceptance" directory containing the acceptance tests, the test
names wi
Tests using the avocado.utils.vmimage library make use of qemu-img,
and because it makes sense to use the version matching the rest of the
source code, let's make sure it gets built.
Its selection, instead of a possible qemu-img binary installed system
wide, is already dealt with by the change tha
This acceptance test, validates that a full blown Linux guest can
successfully boot in QEMU. In this specific case, the guest chosen is
Fedora version 30. It adds two different tests for machine types pc
and q35.
The method for checking the successful boot is based on "cloudinit"
and its "phone
On 6/6/19 1:16 AM, Cédric Le Goater wrote:
Hello Eddie,
On 04/06/2019 00:09, Eddie James wrote:
The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations
between the SOC (acting as a BMC) and a host processor in a server.
The XDMA engine exists on the AST2400, AST2500, and AST2
On Mon, Jun 03, 2019 at 02:18:19PM -0400, Laine Stump wrote:
> On 6/3/19 2:12 PM, Michael S. Tsirkin wrote:
> > On Mon, Jun 03, 2019 at 02:06:47PM -0400, Laine Stump wrote:
> > > On 5/28/19 10:54 PM, Michael S. Tsirkin wrote:
> > > > On Tue, May 28, 2019 at 05:14:22PM -0700, si-wei liu wrote:
> > >
Patchew URL: https://patchew.org/QEMU/20190606184159.979-1-js...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH 0/5] block/dirty-bitmap: check number and size
constraints against queued bitmaps
Type: se
On 6/6/19 7:24 PM, Markus Armbruster wrote:
> When scripts/get_maintainer.pl reports something like
>
> John Doe (maintainer:Overall)
>
> the user is left to wonder *which* of our three "Overall" sections
> applies: the one under "Guest CPU cores (TCG)", or the one under
> "Guest CPU Cores (
On 6/6/19 7:24 PM, Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> ---
> MAINTAINERS | 24 +++-
> 1 file changed, 11 insertions(+), 13 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index bdc82c5735..6dc5b5cb67 100644
> --- a/MAINTAINERS
> +++ b/MAINT
On 6/6/19 5:54 PM, no-re...@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20190606184159.979-1-js...@redhat.com/
>
>
>
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Subject: [Qemu-devel] [PATCH 0/5] block/dirty-bitm
On 5/3/19 9:37 PM, Eduardo Habkost wrote:
> Python 2 will reach end of life in January 1 2020. Declare it as
> deprecated.
>
> Signed-off-by: Eduardo Habkost
> ---
> configure| 8
> qemu-deprecated.texi | 8
> 2 files changed, 16 insertions(+)
>
> diff --git a/con
From: Philippe Mathieu-Daudé
Similar to the x86_64/pc test, it boots a Linux kernel on a Malta
machine and verify the serial is working.
Use the documentation added in commit f7d257cb4a17 to test
nanoMIPS kernels and the I7200 CPU.
This test can be run using:
$ avocado --show=console run -t
Hi,
It was a rainy week-end here, so I invested it to automatize some
of my MIPS tests.
The BootLinuxSshTest is not Global warming friendly, it is not
meant to run on a CI system but rather on a workstation previous
to post a pull request.
It can surely be improved, but it is a good starting poin
From: Philippe Mathieu-Daudé
This tests boots a Linux kernel on a Malta machine up to a
busybox shell on the serial console. Few commands are executed
before halting the machine (via reboot).
We use the initrd cpio image from the kerneltests project:
https://kerneltests.org/
If MIPS is a target
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