To summarize implications on libvirt...
This patch currently doesn't change the deprecation status of any machine
type, so it is effectively no-op metadata addition right now.
Libvirt version N can implement support for this today, and nothing would
change from a functional POV with QEMU 4.1.
At
On Wed, Jun 05, 2019 at 05:28:05PM +, Vladimir Sementsov-Ogievskiy wrote:
> 05.06.2019 20:12, Eric Blake wrote:
> > On 6/5/19 12:05 PM, Vladimir Sementsov-Ogievskiy wrote:
> >
> >>> By enabling TCP keepalives we are explicitly making the connection
> >>> less reliable by forcing it to be termi
Patchew URL:
https://patchew.org/QEMU/20190604161514.262241-1-vsement...@virtuozzo.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/ba
Daniel P. Berrangé writes:
> On Tue, May 28, 2019 at 08:12:24PM +0200, Markus Armbruster wrote:
>> We have a bunch of headers without multiple inclusion guards. Some are
>> clearly intentional, some look accidental. Too many for me to find out
>> by examining each of them, so I'm asking their m
Laurent Vivier writes:
> On 05/06/2019 15:05, Markus Armbruster wrote:
>> Laurent Vivier writes:
>>
>>> Add a new RNG backend using QEMU builtin getrandom function.
>>>
>>> v7: rebase on master
>>> Make rng-builtin asynchronous with QEMUBH (removed existing R-b)
>>
>> Pardon the ignorant q
Just ran the test with simavr, once it hit BREAK, gdb stopped
On Wed, Jun 5, 2019 at 7:12 PM Alex Bennée wrote:
>
> Michael Rolnik writes:
>
> > Richard.
> >
> > We use break instruction for testing. (Here
> > https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
> ).
> > Eac
On Wed, Jun 05, 2019 at 06:33:11PM +0100, Daniel P. Berrangé wrote:
[...]
> I wonder if there's a way to close the testing gap somehow ? Random idea
> would be a non-versioned "pc-no-deprecated" machine type, which blocks
> all use of deprecated features and does not promise any migration compat.
>
On Wed, Jun 05, 2019 at 04:44:03PM +0100, Daniel P. Berrangé wrote:
[...]
> Thus to answer your python 2 question, we should ask which of our build
> targets cannot support python 3 ?
>
> Obviously we know the answer to that is RHEL-7. Except there is some
> fuzziness in there because it depends o
On Tue, May 21, 2019 at 01:19:08AM +0200, Philippe Mathieu-Daudé wrote:
> Similar to the x86_64/pc test, it boots a Linux kernel on a Malta
> machine and verify the serial is working.
>
> Use the documentation added in commit f7d257cb4a17 to test
> nanoMIPS kernels and the I7200 CPU.
>
> This tes
On 05/06/2019 19:56, Markus Armbruster wrote:
> Laurent Vivier writes:
>
>> On 05/06/2019 15:05, Markus Armbruster wrote:
>>> Laurent Vivier writes:
>>>
Add a new RNG backend using QEMU builtin getrandom function.
v7: rebase on master
Make rng-builtin asynchronous with QE
Paolo, can you take this one please.
* Catherine Ho (catherine.h...@gmail.com) wrote:
> Commit 18269069c310 ("migration: Introduce ignore-shared capability")
> addes ignore-shared capability to bypass the shared ramblock (e,g,
> membackend + numa node). It does good to live migration.
>
> As told
Patchew URL:
https://patchew.org/QEMU/20190605162326.13896-1-alex.ben...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190605162326.13896-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [PATCH v1 0/4] softmmu de-macr
On 2/8/19 12:21 PM, Max Reitz wrote:
> On 07.02.19 07:56, Markus Armbruster wrote:
>> Max Reitz writes:
>>
>>> This patch allows specifying a discriminator that is an optional member
>>> of the base struct. In such a case, a default value must be provided
>>> that is used when no value is given.
v1: Patch1 fixed out-of-bounds assertions in hw/sd/sd.c
v2: Added patch2 that fixed the incorrect assertion for poll_fds
in util/main-loop.c based on the feedbacks from Peter Maydell
and Liam Merwick,
Lidong Chen (2):
sd: Fix out-of-bounds assertions
util/main-loop: Fix incorrect asse
Due to an off-by-one error, the assert statements allow an
out-of-bound array access.
Signed-off-by: Lidong Chen
Reviewed-by: Liam Merwick
Reviewed-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Li Qiang
Reviewed-by: Darren Kenny
---
hw/sd/sd.c | 4 ++--
1 file chang
The check for poll_fds in g_assert() was incorrect. The correct assertion
should check "n_poll_fds + w->num <= ARRAY_SIZE(poll_fds)" because the
subsequent for-loop is doing access to poll_fds[n_poll_fds + i] where i
is in [0, w->num).
Signed-off-by: Lidong Chen
Suggested-by: Peter Maydell
Sugge
On 05.06.19 18:22, Max Reitz wrote:
> On 05.06.19 03:15, John Snow wrote:
>> Running tests on a development branch (I haven't touched chardev stuff,
>> I swear!); I ran into the below crash where s->ioc was NULL. I don't
>> have the time to investigate at this exact moment, so please excuse the
>>
On 26.04.19 09:51, Paolo Bonzini wrote:
> On 23/04/19 18:55, Daniel P. Berrangé wrote:
>> ping - paolo/marc-andré - unless I'm missing something, it looks like
>> this chardev series slipped through the cracks and missed 4.0
>
> Yeah, it had a bug unfortunately. I'm looking at it RSN.
I’ll just
On Thu, May 30, 2019 at 11:13:41AM +1000, David Gibson wrote:
> On Thu, May 23, 2019 at 05:18:51PM -0300, Maxiwell S. Garcia wrote:
> > On Thu, May 23, 2019 at 09:29:52AM +1000, David Gibson wrote:
> > > On Mon, May 20, 2019 at 05:43:40PM -0300, Maxiwell S. Garcia wrote:
> > > > This handler was ad
On 6/5/19 12:36 PM, Daniel P. Berrangé wrote:
>>
>> Ok.
>>
>> One more thing to discuss then. Should I add keepalive directly to
>> BlockdevOptionsNbd?
>>
>> Seems more useful to put it into SocketAddress, to be reused by other socket
>> users..
>> But "SocketAddress" sounds like address, not li
Hi,
I am writing some code I'm hoping will be able to make it into Qemu, but I
can't seem to find what the baseline portability requirements are. I'm
specifically wondering about newer POSIX features like openat(), which seems
to be used in the 9p filesystem and nowhere else, and what version of
Expected table change is then handled like this:
1. add table to diff allowed list
2. change generating code (can be combined with 1)
3. maintainer runs a script to update expected +
blows away allowed diff list
Signed-off-by: Michael S. Tsirkin
---
tests/bios-tables-test-allowed-diff.h | 1
From: Wei Yang
build_append_foo() API doesn't need explicit endianness conversions
which eliminates a source of errors and it makes build_mcfg() look like
declarative definition of MCFG table in ACPI spec, which makes it easy
to review.
Signed-off-by: Wei Yang
Suggested-by: Igor Mammedov
Revie
From: Igor Mammedov
'family' option is not part of type 2 table and if user tries to use it
as such QEMU will error out with an unknow option error.
Drop it from docs lest it confuse users.
Fixes: b155eb1d04 ("smbios: document cmdline options for smbios type 2-4, 17
structures")
Signed-off-by:
The following changes since commit 8c1ecb590497b0349c550607db923972b37f6963:
Merge remote-tracking branch
'remotes/stsquad/tags/pull-testing-next-280519-2' into staging (2019-05-28
17:38:32 +0100)
are available in the Git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git ta
when binary of the tables is identical, there is no need to run iasl
to check that they are functionally equivalent.
Signed-off-by: Michael S. Tsirkin
---
tests/bios-tables-test.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/tests/bios-tables-test.c b/tes
From: Wei Yang
Now we have two identical build_mcfg functions.
Consolidate them in acpi/pci.c.
Signed-off-by: Wei Yang
v4:
* ACPI_PCI depends on both ACPI and PCI
* rebase on latest master, adjust arm Kconfig
v3:
* adjust changelog based on Igor's suggestion
Message-Id: <20190521062836.
Fail after comparing all tables: this way
user gets the full list of tables that need
to be updated or whitelisted.
Signed-off-by: Michael S. Tsirkin
---
tests/bios-tables-test.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/bios-tables-test.c b/tests/bios-table
On 6/5/19 2:48 PM, Eric Blake wrote:
> This also made me wonder if we should start a deprecation clock to
> improve the nbd-server-start command to use SocketAddress instead of
> SocketAddressLegacy. If we revive Max's work on implementing a default
> branch for a union discriminator
> (https://l
On Wed, Jun 05, 2019 at 04:50:06PM +0100, Daniel P. Berrangé wrote:
> On Mon, Jun 03, 2019 at 02:26:49PM +0200, Markus Armbruster wrote:
> > John Snow writes:
> >
> > > On 5/31/19 3:24 PM, Eduardo Habkost wrote:
> > >> Long story short: I would really like to drop support for Python
> > >> 2 in Q
This pull request is not for master.
Hi Cornelia,
The following changes since commit dd5382ad6deb5a07ec3c72b2c3cce36ce1307a57:
vfio-ccw: support async command subregion (2019-06-05 07:55:18 +0200)
are available in the Git repository at:
https://github.com/davidhildenbrand/qemu.git tags/s39
On Thu, May 23, 2019 at 09:40:06AM -0400, Cleber Rosa wrote:
> - Original Message -
> > From: "Philippe Mathieu-Daudé"
> > To: "Cleber Rosa" , "Eduardo Habkost"
> >
> > Cc: qemu-devel@nongnu.org, "Peter Maydell" ,
> > qemu-...@nongnu.org, "Philippe Mathieu-Daudé"
> > , "Andrew Baumann"
Logic mostly courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h| 6 +
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 34
target/s390x/vec_string_helper.c | 45 ++
Complicated stuff. Provide two different helpers for CC an !CC handling.
We might want to add more helpers later.
zero_search() and match_index() are courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/Makefile.objs | 2 +-
target/s39
CPU_DoubleU is primarily used to reinterpret between integer and floats.
We don't really need this functionality. So let's just keep it simple
and use an uint64_t.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
linux-user/s390x/signal.c | 4 +-
target/s390x/arch_dump.c
Core logic courtesy of Richard H.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h| 6
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 31 +
target/s390x/vec_string_helper.c | 57
The PoP (z14, 7-382) says:
Doublewords to the right of the doubleword in which the
highest-numbered facility bit is assigned for a model
may or may not be stored.
However, stack protection in certain binaries can't deal with that.
"gzip" example code:
f1b4: a7 08 00 03
Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be
able to make use of it.
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: David Hildenbrand
---
target/s390x/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/s390x/cpu.c b/target/s390x/
used_stfl_bytes is 0, before initialized via prepare_stfl() on the
first invocation. We have to move the calculation of max_bytes after
prepare_stfl().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/misc_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 dele
Unfortunately, there is no easy way to avoid looping over all elements
in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and
all element types. Especially for different values of rt, the compiler
might be able to optimize the code a lot.
Add s390_vec_write_element().
Reviewed-by
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed, 30 insertions(+)
diff --
1. We'll reuse op_vcdg() for similar instructions later, prepare for
that.
2. We'll reuse vop64_2() later for other instructions.
We have to mangle the erm (effective rounding mode) and the m4 into
the simd_data(), and properly unmangle them again.
Make sure to restore the erm before triggerin
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing
helper function.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 +++
ta
As far as I can see, there is only a tiny difference.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 4
target/s390x/translate_vx.inc.c | 21 +
target/s390x/vec_fpu_helper.c
Let's add it to the max model, so we can enable it.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/gen-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index c346b76bdf..a818c80332 100644
-
We can reuse most of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
We don't care about the other two missing base features:
- S390_FEAT_DFP_PACKED_CONVERSION
- S390_FEAT_GROUP_GEN13_PTFF
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
hw/s390x/s390-virtio-ccw.c | 2 ++
target/s390x/cpu_models.c | 4 ++--
target/s390x/gen-features.c | 1
Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H.
Add s390_vec_read_element() that can deal with element sizes.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h| 6 +++
target/s390x/insn-data.def | 2 +
target/s
Let's add all HWCAPs that we can support under TCG right now, when the
respective CPU facilities are enabled.
Cc: Riku Voipio
Cc: Laurent Vivier
Cc: Cornelia Huck
Cc: Laurent Vivier
Cc: Richard Henderson
Acked-by: Laurent Vivier
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbran
Handling is similar to data exceptions, however we can always store the
VXC into the lowore and the FPC:
z14 PoP, 6-20, "Vector-Exception Code"
When a vector-processing exception causes a pro-
gram interruption, a vector-exception code (VXC) is
stored at location 147, and zeros are sto
From: Richard Henderson
This replaces the target-specific implementations for VSEL.
Signed-off-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/translate_vx.inc.c | 38 ++---
1 file changed, 6 insertions(+), 32 deletions(-)
diff --git a/targ
Vector floating-point instructions will require these functions, so
allow to use them from other files.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/fpu_helper.c | 4 ++--
target/s390x/internal.h | 4
2 files changed, 6 insertions(+), 2 deletions(-)
d
11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store")
revealed that the vregs are not aligned to 16 bytes. Align them to
16 bytes, to avoid segfault'ing on x86.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/cpu.h | 2 +-
1 file changed, 1 insertio
Very similar to VECTOR FP DIVIDE.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 +
4 files chang
Provide for all three instructions all four combinations of cc bit and
s bit.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 12
target/s390x/insn-data.def | 6 ++
target/s390x/translate_vx.inc.c | 51
target/
Similar to VECTOR FP ADD.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 +
4 files changed, 24 i
We can reuse float64_dcmask().
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 21 +++
target/s390x/vec_fpu_helper.c | 37 +++
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 4 +++
target/s390x/translate_vx.inc.c | 23
target/s390x/vec_fpu_helper.c | 48 +
4 files changed,
We can reuse most of the infrastructure added for VECTOR FP ADD.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 +
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed, 30 insertions(+)
diff --
1. We'll reuse op_vfa() for similar instructions later, prepare for
that.
2. We'll reuse vop64_3() for other instructions later.
3. Take care of modifying the vector register only if no trap happened.
- on traps, flags are not updated and no elements are modified
- traps don't modify the fpc f
On 6/5/19 12:55 PM, H. Peter Anvin wrote:
> Hi,
>
> I am writing some code I'm hoping will be able to make it into Qemu, but I
> can't seem to find what the baseline portability requirements are. I'm
> specifically wondering about newer POSIX features like openat(), which seems
> to be used in th
The only FP instruction we can implement without an helper.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 52 +
2 files changed, 54 insertions(+)
diff --git a/target
On 6/5/19 3:13 PM, Eduardo Habkost wrote:
>> IOW, I don't think RHEL-7 support as a build platform blocks us from
>> dropping py2. We merely need to tweak our build platforms doc to clarify
>> our intent wrt add-on yum repos.
>
> If we clarify the docs in QEMU 4.1, is there anything that
> preven
On Wed, Jun 05, 2019 at 03:42:39PM -0500, Eric Blake wrote:
> On 6/5/19 3:13 PM, Eduardo Habkost wrote:
>
> >> IOW, I don't think RHEL-7 support as a build platform blocks us from
> >> dropping py2. We merely need to tweak our build platforms doc to clarify
> >> our intent wrt add-on yum repos.
>
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++
4 files changed, 30 insertions(+)
diff --
Dave Martin has recently posted a kernel patch set for
supporting ARMv8.5 Branch Target Identification in userland.
http://lists.infradead.org/pipermail/linux-arm-kernel/2019-May/654654.html
While that support is not yet in the upstream kernel, it looks
to be close to its final form. Note tha
On Wed, Jun 05, 2019 at 12:06:59PM -0400, Cleber Rosa wrote:
> On Tue, May 21, 2019 at 12:06:35AM +0200, Philippe Mathieu-Daudé wrote:
> > Similar to the x86_64/pc test, it boots a Linux kernel on an
> > Emcraft board and verify the serial is working.
> >
> > If ARM is a target being built, "make
We can reuse some of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
This is a collection of related defines for notes, copied
from glibc's . We're not going to use all of these
right away, but it seemed foolish to cherry-pick only the
ones we need now.
Signed-off-by: Richard Henderson
---
include/elf.h | 48
1 fi
Take care of reading/indicating the 32-bit elements.
Reviewed-by: Richard Henderson
Signed-off-by: David Hildenbrand
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 ++
target/s390x/vec_fpu_helper.c | 3
For aarch64, this includes the GNU_PROPERTY_AARCH64_FEATURE_1_BTI bit,
which indicates that the image should be mapped with guarded pages.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 83 +++-
1 file changed, 75 insertions(+), 8 deletions(-)
The value of btype for syscalls is CONSTRAINED UNPREDICTABLE,
so we need to make sure that the value is 0 before clone,
fork, or syscall return.
The kernel sets btype for the signal handler as if for a call.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/cpu_loop.c | 7 +++
linux-
This will build with older toolchains, without the upstream support
for -mbranch-protection. Such a toolchain will produce a warning
in such cases,
ld: warning: /tmp/ccyZt0kq.o: unsupported GNU_PROPERTY_TYPE (5) \
type: 0xc000
but the still places the note at the correct location in the bina
Transform the prot bit to a qemu internal page bit, and save
it in the page tables.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 2 ++
linux-user/syscall_defs.h | 4
linux-user/mmap.c | 16
target/arm/translate-a64.c | 6 +++---
4 files cha
On Tue, May 28, 2019 at 11:13 AM Markus Armbruster wrote:
>
> We have a bunch of headers without multiple inclusion guards. Some are
> clearly intentional, some look accidental. Too many for me to find out
> by examining each of them, so I'm asking their maintainers.
>
> Why do I ask? I'd like
On May 21, 2019 12:07 AM, "Philippe Mathieu-Daudé" wrote:
>
> Avoid to log empty lines in console debug logs.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
Acked-by: Aleksandar Markovic
> tests/acceptance/boot_linux_console.py | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
The kernel will return -EINVAL for bits set in the prot argument
that are unknown or invalid. Previously we were simply cropping
out the bits that we care about.
Introduce validate_prot_to_pageflags to perform this check in a
single place between the two syscalls. Differentiate between
the targe
On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
wrote:
>
> The current PMP check function checks for env->priv which is not the effective
> memory privilege mode.
>
> For example, mstatus.MPRV could be set while executing in M-Mode, and in that
> case the privilege mode for the PMP check should be
On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
wrote:
>
> The PMP should be checked when doing a page table walk, and report access
> fault exception if the to-be-read PTE failed the PMP check.
>
> Suggested-by: Jonathan Behrens
> Signed-off-by: Hesham Almatary
> ---
> target/riscv/cpu.h
On Jun 5, 2019 11:03 PM, "Richard Henderson"
wrote:
>
> This is a collection of related defines for notes, copied
> from glibc's . We're not going to use all of these
> right away, but it seemed foolish to cherry-pick only the
> ones we need now.
>
But you are doing exactly that: cherry-picking,
Joel is on vacation so here it is again.
> Begin forwarded message:
>
> From: Alistair Francis
> Subject: Re: [j...@sing.id.au: atomic failures on qemu-system-riscv64]
> Date: June 5, 2019 at 7:19:53 PM GMT+1
> To: "j...@sing.id.au" , "pal...@sifive.com"
>
> Cc: "ma...@decred.org" , "m...@carl
On Tue, May 21, 2019 at 01:19:09AM +0200, Philippe Mathieu-Daudé wrote:
> This tests boots a Linux kernel on a Malta machine up to a
> busybox shell on the serial console. Few commands are executed
> before halting the machine (via reboot).
>
> We use the initrd cpio image from the kerneltests pro
Rewrite the implementation of the ssh block driver to use libssh instead
of libssh2. The libssh library has various advantages over libssh2:
- easier API for authentication (for example for using ssh-agent)
- easier API for known_hosts handling
- supports newer types of keys in known_hosts
Use AP
On 6/5/19 3:49 PM, Eduardo Habkost wrote:
> On Wed, Jun 05, 2019 at 03:42:39PM -0500, Eric Blake wrote:
>> On 6/5/19 3:13 PM, Eduardo Habkost wrote:
>>
IOW, I don't think RHEL-7 support as a build platform blocks us from
dropping py2. We merely need to tweak our build platforms doc to cla
Patchew URL: https://patchew.org/QEMU/20190605213654.9785-1-ptosc...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190605213654.9785-1-ptosc...@redhat.com
Type: series
Subject: [Qemu-devel] [PATCH v6] ssh: switch from
On Wed, 5 Jun 2019 at 23:07, Alistair Francis wrote:
>
> On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
> wrote:
> >
> > The PMP should be checked when doing a page table walk, and report access
> > fault exception if the to-be-read PTE failed the PMP check.
> >
> > Suggested-by: Jonathan Behren
Patchew URL:
https://patchew.org/QEMU/20190605205706.569-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v6 0/6] linux-user/aarch64: Support PROT_BTI
Type: series
Message-id: 20190605
On Wed, 05 Jun 2019 13:59:53 PDT (-0700), ma...@decred.org wrote:
Joel is on vacation so here it is again.
Begin forwarded message:
From: Alistair Francis
Subject: Re: [j...@sing.id.au: atomic failures on qemu-system-riscv64]
Date: June 5, 2019 at 7:19:53 PM GMT+1
To: "j...@sing.id.au" , "pal
Hi,
Looking at QEMU source code, I am puzzled regarding how migration backwards
compatibility is preserved regarding X86CPU.
As I understand it, fields that are based on KVM capabilities and guest runtime
usage are defined in VMState subsections in order to not send them if not
necessary.
This
On 6/4/2019 10:34 PM, Cornelia Huck wrote:
On Fri, 24 May 2019 16:18:38 +0800
Tao Xu wrote:
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
Availability of the user wait instructions is indicated by the presence
of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5].
The pat
Two trivial patches to make save_xbzrle_page() a little bit easy to
understand.
Wei Yang (2):
migration/xbzrle: update cache and current_data in one place
migration/xbzrle: cleanup the handling cache miss condition
migration/ram.c | 36 +---
1 file changed, 17
For cache miss condition not in last_stage, we need to insert data into
cache. When this step succeed, current_data should be updated. While no
matter these checks pass or not, -1 is returned.
Based on this, the logic in cache miss handling could be simplified a
little.
Signed-off-by: Wei Yang
-
When we are not in the last_stage, we need to update the cache if page
is not the same.
Currently this procedure is scattered in two places and mixed with
encoding status check.
This patch extract this general step out to make the code a little bit
easy to read.
Signed-off-by: Wei Yang
---
mig
On Wed, May 29, 2019 at 11:10:14AM +0530, Aravinda Prasad wrote:
> This patch adds support in QEMU to handle "ibm,nmi-register"
> and "ibm,nmi-interlock" RTAS calls.
>
> The machine check notification address is saved when the
> OS issues "ibm,nmi-register" RTAS call.
>
> This patch also handles
On Mon, Jun 03, 2019 at 01:17:23PM +0200, Greg Kurz wrote:
> On Mon, 3 Jun 2019 12:12:43 +0200
> Greg Kurz wrote:
>
> > On Wed, 29 May 2019 11:10:14 +0530
> > Aravinda Prasad wrote:
> >
> > > This patch adds support in QEMU to handle "ibm,nmi-register"
> > > and "ibm,nmi-interlock" RTAS calls.
On Wed, May 29, 2019 at 11:10:32AM +0530, Aravinda Prasad wrote:
> Memory error such as bit flips that cannot be corrected
> by hardware are passed on to the kernel for handling.
> If the memory address in error belongs to guest then
> the guest kernel is responsible for taking suitable action.
> P
On Sun, May 19, 2019 at 04:54:22AM +0800, Like Xu wrote:
> The global smp variables in ppc are replaced with smp machine properties.
>
> A local variable of the same name would be introduced in the declaration
> phase if it's used widely in the context OR replace it on the spot if it's
> only used
On Wed, Jun 05, 2019 at 11:52:41PM -0300, Eduardo Habkost wrote:
> On Sun, May 19, 2019 at 04:54:22AM +0800, Like Xu wrote:
> > The global smp variables in ppc are replaced with smp machine properties.
> >
> > A local variable of the same name would be introduced in the declaration
> > phase if it
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