Philippe Mathieu-Daudé writes:
> On 3/15/19 3:51 PM, Markus Armbruster wrote:
>> Leading underscores are ill-advised because such identifiers are
>> reserved. Trailing underscores are merely ugly. Strip both.
>>
>> Our header guards commonly end in _H. Normalize the exceptions.
>>
>> Done wi
Daniel P. Berrangé writes:
...
>> Thanks, this fixes it! I had a related question about the way
>> qemu_file_monitor_add_watch works.
>>
>> Am I correct in understanding that if there is already a watch on a dir,
>> we return back mon->nextid++ i.e the next free id. Why don't we return
>> back th
On Fri, Mar 15, 2019 at 06:12:18PM +0100, Philippe Mathieu-Daudé wrote:
> TYPE_QAUTHZ is an abstract object of type TYPE_OBJECT. All other
> are children of TYPE_QAUTHZ, thus also objects.
>
> Keep INTERFACE_CHECK() for interfaces, and use OBJECT_CHECK() on
> objects.
Hmm
#define OBJECT_CHECK(
On Fri, Mar 15, 2019 at 7:15 AM Bastian Koppelmann
wrote:
>
> during the refactor to decodetree we removed the manual decoding that is
> necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
> and c.fsw/c.sd. This reintroduces the manual parsing and the
> omited implementation.
>
>
On Fri, Mar 15, 2019 at 01:24:42PM -0400, Bandan Das wrote:
> Daniel P. Berrangé writes:
> ...
> >> Thanks, this fixes it! I had a related question about the way
> >> qemu_file_monitor_add_watch works.
> >>
> >> Am I correct in understanding that if there is already a watch on a dir,
> >> we retu
Ed Vielmetti writes:
> We have been trying to merge the Gitlab runner patches for arm64
> for over a year now; see
>
> https://gitlab.com/gitlab-org/gitlab-runner/merge_requests/725
Yes I found that one. I'm trying to work out exactly how there build
system works. It seems to build all archite
Signed-off-by: Marc-André Lureau
---
MAINTAINERS |2 +-
docs/interop/index.rst |2 +-
docs/interop/vhost-user.rst | 1351 +++
docs/interop/vhost-user.txt | 1219 ---
4 files changed, 1353 insertions(+), 1221
On Fri, Mar 15, 2019 at 09:58:47AM +0100, Roger Pau Monne wrote:
> Or if it's not possible to honor the hinted address an error is returned
> instead. This makes it easier to spot the actual failure, instead of
> failing later on when the caller of xen_remap_bucket realizes the
> mapping has not be
There are a couple of options hosted at Packet - Shippable, Codefresh, and
Drone. I perhaps know more about Drone than the others. Each of them have a
supported/sponsored version which can be used to produce arm64 binaries
natively.
I'll admit to dropping into this conversation in mid-stream thoug
From: Antonio Ospite
The configure script breaks when the qemu source directory is in a path
containing white spaces, in particular the list of targets is not
correctly generated when calling "./configure --help".
To avoid this issue, refuse to run the configure script if there are
spaces or col
On Fri, Mar 15, 2019 at 09:54:42AM +, Paul Durrant wrote:
> AFAICT xen_remap_bucket() is always called with a NULL vaddr argument
> if entry->vaddr_base == NULL, and called with vaddr ==
> entry->vaddr_base in the other case, so I'd say the vaddr argument is
> superfluous.
I don't think that's
On Fri, Mar 15, 2019 at 7:42 AM Chih-Min Chao wrote:
>
> From: Jim Wilson
>
> Signed-off-by: Jim Wilson
> Signed-off-by: Chih-Min Chao
This looks good, I didn't dig into every register here, but I'm
assuming it's correct.
Reviewed-by: Alistair Francis
Alistair
> ---
> configure
On Fri, Mar 15, 2019 at 7:09 AM Chih-Min Chao wrote:
>
> From: Jim Wilson
>
> Signed-off-by: Jim Wilson
> Signed-off-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Alistair
> ---
> configure | 1 +
> gdb-xml/riscv-32bit-fpu.xml | 6 +-
> gdb-xml/riscv-64bit-cpu.xml |
Daniel P. Berrangé writes:
> On Fri, Mar 15, 2019 at 06:12:18PM +0100, Philippe Mathieu-Daudé wrote:
>> TYPE_QAUTHZ is an abstract object of type TYPE_OBJECT. All other
>> are children of TYPE_QAUTHZ, thus also objects.
>>
>> Keep INTERFACE_CHECK() for interfaces, and use OBJECT_CHECK() on
>> ob
Am Wed, 13 Mar 2019 02:06:39 +0100
schrieb Philippe Mathieu-Daudé :
> On Tue, Mar 12, 2019 at 6:44 PM Markus Armbruster
> wrote:
[...]
> > I gathered the machine types, mapped them to source files, which I
> > fed to get_maintainer.pl. Results are appended. If you're cc'ed,
> > MAINTAINERS fing
On Fri, Mar 15, 2019 at 6:45 AM Chih-Min Chao wrote:
>
> This is the 5th version of the patch set, based on the Jim's previous work,
> http://lists.nongnu.org/archive/html/qemu-riscv/2019-02/msg00059.html
>
> v4 -> v5:
>- rebase 7074ab1
>- update the register xml files to
On Fri, 29 Sep 2017 at 11:12, Daniel P. Berrange wrote:
>
> The https://gitlab.com/keycodemap/keycodemapdb/ repo contains a
> data file mapping between all the different scancode/keycode/keysym
> sets that are known, and a tool to auto-generate lookup tables for
> different combinations
Hi Dan; a
On Fri, Mar 15, 2019 at 7:01 AM Chih-Min Chao wrote:
>
> From: Jim Wilson
>
> The gdb CSR xml file has registers in documentation order, not numerical
> order, so we need a table to map the register numbers. This also adds
> fairly standard gdb hooks to access xml specified registers.
>
> notice
On Fri, Mar 15, 2019 at 06:14:09PM +, Anthony PERARD wrote:
> On Fri, Mar 15, 2019 at 09:58:47AM +0100, Roger Pau Monne wrote:
> > Or if it's not possible to honor the hinted address an error is returned
> > instead. This makes it easier to spot the actual failure, instead of
> > failing later
On Fri, 15 Mar 2019 at 18:26, Antonio Ospite wrote:
>
> From: Antonio Ospite
>
> The configure script breaks when the qemu source directory is in a path
> containing white spaces, in particular the list of targets is not
> correctly generated when calling "./configure --help".
>
> To avoid this i
On 3/15/19 12:50 PM, Antonio Ospite wrote:
> From: Antonio Ospite
>
> The configure script breaks when the qemu source directory is in a path
> containing white spaces, in particular the list of targets is not
> correctly generated when calling "./configure --help".
>
> To avoid this issue, refu
On 3/15/19 1:40 PM, Peter Maydell wrote:
> If you do this after the point where we make the source path absolute, you
> can skip the realpath (which avoids the problem that 'realpath' doesn't exist
> on OSX by default). It will also then be after the handling of the
> --source-path option argument
> From: Thomas Huth
> Subject: Re: Maintainers, please tell us how to boot your machines!
>
> > On Tue, Mar 12, 2019 at 6:44 PM Markus Armbruster
> > wrote:
> [...]
> > > I gathered the machine types, mapped them to source files, which I
> > > fed to get_maintainer.pl. Results are appended. If
On 3/15/19 11:42 AM, Philippe Mathieu-Daudé wrote:
> Hi,
>
>>From my previous experience with the tests/ patches, I understood we
> could still send PR that improve testing after soft freeze.
> This series doesn't modify the QEMU binaries, it add EDK2 firmware blobs
> in roms/ and rules to rebuild
Ed Vielmetti writes:
> There are a couple of options hosted at Packet - Shippable, Codefresh, and
> Drone. I perhaps know more about Drone than the others. Each of them have a
> supported/sponsored version which can be used to produce arm64 binaries
> natively.
>
> I'll admit to dropping into t
On 3/15/19 7:30 AM, Peter Maydell wrote:
> This commit is the same as commit 823e1b3818f9b10b824ddc which we
> had to revert in commit 942f99c825fc94c8b1a4, except that the bug
> which was preventing EDK2 guest firmware running has been fixed:
> kvm_arm_reset_vcpu() now calls write_list_to_cpustate
On 3/15/19 3:30 PM, Peter Maydell wrote:
> At the moment the Arm implementations of kvm_arch_{get,put}_registers()
> don't support having QEMU change the values of system registers
> (aka coprocessor registers for AArch32). This is because although
> kvm_arch_get_registers() calls write_list_to_cpu
Set msi_nonbroken as true for the PLIC.
According to the comment located here:
https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
the msi_nonbroken variable should be set to true even if they don't
support MSI. In this case that is what we
On 15/03/2019 18:38, Anthony PERARD wrote:
> On Fri, Mar 15, 2019 at 06:14:09PM +, Anthony PERARD wrote:
>> On Fri, Mar 15, 2019 at 09:58:47AM +0100, Roger Pau Monne wrote:
>>> Or if it's not possible to honor the hinted address an error is returned
>>> instead. This makes it easier to spot the
Patchew URL: https://patchew.org/QEMU/cover.1552659955.git.bala...@eik.bme.hu/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
time ma
This adds DDC support to ati-vga and connects i2c-ddc to provide EDID
info that is read by guests to find available screen modes. Not sure
if this is 100% correct yet but at least MorphOS is happy with it and
starts in a high resolution mode instead of 640x480 (although its
splash screen is still n
The bitbang i2c implementation is also useful for other device models
such as DDC in display controllers. Move the header to include/hw/i2c/
to allow it to be used from other device models and adjust users of
this include. This also reverts commit 2b4c1125ac which is no longer
needed.
Signed-off-b
Version 3 keeps bitbang_i2c.h and moves it to include/hw/i2c/
otherwise same as version 2.
BALATON Zoltan (2):
i2c: Move bitbang_i2c.h to include/hw/i2c/
ati-vga: Implement DDC and EDID info from monitor
hw/display/Kconfig | 2 ++
hw/display/ati.c | 43
Patchew URL: https://patchew.org/QEMU/cover.1552689690.git.bala...@eik.bme.hu/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
time ma
On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
wrote:
>
> v3:
> - Add a patch to remove some dead code
> - Rebase on master
> v2:
> - Add a patch for SiFive U SMP support
> - Rebase on master
>
> Alistair Francis (3):
> riscv: pmp: Log pmp access errors as guest errors
> riscv: sifive_u:
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc25820fe..3199238ba0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -398,7 +398,10 @@ static void riscv_
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6d3fbc
From: Michael Clark
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev
Cc: Richard Henderson
Cc: Alistair Francis
Reviewed-by: Laurent Vivier
Signed-off-by: Michael Clark
Signed-off-by: Alistair F
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc3ddc0ae4..568c4cd637 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -80,12 +80,6 @@ const char * const riscv_intr_names[] =
From: Michael Clark
If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:
pc = mtvec + cause * 4
In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync
From: Michael Clark
This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.
Fixes WFI doesn't return when a IPI is issued:
- https://github.com/riscv/riscv-qemu/issues/132
To test:
1) App
From: Michael Clark
We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.
This logic was previo
From: Kito Cheng
This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.
Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.
Cc: Palmer Dabbelt
Cc: Sagar Kara
From: Michael Clark
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
---
disas/riscv.c | 138
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
---
Makefile.objs | 1 +
target/riscv/cpu_helper.c | 12 +++-
target/riscv/trace-events | 2 ++
3 files changed, 6 insertions(+), 9 deletions(-)
cre
From: Michael Clark
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
---
hw/ri
Signed-off-by: Alistair Francis
---
target/riscv/pmp.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 15a5366616..b11c4ae22f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -113,10 +113,11 @@ stat
v3:
- Add a patch to remove some dead code
- Rebase on master
v2:
- Add a patch for SiFive U SMP support
- Rebase on master
Alistair Francis (3):
riscv: pmp: Log pmp access errors as guest errors
riscv: sifive_u: Allow up to 4 CPUs to be created
target/riscv: Remove unused struct
Kito C
https://github.com/Randrianasulu/pmon/commits/2014
hopefully it will stay this way.
Anyone know what license I must pick for this?
3-clause BSD? 4-clause BSD? (from Copyright file it lists 4 terms)
* $Id: Copyright,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */
/*
*
Fix committed in slirp/src/socket.c
** Changed in: qemu
Status: New => Fix Committed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1817865
Title:
sorecvfrom freezes guest
Status in QEMU:
Quoting Peter Maydell (2019-03-14 10:56:28)
> In commit d0dead3b6df7f6cd970e we changed to shipping the u-boot
> sources as a tarball, to work around a problem where they
> contained a file and directory that had the same name except
> for case, which was preventing QEMU's source tarball being
> un
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