>
> [...]
> > diff --git a/hw/rdma/rdma_hmp.c b/hw/rdma/rdma_hmp.c
> > new file mode 100644
> > index 00..c5814473c5
> > --- /dev/null
> > +++ b/hw/rdma/rdma_hmp.c
> > @@ -0,0 +1,30 @@
> > +/*
> > + * RDMA device: Human Monitor interface
>
> The file name and this comment are a bit akward
From: Suraj Jitindar Singh
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
availability of the large decrementer for a guest.
Signed-off-by: Suraj Jitindar Singh
Message-Id: <20190301024317.22137-1-sjitindarsi...@gmail.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr.c
From: Alexey Kardashevskiy
The "systempagesize" name suggests that it is the host system page size
while it is the smallest page size of memory backing the guest RAM so
let's rename it to stop confusion. This should cause no behavioral change.
Signed-off-by: Alexey Kardashevskiy
Message-Id: <20
From: Greg Kurz
Commit b8165118f52c broke CPU hotplug tests for old machine types:
$ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 ./tests/cpu-plug-test
-m=slow
/ppc64/cpu-plug/pseries-3.1/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.12-sxxm/device-add/2x3x1&maxcpus=6: OK
/ppc64
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: Alexey Kardashevskiy
Message-Id: <20190228225759.21328-2-faro...@linux.ibm.com>
Signed-off-by: David Gibson
---
target/ppc/excp_helper.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff -
From: Alexey Kardashevskiy
The current code assumes that we can address more bits on a PCI bus
for DMA than we really can but there is no way knowing the actual limit.
This makes a better guess for the number of levels and if the kernel
fails to allocate that, this increases the level numbers ti
From: Suraj Jitindar Singh
Implement support to allow KVM guests to take advantage of the large
decrementer introduced on POWER9 cpus.
To determine if the host can support the requested large decrementer
size, we check it matches that specified in the ibm,dec-bits device-tree
property. We also n
The following changes since commit f5b4c31030f45293bb4517445722768434829d91:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into
staging (2019-03-09 17:35:48 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-4.
From: Suraj Jitindar Singh
The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability
for mitigations for indirect branch speculation. Currently the available
values are broken (default), fixed-ibs (fixed by serialising indirect
branches) and fixed-ccd (fixed by diabling the count ca
From: Suraj Jitindar Singh
Enable the large decrementer by default for the pseries-4.0 machine type.
It is disabled again by default_caps_with_cpu() for pre-POWER9 cpus
since they don't support the large decrementer.
Signed-off-by: Suraj Jitindar Singh
Message-Id: <20190301024317.22137-4-sjitin
SPAPR_MEMORY_BLOCK_SIZE is logically a difference in memory addresses, and
hence of type hwaddr which is 64-bit. Previously it wasn't marked as such
which means that it could be treated as 32-bit. That will work in some
circumstances but if multiplied by another 32-bit value it could lead to
a 32
From: Suraj Jitindar Singh
Prior to POWER9 the decrementer was a 32-bit register which decremented
with each tick of the timebase. From POWER9 onwards the decrementer can
be set to operate in a mode called large decrementer where it acts as a
n-bit decrementing register which is visible as a 64-b
From: Suraj Jitindar Singh
The spapr_caps cap-cfpc, cap-sbbc and cap-ibs are used to control the
availability of certain mitigations to the guest. These haven't been
implemented under TCG, it is unlikely they ever will be, and it is unclear
as to whether they even need to be.
As such, make failu
From: Greg Kurz
The RTAS event hotplug code for machine types 2.8 and newer depends on
the CAS negotiated ov5 in order to work properly. However, there's no
CAS when running under qtest. There has been a tentative to trick the
code by faking the OV5_HP_EVT bit, but it turned out to break other
as
From: Suraj Jitindar Singh
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate
the requirement for a hw-assisted version of the count cache flush
workaround.
The count cache flush workaround is a software workaround which can be
used to flush the count cache on context switch.
From: Suraj Jitindar Singh
The H_CALL H_PAGE_INIT can be used to zero or copy a page of guest
memory. Enable the in-kernel H_PAGE_INIT handler.
The in-kernel handler takes half the time to complete compared to
handling the H_CALL in userspace.
Signed-off-by: Suraj Jitindar Singh
Message-Id: <2
From: Cédric Le Goater
By default on P9, the HW CAM line (23bits) is hardwired to :
0x000||0b1||4Bit chip number||7Bit Thread number.
When the block group mode is enabled at the controller level (PowerNV),
the CAM line is changed for CAM compares to :
4Bit chip number||0x001||7Bit
From: Fabiano Rosas
There are four scenarios being handled in this function:
- single stepping
- hardware breakpoints
- software breakpoints
- fallback (no debug supported)
A future patch will add code to handle specific single step and
software breakpoints cases so let's split each scenario in
From: Suraj Jitindar Singh
If we allocate a hash page table then we know that the guest won't be
using process tables, so set the partition table entry maintained for
the guest to zero. If this isn't done, then the guest radix bit will
remain set in the entry. This means that when the guest calls
From: Suraj Jitindar Singh
There are currently 3 mitigations the availability of which is controlled
by the spapr-caps mechanism, cap-cfpc, cap-sbbc, and cap-ibs. Enable these
mitigations by default for the pseries-4.0 machine type.
By now machine firmware should have been upgraded to allow thes
From: Mark Cave-Ayland
When using -drive to configure the hd drive for the Old World machine, the node
name "disk" should be used instead of the "hd" alias.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20190307212058.4890-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: David Gibson
---
hw/ppc
From: Fabiano Rosas
This is in preparation for a refactoring of the kvm_handle_debug
function in the next patch.
Signed-off-by: Fabiano Rosas
Message-Id: <20190228225759.21328-4-faro...@linux.ibm.com>
Signed-off-by: David Gibson
---
target/ppc/kvm.c | 47 --
From: Cédric Le Goater
The NSR register of the HV ring has a different, although similar, bit
layout. TM_QW3_NSR_HE_PHYS bit should now be raised when the
Hypervisor interrupt line is signaled. Other bits TM_QW3_NSR_HE_POOL
and TM_QW3_NSR_HE_LSI are not modeled. LSI are for special interrupts
res
From: Cédric Le Goater
We will use it to get the CPU interrupt presenter in XIVE when the
TIMA is accessed from the indirect page.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-3-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 16
hw/p
From: Mark Cave-Ayland
All TCG vector operations require pointers to the base address of the vector
rather than separate access to the top and bottom 64-bits. Convert the VMX TCG
instructions to use a new avr_full_offset() function instead of avr64_offset()
which can then itself be written as a s
From: Cédric Le Goater
The POWER9 PowerNV machine will use a XIVE interrupt presenter type.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-6-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 6 +++---
hw/ppc/pnv_core.c | 2 +-
include/hw/ppc/
From: Andrew Randrianasulu
Original commit message:
This patch adds an emulation model for i2c controller found on most of the FSL
SoCs.
It also integrates the RTC (ds1338) that sits on the i2c Bus with e500 machine
model.
Patch was originally written by Amit Singh Tomar
see http://patchwork.
From: Cédric Le Goater
The POWER9 and POWER8 processors have different interrupt controllers,
and reporting their state requires calling different helper routines.
However, the interrupt presenters are still handled in the higher
level pic_print_info() routine because they are not related to the
From: Mark Cave-Ayland
Instead of having multiple copies of the offset calculation logic, move it to a
single vsrl_offset() function.
This commit also renames the existing get_vsr()/set_vsr() functions to
get_vsrl()/set_vsrl() which better describes their purpose.
Signed-off-by: Mark Cave-Aylan
From: Cédric Le Goater
The PowerNV machine can perform indirect loads and stores on the TIMA
on behalf of another CPU. Give the controller the possibility to call
the TIMA memory accessors with a XiveTCTX of its choice.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-4-...@kao
From: Cédric Le Goater
The PowerNV machine with need to encode the block id in the source
interrupt number before forwarding the source event notification to
the Router.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-5-...@kaod.org>
Signed-off-by: David Gibson
---
hw/intc/x
From: Mark Cave-Ayland
By using the VsrD macro in avr64_offset() the same offset calculation can be
used regardless of the host endian. This allows get_avr64() and set_avr64() to
be simplified accordingly.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20190307180520.13868-6-mark.cave-ayl...@ilan
From: Cédric Le Goater
This is a simple helper to translate XSCOM addresses to MMIO addresses
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-13-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_psi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff -
From: Cédric Le Goater
Reset all regs but keep the MMIO BAR enabled as it is at realize time.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-14-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_psi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw
From: Mark Cave-Ayland
When using -drive to configure the hd drive for the New World machine, the node
name "disk" should be used instead of the "hd" alias.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20190307212058.4890-3-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: David Gibson
---
hw/ppc
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-12-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_lpc.c | 10 +-
hw/ppc/pnv_psi.c | 4 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_l
From: Alexey Kardashevskiy
On sPAPR vfio_listener_region_add() is called in 2 situations:
1. a new listener is registered from vfio_connect_container();
2. a new IOMMU Memory Region is added from rtas_ibm_create_pe_dma_window().
In both cases vfio_listener_region_add() calls
memory_region_iommu_
From: Mark Cave-Ayland
Now that all VSX registers are stored in host endian order, there is no need
to go via different accessors depending upon the register number. Instead we
introduce vsr64_offset() and use it directly from within get_cpu_vsr{l,h}() and
set_cpu_vsr{l,h}().
This also allows us
From: Mark Cave-Ayland
When VSX support was initially added, the fpr registers were added at
offset 0 of the VSR register and the vsrl registers were added at offset
1. This is in contrast to the VMX registers (the last 32 VSX registers) which
are stored in host-endian order.
Switch the fpr/vsrl
From: Cédric Le Goater
The PowerNV LPC Controller exposes different sets of registers for
each of the functional units it encompasses, among which the OPB
(On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST
Controller.
The mapping addresses of each register range are correct but the si
From: Cédric Le Goater
The POWER9 and POWER8 processors have a different set of devices and a
different device tree layout.
Signed-off-by: Cédric Le Goater
Message-Id: <20190306085032.15744-8-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 27 +--
From: Mark Cave-Ayland
Instead of having multiple copies of the offset calculation logic, move it to a
single fpr_offset() function.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <20190307180520.13868-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: David Gibson
--
From: Philippe Mathieu-Daudé
The t0 tcg_temp register is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20190309214255.9952-2-f4...@amsat.org>
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 14 +++---
1 file changed, 3 insertions(+), 1
From: Cédric Le Goater
We now have enough support to let the XSCOM test run on POWER9.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-13-...@kaod.org>
Signed-off-by: David Gibson
---
tests/pnv-xscom-test.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/tests/pnv-xscom
From: Cédric Le Goater
This is a simple model of the POWER9 XIVE interrupt controller for the
PowerNV machine which only addresses the needs of the skiboot
firmware. The PowerNV model reuses the common XIVE framework developed
for sPAPR as the fundamentals aspects are quite the same. The
differen
From: Cédric Le Goater
To ease the introduction of the PSI bridge model for POWER9, abstract
the POWER chip differences in a PnvPsi class model and introduce a
specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt
controller is still XICS whereas POWER9 uses the new XIVE model.
Sig
From: Cédric Le Goater
To ease the introduction of the OCC model for POWER9, provide a new
class attributes to define XSCOM operations per CPU family and a PSI
IRQ number.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20190307223548.20516-9-...@kaod.org>
Signed-off-by:
From: Cédric Le Goater
It will ease the introduction of the LPC Controller model for POWER9.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20190307223548.20516-5-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_lpc.c
From: Cédric Le Goater
Activate only stop0 and stop1 levels. We should not need more levels
when under QEMU.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-15-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 15 +++
1 file changed, 15 insertions(+)
From: Cédric Le Goater
The OCC on POWER9 is very similar to the one found on POWER8. Provide
the same routines with P9 values for the registers and IRQ number.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-10-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c
From: Mark Cave-Ayland
It isn't possible to include internal.h from cpu.h so move the Vsr* macros
into cpu.h alongside the other VMX/VSX register access functions.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20190307180520.13868-4-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Richard Henderson
From: Cédric Le Goater
We now have enough support to boot a PowerNV machine with a POWER9
processor. Allow HV mode on POWER9.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-16-...@kaod.org>
Signed-off-by: David Gibson
---
target/ppc/translate_init.inc.c | 3 ++-
1 file chan
From: Cédric Le Goater
This is just a simple reminder that SerIRQ routing should be
addressed.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-8-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_lpc.c | 14 ++
include/hw/ppc/pnv_lpc.h | 2 ++
2 fi
From: Cédric Le Goater
The ISA bus has a different DT nodename on POWER9. Compute the name
when the PnvChip is realized, that is before it is used by the machine
to populate the device tree with the ISA devices.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-6-...@kaod.org>
S
From: Cédric Le Goater
The LPC Controller on POWER9 is very similar to the one found on
POWER8 but accesses are now done via on MMIOs, without the XSCOM and
ECCB logic. The device tree is populated differently so we add a
specific POWER9 routine for the purpose.
SerIRQ routing is yet to be done.
From: Cédric Le Goater
The PSI bridge on POWER9 is very similar to POWER8. The BAR is still
set through XSCOM but the controls are now entirely done with MMIOs.
More interrupts are defined and the interrupt controller interface has
changed to XIVE. The POWER9 model is a first example of the usage
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20190309214255.9952-3-f4...@amsat.org>
Signed-off-by: David Gibson
---
target/ppc/translate/vsx-impl.inc.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/ppc/translate/vsx-i
From: Cédric Le Goater
To improve OPAL/skiboot support. We don't need to strictly model these
XSCOM accesses.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-14-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv_xscom.c | 33 +++--
1 file ch
Hi,
Please review the following patch-set which consist of cosmetics fixes to
device's user interface (traces, error_report and monitor) and some bug
fixes.
Thanks Markus, Eric, Marcel and David for your review
Review is needed for patch #4 - "hw/pvrdma: Collect debugging statistics"
v0 -> v1:
From: Cédric Le Goater
Provide a new class attribute to define XSCOM operations per CPU
family and add a couple of XSCOM addresses controlling the power
management states of the core on POWER9.
Signed-off-by: Cédric Le Goater
Message-Id: <20190307223548.20516-11-...@kaod.org>
Signed-off-by: Dav
From: Cédric Le Goater
The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.
Provide a basic Quad model to fake t
To make code more readable move handling of protected list to a
rdma_utils
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/rdma_backend.c | 20 +--
hw/rdma/rdma_backend_defs.h | 8 ++--
hw/rdma/rdma_utils.c| 39 +
Add counters to enable enhance debugging
Signed-off-by: Yuval Shaia
---
hw/rdma/rdma_backend.c| 70 +--
hw/rdma/rdma_rm.c | 7
hw/rdma/rdma_rm_defs.h| 27 ++-
hw/rdma/vmw/pvrdma.h | 10 ++
hw/rdma/vmw/pvrdma_cmd.c |
The function rdma_poll_cq is called from two contexts - completion
handler thread which sense new completion on backend channel and
explicitly as result of guest issuing poll_cq command.
Add lock to protect against concurrent executions.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
The function's argument rdma_dev_res is not needed as it is stored in
the backend_dev object at init.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/rdma_backend.c | 13 ++---
hw/rdma/rdma_backend.h | 1 -
hw/rdma/vmw/pvrdma_qp_ops.c | 3 +--
3 files ch
Utilize error_report for all pr_err calls and some pr_dbg that are
considered as errors.
For the remaining pr_dbg calls, the important ones were replaced by
trace points while other deleted.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/rdma_backend.c| 336 +++
When QP is destroyed the backend QP is destroyed as well. This ensures
we clean all received buffer we posted to it.
However, a contexts of these buffers are still remain in the device.
Fix it by maintaining a list of buffer's context and free them when QP
is destroyed.
Signed-off-by: Yuval Shaia
This hook was installed to close the device when VM is going down.
After the device is closed there is no need to be informed on VM
shutdown.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/vmw/pvrdma_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/rdma/vmw/
Allow interrogating device internals through HMP interface.
The exposed indicators can be used for troubleshooting by developers or
sysadmin.
There is no need to expose these attributes to a management system (e.x.
libvirt) because (1) most of them are not "device-management' related
info and (2) t
This hook is not called and was implemented by mistake.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/vmw/pvrdma_main.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c
index 01bb6e6b17..84df4294eb 100644
--- a
When device is going down free all saved MAD buffers.
Signed-off-by: Yuval Shaia
Reviewed-by: Marcel Apfelbaum
---
hw/rdma/rdma_backend.c| 34 +-
hw/rdma/vmw/pvrdma_main.c | 2 ++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/hw/rdma/rdma_ba
/60] ppc-for-4.0 queue 20190310
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT
Thanks Emilio,
I found the ssh connection is very slow and the submodule wasn’t checked out
completely.
I uses the https connection and it works as normal.
Thanks,
Li Qiang
发件人: Emilio G. Cota
发送时间: 2019年3月10日 1:38
收件人: Li Qiang
抄送: qemu-devel@nongnu.org
主题: Re: 'make check' error
On Sat, Mar 0
Daniel P. Berrangé writes:
> On Mon, Mar 04, 2019 at 12:45:14PM +0100, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>>
>> > On Mon, Mar 04, 2019 at 08:13:53AM +0100, Markus Armbruster wrote:
>> >> If we deprecate outdated NUMA configurations now, we can start rejecting
>> >> them with
Daniel P. Berrangé writes:
> On Wed, Mar 06, 2019 at 08:03:48PM +0100, Igor Mammedov wrote:
>> On Mon, 4 Mar 2019 16:35:16 +
>> Daniel P. Berrangé wrote:
>>
>> > On Mon, Mar 04, 2019 at 05:20:13PM +0100, Michal Privoznik wrote:
>> > > We couldn't have done that. How we would migrate from ol
Just faced this problem when trying to test vfio-pci using upstream:
qemu-system-ppc64: -device vfio-pci,host=0035:03:00.0,id=hostdev8:
'vfio-pci' is not a valid device model name
This patch fixed it.
Tested-by: Daniel Henrique Barboza
On 3/8/19 2:36 PM, Paolo Bonzini wrote:
CONFIG_VFIO_
On 09/03/2019 19:19, Philippe Mathieu-Daudé wrote:
> Since commit 578f3c7b0835 ("arm: add fw_cfg to "virt" board",
> 2014-12-22), the machvirt_init() unconditionally creates the
> fw_cfg object. Later, commit c30e15658b1b ("smbios: implement
> smbios support for mach-virt", 2015-09-07) added a sup
On 09/03/2019 19:19, Philippe Mathieu-Daudé wrote:
> The load/store API eases code review.
>
> Reviewed-by: Laszlo Ersek
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/nvram/fw_cfg.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/f
Hi,
Okay, as you wish. My code works either way and on real hardware as
well, because I acknowledge the periodic IRQ as soon as possible, so
good for me.
Sign-off-by: Zoltán Baldaszti
Subject: [PATCH] Added periodic IRQ support for bcm2836_control local timer
diff --git a/hw/intc/bcm2836_control
When running ssh over IPv6 with linux-user I faced this warning:
Unsupported setsockopt level=41 optname=67
setsockopt IPV6_TCLASS 32: Protocol not available:
This patch adds code to the linux-user emulatation for setting and
retrieving of a few missing IPV6 options, including IPV6_TCLASS.
Sign
Fixes: 2dbfadf
Spotted by ASAN when 'make check'.
Signed-off-by: Li Qiang
---
tests/test-bdrv-graph-mod.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/test-bdrv-graph-mod.c b/tests/test-bdrv-graph-mod.c
index 458dfa6661..8bf0fe735d 100644
--- a/tests/test-bdrv-graph-mod.c
+++ b/test
Hi Laszlo,
On 3/9/19 1:48 AM, Laszlo Ersek wrote:
> Add the "efi" target to "Makefile".
>
> Introduce "Makefile.edk2" for building and cleaning the firmware images
> and varstore templates.
>
> Collect the common bits from the recipes in the helper script
> "edk2-build.sh".
>
> Signed-off-by: L
On Fri, 8 Mar 2019 at 17:41, Eric Blake wrote:
>
> The following changes since commit c557a8c7b755d8c153fc0f5be00688228be96e76:
>
> Merge remote-tracking branch
> 'remotes/dgilbert/tags/pull-migration-20190306a' into staging (2019-03-06
> 14:50:33 +)
>
> are available in the Git repository
Hi Jason,
What's the status of this patch? I don't see it in upstream.
Thanks,
Li Qiang
Jason Wang 于2018年11月22日周四 上午10:22写道：
>
> On 2018/11/22 上午1:39, Michael S. Tsirkin wrote:
> > On Wed, Nov 21, 2018 at 11:30:41AM -0600, Eric Blake wrote:
> >> On 11/21/18 6:23 AM, Michael S. Tsirkin wrote:
>
On 3/10/19 4:56 AM, Michael S. Tsirkin wrote:
> On Sat, Mar 09, 2019 at 01:48:16AM +0100, Laszlo Ersek wrote:
>> Repo: https://github.com/lersek/qemu.git
>> Branch: edk2_build
>>
>> This series advances the roms/edk2 submodule to the "edk2-stable201903"
>> release, and builds and captures platfor
Hi Paolo,
What's the status of this patch? I don't see it in upstream.
Thanks,
Li Qiang
At 2019-01-08 07:41:09, "Paolo Bonzini" wrote:
>On 02/01/19 08:41, Li Qiang wrote:
>> Commit 376692b9dc6(cpus: protect work list with work_mutex)
>> initialize a work_mutex in cpu_common_initfn, however fo
On Sat, 9 Mar 2019 at 07:50, Paolo Bonzini wrote:
>
> The following changes since commit 62cfabb52210139843e26c95434356f73a0631b9:
>
> Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190307' into
> staging (2019-03-08 15:17:01 +)
>
> are available in the git repository at:
>
>
>
Spotted by ASAN when 'make check'.
Signed-off-by: Li Qiang
---
tests/test-announce-self.c | 20 ++--
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/tests/test-announce-self.c b/tests/test-announce-self.c
index 1644d34a3f..3f370d8bf5 100644
--- a/tests/test-announc
Hi Bin,
On Sun, 2019-03-10 at 09:07 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Feb 11, 2019 at 6:13 AM Lukas Auer
> wrote:
> > Re-add the previous compatible string "riscv-virtio-soc" to the soc
> > device tree node to allow U-Boot and Linux to bind machine-specific
> > drivers to it. The cu
This adds DDC support to ati-vga and connects i2c-ddc to provide EDID
info that is read by guests to find available screen modes. Not sure
if this is 100% correct yet but at least MorphOS is happy with it and
starts in a high resolution mode instead of 640x480 (although its
splash screen is still n
Compiling vt82c686.c fails without APM and ACPI_PM funtions. Add
dependency on these in Kconfig to fix this.
Signed-off-by: BALATON Zoltan
---
hw/isa/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 57e09a0cb8..e092da3fc3 100644
--- a/hw/isa/Kco
At least two machines, the PPC mac99 and MIPS fulong2e, have an ATI
gfx chip by default (Rage 128 Pro and M6/RV100 respectively) and
guests running on these and the PMON2000 firmware of the fulong2e
expect this to be available. Fortunately these are very similar chips
so they can be mostly emulated
Add (partial) emulation of the on-board GPU of the machine. This
allows the PMON2000 firmware to run and should also work with Linux
console but probably not with X yet.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar
Rebase on master to fix build with new Kconfig based stuff.
BALATON Zoltan (2):
hw/display: Add basic ATI VGA emulation
mips_fulong2e: Add on-board graphics chip
hw/display/Kconfig | 6 +
hw/display/Makefile.objs | 2 +
hw/display/ati.c | 865 +++
@Peter Luyou and me are working on try to pass the info about whether P
flag is enabled or not by enviroment var or auxval. While we have not
found the right method to do it from binfmt_misc.
In fact, currently qemu trys to process the O flag, and it cannot work at all.
When you install qemu-user-
Daniel P. Berrangé writes:
[...]
> As long term contributors we've built enough enough knowledge to
> QEMU to consider our build system attractive or even "simple",
The words that come to my mind aren't "attractive" or "simple", but
"impressively clever", "brittle", and "uh, can I hack on someth
Public bug reported:
After a host crash, the qcow2 image of the VM, stored on a remote NFS
share, has become inaccessible. Libvirt/QEMU reports that 'failed to get
"write" lock\nIs another process using the image
[/path/nfs/image.qcow2]?'. No process is accessing the image from either
host or the
Peter Maydell writes:
> On Thu, 7 Mar 2019 at 06:39, Thomas Huth wrote:
>> On 06/03/2019 19.12, Paolo Bonzini wrote:
>> > lately I have been thinking of converting the QEMU build system to
>> > Meson. Meson is a relatively new build system that can replace
>> > Autotools or hand-written Makefil
On 3/10/19 12:34 PM, Li Qiang wrote:
> Fixes: 2dbfadf
^ Please keep tags together (with Signed-off-by, ...)
> Spotted by ASAN when 'make check'.
I'm not native English speaker but I'd say:
Spotted by ASAN [with] 'make check'.
or
Spotted by ASAN [while running] 'make check'.
Here goes:
"Fi
Hi Lukas,
On Sun, Mar 10, 2019 at 9:44 PM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Sun, 2019-03-10 at 09:07 +0800, Bin Meng wrote:
> > Hi Lukas,
> >
> > On Mon, Feb 11, 2019 at 6:13 AM Lukas Auer
> > wrote:
> > > Re-add the previous compatible string "riscv-virtio-soc" to the soc
> > > device tree
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