Patchew URL: https://patchew.org/QEMU/20190310082703.1245-1-da...@gibson.dropbear.id.au/
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20190310082703.1245-1-da...@gibson.dropbear.id.au Subject: [Qemu-devel] [PULL 00/60] ppc-for-4.0 queue 20190310 === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20190310082703.1245-1-da...@gibson.dropbear.id.au -> patchew/20190310082703.1245-1-da...@gibson.dropbear.id.au Switched to a new branch 'test' a13e9857de spapr: Use CamelCase properly 9b2d3e81df target/ppc: Optimize x[sv]xsigdp using deposit_i64() 1a63e5d488 target/ppc: Optimize xviexpdp() using deposit_i64() 82f058a774 target/ppc: add HV support for POWER9 c85ade25f0 ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9 e39b190d65 ppc/pnv: add more dummy XSCOM addresses 2aaa98b799 ppc/pnv: activate XSCOM tests for POWER9 40a779400e ppc/pnv: POWER9 XSCOM quad support bf6b37e0e3 ppc/pnv: extend XSCOM core support for POWER9 a16eb6280a ppc/pnv: add a OCC model for POWER9 177a01f268 ppc/pnv: add a OCC model class 0032552915 ppc/pnv: add SerIRQ routing registers cad3544b00 ppc/pnv: add a LPC Controller model for POWER9 c8a3537791 ppc/pnv: add a 'dt_isa_nodename' to the chip 8a24b7e984 ppc/pnv: add a LPC Controller class model b565618566 ppc/pnv: lpc: fix OPB address ranges b3753bf4d5 ppc/pnv: add a PSI bridge model for POWER9 0f805a7337 ppc/pnv: add a PSI bridge class model dc90b53163 mac_newworld: use node name instead of alias name for hd device in FWPathProvider b40751980c mac_oldworld: use node name instead of alias name for hd device in FWPathProvider 09a2890670 target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() 6502f1d34c target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order c8ccee4ae4 target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64() 009069ca82 target/ppc: introduce avr_full_offset() function 42276547b8 target/ppc: move Vsr* macros from internal.h to cpu.h 9b303bf2fe target/ppc: introduce single vsrl_offset() function 7d115a7cca target/ppc: introduce single fpr_offset() function bc857d3423 spapr_iommu: Do not replay mappings from just created DMA window 318207457b ppc/pnv: psi: add a reset handler d8c41355f7 ppc/pnv: psi: add a PSIHB_REG macro 0afa36e08f ppc/pnv: fix logging primitives using Ox 71115811ab ppc/xive: activate HV support 6a4dfae59e ppc/pnv: introduce a new pic_print_info() operation to the chip model d775142ddd ppc/pnv: introduce a new dt_populate() operation to the chip model 087e79ef3a ppc/pnv: add a XIVE interrupt controller model for POWER9 560306e92f ppc/pnv: change the CPU machine_data presenter type to Object * 61f1c7c909 ppc/pnv: export the xive_router_notify() routine 7de67358c5 ppc/xive: export the TIMA memory accessors bb2f939bf2 ppc: externalize ppc_get_vcpu_by_pir() 371cc21427 ppc/xive: hardwire the Physical CAM line of the thread context 2bd3f311b6 PPC: E500: Add FSL I2C controller and integrate RTC with it cd8d1d103b target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling 331fb825f9 spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit) 4d0a5b8bac target/ppc/spapr: Clear partition table entry when allocating hash table 459399789c PPC: E500: Update u-boot to v2019.01 d95c3a89e7 target/ppc: Refactor kvm_handle_debug 4e0adda559 target/ppc: Move handling of hardware breakpoints to a separate function f914b4a55d target/ppc: Move exception vector offset computation into a function dec20748cf target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type 2a2020fd52 target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg abe6251060 target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST efcc41a1f0 target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS d27181434a target/ppc/spapr: Enable the large decrementer for pseries-4.0 e3509a4217 target/ppc: Implement large decrementer support for KVM 85592739a6 target/ppc: Implement large decrementer support for TCG ed7935af70 target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER 9bcb00db74 Revert "spapr: support memory unplug for qtest" 16684c3584 spapr: Simulate CAS for qtest 31faed9bf2 vfio/spapr: Rename local systempagesize variable 29eef1ef4b vfio/spapr: Fix indirect levels calculation === OUTPUT BEGIN === 1/60 Checking commit 29eef1ef4b33 (vfio/spapr: Fix indirect levels calculation) 2/60 Checking commit 31faed9bf208 (vfio/spapr: Rename local systempagesize variable) 3/60 Checking commit 16684c358405 (spapr: Simulate CAS for qtest) 4/60 Checking commit 9bcb00db7471 (Revert "spapr: support memory unplug for qtest") 5/60 Checking commit ed7935af70ab (target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER) WARNING: line over 80 characters #47: FILE: hw/ppc/spapr_caps.c:397: + error_setg(errp, "No large decrementer support, try cap-large-decr=off"); total: 0 errors, 1 warnings, 67 lines checked Patch 5/60 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 6/60 Checking commit 85592739a601 (target/ppc: Implement large decrementer support for TCG) ERROR: space prohibited between function name and open parenthesis '(' #65: FILE: hw/ppc/ppc.c:765: +target_ulong cpu_ppc_load_decr (CPUPPCState *env) ERROR: braces {} are necessary for all arms of this statement #81: FILE: hw/ppc/ppc.c:780: + if (env->spr[SPR_LPCR] & LPCR_LD) [...] ERROR: space prohibited between function name and open parenthesis '(' #87: FILE: hw/ppc/ppc.c:785: +target_ulong cpu_ppc_load_hdecr (CPUPPCState *env) ERROR: braces {} are necessary for all arms of this statement #101: FILE: hw/ppc/ppc.c:798: + if (pcc->lrg_decr_bits > 32) [...] ERROR: braces {} are necessary for all arms of this statement #124: FILE: hw/ppc/ppc.c:865: + if (negative) [...] ERROR: space prohibited between function name and open parenthesis '(' #169: FILE: hw/ppc/ppc.c:921: +void cpu_ppc_store_decr (CPUPPCState *env, target_ulong value) ERROR: braces {} are necessary for all arms of this statement #174: FILE: hw/ppc/ppc.c:926: + if (env->spr[SPR_LPCR] & LPCR_LD) [...] ERROR: space prohibited between function name and open parenthesis '(' #202: FILE: hw/ppc/ppc.c:951: +void cpu_ppc_store_hdecr (CPUPPCState *env, target_ulong value) ERROR: braces {} are necessary for all arms of this statement #254: FILE: hw/ppc/spapr_caps.c:398: + if (!val) [...] ERROR: braces {} are necessary for all arms of this statement #276: FILE: hw/ppc/spapr_caps.c:420: + if (val) [...] + else [...] ERROR: space prohibited between function name and open parenthesis '(' #316: FILE: target/ppc/cpu.h:1324: +target_ulong cpu_ppc_load_decr (CPUPPCState *env); ERROR: space prohibited between function name and open parenthesis '(' #317: FILE: target/ppc/cpu.h:1325: +void cpu_ppc_store_decr (CPUPPCState *env, target_ulong value); ERROR: space prohibited between function name and open parenthesis '(' #318: FILE: target/ppc/cpu.h:1326: +target_ulong cpu_ppc_load_hdecr (CPUPPCState *env); ERROR: space prohibited between function name and open parenthesis '(' #319: FILE: target/ppc/cpu.h:1327: +void cpu_ppc_store_hdecr (CPUPPCState *env, target_ulong value); total: 14 errors, 0 warnings, 299 lines checked Patch 6/60 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 7/60 Checking commit e3509a42179c (target/ppc: Implement large decrementer support for KVM) WARNING: line over 80 characters #46: FILE: hw/ppc/spapr_caps.c:413: + error_setg(errp, "No large decrementer support, try cap-large-decr=off"); ERROR: braces {} are necessary for all arms of this statement #60: FILE: hw/ppc/spapr_caps.c:430: + if (kvmppc_enable_cap_large_decr(cpu, val)) [...] WARNING: line over 80 characters #61: FILE: hw/ppc/spapr_caps.c:431: + error_setg(errp, "No large decrementer support, try cap-large-decr=off"); ERROR: braces {} are necessary for all arms of this statement #103: FILE: target/ppc/kvm.c:1937: + if (nr_bits > 0) [...] ERROR: braces {} are necessary for all arms of this statement #128: FILE: target/ppc/kvm.c:2470: + if (enable) [...] + else [...] ERROR: braces {} are necessary for all arms of this statement #135: FILE: target/ppc/kvm.c:2477: + if (!!(lpcr & LPCR_LD) != !!enable) [...] total: 4 errors, 2 warnings, 129 lines checked Patch 7/60 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 8/60 Checking commit d27181434a16 (target/ppc/spapr: Enable the large decrementer for pseries-4.0) 9/60 Checking commit efcc41a1f035 (target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS) 10/60 Checking commit abe6251060f1 (target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST) WARNING: line over 80 characters #105: FILE: hw/ppc/spapr_hcall.c:1696: + uint8_t count_cache_flush_assist = spapr_get_cap(spapr, SPAPR_CAP_CCF_ASSIST); ERROR: braces {} are necessary for all arms of this statement #113: FILE: hw/ppc/spapr_hcall.c:1737: + if (count_cache_flush_assist) [...] ERROR: braces {} are necessary for all arms of this statement #160: FILE: target/ppc/kvm.c:2412: + if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) [...] WARNING: line over 80 characters #172: FILE: target/ppc/kvm.c:2439: + cap_ppc_count_cache_flush_assist = parse_cap_ppc_count_cache_flush_assist(c); total: 2 errors, 2 warnings, 146 lines checked Patch 10/60 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 11/60 Checking commit 2a2020fd5275 (target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg) ERROR: braces {} are necessary for all arms of this statement #98: FILE: hw/ppc/spapr_caps.c:315: + if (local_err != NULL) [...] total: 1 errors, 0 warnings, 75 lines checked Patch 11/60 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 12/60 Checking commit dec20748cfa8 (target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type) 13/60 Checking commit f914b4a55d6e (target/ppc: Move exception vector offset computation into a function) 14/60 Checking commit 4e0adda559b7 (target/ppc: Move handling of hardware breakpoints to a separate function) 15/60 Checking commit d95c3a89e706 (target/ppc: Refactor kvm_handle_debug) 16/60 Checking commit 459399789c9e (PPC: E500: Update u-boot to v2019.01) 17/60 Checking commit 4d0a5b8bacd4 (target/ppc/spapr: Clear partition table entry when allocating hash table) 18/60 Checking commit 331fb825f9cb (spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit)) 19/60 Checking commit cd8d1d103b55 (target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling) 20/60 Checking commit 2bd3f311b63d (PPC: E500: Add FSL I2C controller and integrate RTC with it) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #64: new file mode 100644 total: 0 errors, 1 warnings, 469 lines checked Patch 20/60 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/60 Checking commit 371cc2142706 (ppc/xive: hardwire the Physical CAM line of the thread context) 22/60 Checking commit bb2f939bf2dc (ppc: externalize ppc_get_vcpu_by_pir()) 23/60 Checking commit 7de67358c5b2 (ppc/xive: export the TIMA memory accessors) 24/60 Checking commit 61f1c7c9093c (ppc/pnv: export the xive_router_notify() routine) 25/60 Checking commit 560306e92fdd (ppc/pnv: change the CPU machine_data presenter type to Object *) 26/60 Checking commit 087e79ef3a01 (ppc/pnv: add a XIVE interrupt controller model for POWER9) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #62: new file mode 100644 total: 0 errors, 1 warnings, 2215 lines checked Patch 26/60 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 27/60 Checking commit d775142ddd2f (ppc/pnv: introduce a new dt_populate() operation to the chip model) 28/60 Checking commit 6a4dfae59e4e (ppc/pnv: introduce a new pic_print_info() operation to the chip model) 29/60 Checking commit 71115811ab4b (ppc/xive: activate HV support) 30/60 Checking commit 0afa36e08fc0 (ppc/pnv: fix logging primitives using Ox) 31/60 Checking commit d8c41355f7d6 (ppc/pnv: psi: add a PSIHB_REG macro) 32/60 Checking commit 318207457bf4 (ppc/pnv: psi: add a reset handler) 33/60 Checking commit bc857d342374 (spapr_iommu: Do not replay mappings from just created DMA window) 34/60 Checking commit 7d115a7cca15 (target/ppc: introduce single fpr_offset() function) 35/60 Checking commit 9b303bf2fee1 (target/ppc: introduce single vsrl_offset() function) 36/60 Checking commit 42276547b8da (target/ppc: move Vsr* macros from internal.h to cpu.h) 37/60 Checking commit 009069ca82e9 (target/ppc: introduce avr_full_offset() function) 38/60 Checking commit c8ccee4ae4af (target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64()) 39/60 Checking commit 6502f1d34c0d (target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order) 40/60 Checking commit 09a28906704f (target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}()) 41/60 Checking commit b40751980c2a (mac_oldworld: use node name instead of alias name for hd device in FWPathProvider) 42/60 Checking commit dc90b5316341 (mac_newworld: use node name instead of alias name for hd device in FWPathProvider) 43/60 Checking commit 0f805a733782 (ppc/pnv: add a PSI bridge class model) 44/60 Checking commit b3753bf4d584 (ppc/pnv: add a PSI bridge model for POWER9) 45/60 Checking commit b56561856691 (ppc/pnv: lpc: fix OPB address ranges) 46/60 Checking commit 8a24b7e984cc (ppc/pnv: add a LPC Controller class model) 47/60 Checking commit c8a35377919a (ppc/pnv: add a 'dt_isa_nodename' to the chip) 48/60 Checking commit cad3544b002f (ppc/pnv: add a LPC Controller model for POWER9) 49/60 Checking commit 003255291514 (ppc/pnv: add SerIRQ routing registers) 50/60 Checking commit 177a01f268e2 (ppc/pnv: add a OCC model class) 51/60 Checking commit a16eb6280ab9 (ppc/pnv: add a OCC model for POWER9) 52/60 Checking commit bf6b37e0e3ac (ppc/pnv: extend XSCOM core support for POWER9) 53/60 Checking commit 40a779400ee9 (ppc/pnv: POWER9 XSCOM quad support) 54/60 Checking commit 2aaa98b799e6 (ppc/pnv: activate XSCOM tests for POWER9) 55/60 Checking commit e39b190d6527 (ppc/pnv: add more dummy XSCOM addresses) 56/60 Checking commit c85ade25f000 (ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9) 57/60 Checking commit 82f058a7749c (target/ppc: add HV support for POWER9) 58/60 Checking commit 1a63e5d48857 (target/ppc: Optimize xviexpdp() using deposit_i64()) 59/60 Checking commit 9b2d3e81dfc8 (target/ppc: Optimize x[sv]xsigdp using deposit_i64()) 60/60 Checking commit a13e9857de40 (spapr: Use CamelCase properly) WARNING: Block comments use a leading /* on a separate line #1577: FILE: hw/ppc/spapr.c:1945: + /* Prior to the introduction of SpaprOptionVector, we had two option total: 0 errors, 1 warnings, 6909 lines checked Patch 60/60 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190310082703.1245-1-da...@gibson.dropbear.id.au/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-de...@redhat.com
