MSI is the default and LSI specific code is guarded by the
xive_source_irq_is_lsi() helper. The xive_source_irq_set()
helper is a nop for MSIs.
Simplify the code by turning xive_source_irq_set() into
xive_source_irq_set_lsi() and only call it for LSIs. The
call to xive_source_irq_set(false) in spa
On 2/12/19 1:12 PM, Eric Blake wrote:
> On 2/11/19 7:02 PM, John Snow wrote:
>> The current internal meanings of "locked", "user_locked",
>> "qmp_locked", "frozen", "enabled", and "disabled" are all
>> a little muddled.
>>
>> Deprecate the @status field in favor of two new booleans
>> that carry
To support PHB hotplug we need to clean up lingering references,
memory, child properties, etc. prior to the PHB object being
finalized. Generally this will be called as a result of calling
object_unparent() on the PHB object, which in turn would normally
be called as the result of an unplug() oper
On 12.02.19 19:01, Richard Henderson wrote:
> On 2/12/19 3:02 AM, David Hildenbrand wrote:
>> +static bool s390_tdc32(CPUS390XState *env, float32 f1, uint16_t dc_mask)
>> +{
>> +const bool neg = float32_is_neg(f1);
>> +const bool zero = float32_is_zero(f1);
>> +const bool no
From: Michael Roth
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
---
hw/ppc/spapr.c | 13 +
hw/ppc/spapr_drc.c | 17 +
include/hw/ppc/spapr.h |1 +
include/hw/ppc/spapr_drc.h |8
4 files
From: Michael Roth
Extend the existing EPOW event format we use for PCI
devices to emit PHB plug/unplug events.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
---
hw/ppc/spapr_events.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/ppc/spapr_even
From: Michael Roth
Certain devices types, like memory/CPU, are now being handled using a
hotplug interface provided by a top-level MachineClass. Hotpluggable
host bridges are another such device where it makes sense to use a
machine-level hotplug handler. However, unlike those devices,
host-bridg
From: Michael Roth
PHB hotplug re-uses PHB device tree generation code and passes
it to a guest via RTAS. Doing this requires knowledge of where
exactly in the device tree the node describing the PHB begins.
Provide this via a new optional pointer that can be used to
store the PHB node's start o
This will be used by PHB hotplug in order to create the "interrupt-map"
property of the PHB node.
Reviewed-by: Cédric Le Goater
Signed-off-by: Greg Kurz
---
v4: - return phandle via a pointer
---
hw/ppc/spapr_irq.c | 26 ++
include/hw/ppc/spapr_irq.h |2 ++
On Tue, Feb 12, 2019 at 03:00:55PM +0800, Jason Wang wrote:
>
> On 2019/2/12 下午2:48, Jason Wang wrote:
> >
> > On 2019/2/11 下午9:40, Anton Kuchin wrote:
> > > As far as I can see currently IOThread offloading is used only for
> > > block devices and all others are emulated by main thread.
> > >
>
From: Michael Roth
This is needed to denote a boot-time PHB as being hot-pluggable.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
---
hw/ppc/spapr_pci.c |9 +
1 file changed, 9 insertions(+)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
in
From: Michael Roth
The 'dr_phb_enabled' field of that class can be set as part of
machine-specific init code. It will be used to conditionally
enable creation of DRC objects and device-tree description to
facilitate hotplug of PHBs.
Since we can't migrate this state to older machine types,
defau
This will be needed by PHB hotplug in order to access the "phandle"
property of the interrupt controller node.
Reviewed-by: Cédric Le Goater
Signed-off-by: Greg Kurz
---
v4: - folded some changes from patches 15, 16 and 17 of v3
- dropped useless helpers
---
hw/intc/spapr_xive.c|
On Tue, 12 Feb 2019 at 18:25, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 2/12/19 7:19 PM, Peter Maydell wrote:
> > The code for handling the NVIC SHPR1 register intends to permit
> > byte and halfword accesses (as the architecture requires). However
> > the 'case' line for it only lists th
The current logic is to provide the FDT fragment when attaching a device
to a DRC. This works perfectly fine for our current hotplug support, but
soon we will add support for PHB hotplug which has some constraints, that
CPU, PCI and LMB devices don't seem to have.
The first constraint is that the
On 2/12/19 1:26 PM, Eric Blake wrote:
> On 2/11/19 7:02 PM, John Snow wrote:
>> "Frozen" was a good description a long time ago, but it isn't adequate now.
>> Rename the frozen predicate to has_successor to make the semantics of the
>> predicate more clear to outside callers.
>>
>> In the proces
On Tue, 12 Feb 2019 23:19:49 +0800
Changpeng Liu wrote:
> Commit caa1ee43 "vhost-user-blk: add discard/write zeroes features
> support" added fields to struct virtio_blk_config. This changes
> the size of the config space and breaks migration from QEMU 3.1
> and older:
>
> qemu-system-ppc64: get
Hotplugging PHBs is a machine-level operation, but PHBs reside on the
main system bus, so we register spapr machine as the handler for the
main system bus.
Provide the usual pre-plug, plug and unplug-request handlers.
Move the checking of the PHB index to the pre-plug handler. It is okay
to do th
On 2/11/19 7:02 PM, John Snow wrote:
> "Frozen" was a good description a long time ago, but it isn't adequate now.
> Rename the frozen predicate to has_successor to make the semantics of the
> predicate more clear to outside callers.
>
> In the process, remove some calls to frozen() that no longer
On Wed, Feb 06, 2019 at 11:30:13AM +0100, Igor Mammedov wrote:
> On Tue, 5 Feb 2019 16:19:50 +0100
> Laszlo Ersek wrote:
>
> > On 02/05/19 16:07, Igor Mammedov wrote:
> > > On Mon, 4 Feb 2019 17:03:20 +0100
> > > Laszlo Ersek wrote:
> > >
> > > Am I to greedy to ask for prebuilt AVMF image in
On 2/12/19 3:02 AM, David Hildenbrand wrote:
> We can directly work on the uint64_t value, no need for a temporary
> uint32_t value.
>
> Also cleanup and shorten the comments.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/fpu_helper.c | 22 --
> 1 file changed, 1
On 2/12/19 3:03 AM, David Hildenbrand wrote:
> The trap is triggered based on priority of the enabled signaling flags.
> Only overflow and underflow allow a concurrent inexact exception.
>
> z14 PoP, 9-33, Figure 9-21
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/fpu_helper.c | 13 +
On 2/12/19 1:58 PM, Eric Blake wrote:
> On 2/11/19 7:02 PM, John Snow wrote:
>> Currently, enabled means something like "the status of the bitmap
>> is ACTIVE." After this patch, it should mean exclusively: "This
>> bitmap is recording guest writes, and is allowed to do so."
>>
>> In many places
On 2/11/19 7:02 PM, John Snow wrote:
> Instead of implying a locked status, make it explicit.
> Now, bitmaps in use by migration, NBD or backup operations
> are all treated the same way with the same code paths.
> ---
> block/dirty-bitmap.c | 9 +
> 1 file changed, 5 insertions(+), 4 delet
On 2/12/19 3:03 AM, David Hildenbrand wrote:
> We already forward the 3 bits correctly in the translation functions. We
> also have to handle them properly and check for specification
> exceptions.
>
> Setting an invalid rounding mode (BFP only, all DFP rounding modes)
> results in a specification
On 2/11/19 7:02 PM, John Snow wrote:
> Currently, enabled means something like "the status of the bitmap
> is ACTIVE." After this patch, it should mean exclusively: "This
> bitmap is recording guest writes, and is allowed to do so."
>
> In many places, this is how this predicate was already used.
On 2/11/19 7:02 PM, John Snow wrote:
> These mean the same thing now. Unify them and rename the merged call
> bdrv_dirty_bitmap_busy to indicate semantically what we are describing,
> as well as help disambiguate from the various _locked and _unlocked
> versions of bitmap helpers that refer to mute
On 12.02.19 20:07, Richard Henderson wrote:
> On 2/12/19 3:03 AM, David Hildenbrand wrote:
>> We already forward the 3 bits correctly in the translation functions. We
>> also have to handle them properly and check for specification
>> exceptions.
>>
>> Setting an invalid rounding mode (BFP only, al
On 2/12/19 2:27 PM, Eric Blake wrote:
> On 2/11/19 7:02 PM, John Snow wrote:
>> These mean the same thing now. Unify them and rename the merged call
>> bdrv_dirty_bitmap_busy to indicate semantically what we are describing,
>> as well as help disambiguate from the various _locked and _unlocked
>
On 12.02.19 02:16, Collin Walling wrote:
> The extended PTFF features (qsie, qtoue, stoe, stoue) are dependent
> on the multiple-epoch facility (mepoch). Let's print a warning if these
> features are enabled without mepoch.
>
> While we're at it, let's move the FEAT_GROUP_INIT for mepochptff down
Marc-André Lureau, le mar. 12 févr. 2019 17:09:51 +0100, a ecrit:
> QEMU wraps the socket functions in os-win32.h, but in commit
> a9d8b3ec4385793815d71217857304, the header inclusion was dropped,
> breaking slirp on Windows. Fix the regression by wrapping all the
> socket functions.
Applied to my
This change adds the possibility to write acceptance tests with multi
virtual machine support. It's done keeping the virtual machines objects
stored in a test attribute (dictionary). This dictionary shouldn't be
accessed directly but through the new method added `get_vm`. This new
method accept a l
This is the third attempt to add the multi vm capability to base class
of acceptance tests.
The difference from first version is that in this current version a
simple migration test was added (done by Cleber) so the new code that is
being added is properly used and we're not adding "new dead code"
This change adds the simplest possible migration test. Beyond the test
purpose itself it's also useful to exercise the multi virtual machines
capabilities from base avocado qemu test class.
Signed-off-by: Cleber Rosa
Signed-off-by: Caio Carrara
---
tests/acceptance/migration.py | 53 +++
On 2/6/19 11:02 AM, John Snow wrote:
> When bitmaps are persistent, they may incur a disk read or write when bitmaps
> are added or removed. For configurations like virtio-dataplane, failing to
> acquire this lock will abort QEMU when disk IO occurs.
>
> We used to acquire aio_context as part of t
From: Aleksandar Markovic
Add a header that contains test utilities. For now, it contains
only a function for checking and printing test results for bit
counting and similar MSA instructions.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/test_utils.h | 84 ++
On 2/12/19 2:36 PM, Eric Blake wrote:
> On 2/6/19 11:02 AM, John Snow wrote:
>> When bitmaps are persistent, they may incur a disk read or write when bitmaps
>> are added or removed. For configurations like virtio-dataplane, failing to
>> acquire this lock will abort QEMU when disk IO occurs.
>>
From: Aleksandar Markovic
This series begins to add unit tests (aka tcg tests) for MIPS'
MSA ASE. More tests and related test infrastructure will be added
in subsequent version of this series.
There are several checkpatch warnings that are all false positives
for given circumstances.
Aleksandar
From: Aleksandar Markovic
Remove a file that was added long time ago by mistake.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/mips64-dspr2/.directory | 2 --
1 file changed, 2 deletions(-)
delete mode 100644 tests/tcg/mips/mips64-dspr2/.directory
diff --git a/tests/tcg/mips/mips64-d
From: Aleksandar Markovic
The file tests/tcg/mips/include/test_inputs.h is planned to
contain various test inputs. For now, it contains 64 128-bit
pattern inputs (alternating groups od ones and zeroes) and
16 128-bit random inputs.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/
On Tue, 2019-02-12 at 10:14 -0700, Alex Williamson wrote:
> On Tue, 12 Feb 2019 17:25:46 +0100
> Knut Omang wrote:
>
> > On Tue, 2019-02-12 at 08:59 -0700, Alex Williamson wrote:
> > > On Tue, 12 Feb 2019 09:07:43 +0100
> > > Knut Omang wrote:
> > >
> > > > On Mon, 2019-02-11 at 16:09 -0700,
From: Aleksandar Markovic
Add a header that contains wrappers around MSA instructions assembler
invocations. For now, only bit counting instructions (NLOC, NLZC, and
PCNT; each in four data format flavors) are supported.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/wrappers_ms
From: Aleksandar Markovic
Add tests for MSA bit counting instructions. Each test consists of 80
test cases, so altogether there are 960 test cases.
Signed-off-by: Aleksandar Markovic
---
.../user/ase/msa/bit_counting/test_msa_nloc_b.c| 144 +
.../user/ase/msa/bit_counti
On 2/12/19 3:03 AM, David Hildenbrand wrote:
> Let's split handling of BFP/DFP rounding mode configuration. Also,
> let's not reuse the sfpc handler, use a separate handler so we can
> properly check for specification exceptions for SRNMB.
>
> Signed-off-by: David Hildenbrand
> ---
Reviewed-by:
On 2/12/19 1:53 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Remove a file that was added long time ago by mistake.
Might be worth mentioning commit d70080c4 (in 2012).
Is this the sort of file that is likely enough to be created during
typical workflows that it should be list
On 2/12/19 11:32 AM, David Hildenbrand wrote:
>> Yes, you want round_to_odd. I suppose that's not valid for float128 right
>> now?
>
> roundAndPackFloat64()
>
> as well as
>
> roundAndPackFloat128()
>
> support it.
>
> It's not implemented for round_canonical(), round_to_int(),
These two ar
On 2/12/19 3:03 AM, David Hildenbrand wrote:
> Some instructions allow to suppress IEEE inexact exceptions.
>
> z14 PoP, 9-23, "Suppression of Certain IEEE Exceptions"
> IEEE-inexact-exception control (XxC): Bit 1 of
> the M4 field is the XxC bit. If XxC is zero, recogni-
> tion of IEE
On 2/12/19 7:24 PM, Greg Kurz wrote:
> Only pseries machines, either recent ones started with ic-mode=xics
> or older ones using the legacy irq allocation scheme, need to set the
> @offset of the ICS to XICS_IRQ_BASE. Recent pseries started with
> ic-mode=dual set it to 0 and powernv machines set i
When bitmaps are persistent, they may incur a disk read or write when bitmaps
are added or removed. For configurations like virtio-dataplane, failing to
acquire this lock will abort QEMU when disk IO occurs.
We used to acquire aio_context as part of the bitmap lookup, so re-introduce
the lock for
On 12/02/2019 18:21, Philippe Mathieu-Daudé wrote:
> On 2/12/19 6:50 PM, Mark Cave-Ayland wrote:
>> On 12/02/2019 17:21, Philippe Mathieu-Daudé wrote:
>>
> If this delay is to prevent a bug which only happens in MacOS then that's
> the hack
> not the normal code path to run without th
On 2/12/19 3:03 AM, David Hildenbrand wrote:
> We want to reuse this in the context of vector instructions. So use
> better matching names and introduce s390_restore_bfp_rounding_mode().
>
> While at it, add proper newlines.
>
> Signed-off-by: David Hildenbrand
> ---
Reviewed-by: Richard Hender
On 2/12/19 7:24 PM, Greg Kurz wrote:
> The pseries machine only uses LSIs to support legacy PCI devices. Every
> PHB claims 4 LSIs at realize time. When using in-kernel XICS (or upcoming
> in-kernel XIVE), QEMU synchronizes the state of all irqs, including these
> LSIs, later on at machine reset.
>
> From: Eric Blake
> Sent: Tuesday, February 12, 2019 9:04 PM
> To: Aleksandar Markovic; qemu-devel@nongnu.org
> Cc: Aleksandar Rikalo; alex.ben...@linaro.org; Aleksandar Markovic;
> aurel...@aurel32.net
> Subject: Re: [Qemu-devel] [PATCH 1/5] tests/tcg: target/mips: Remove an
> unnecessary file
On 2/12/19 2:07 PM, John Snow wrote:
> When bitmaps are persistent, they may incur a disk read or write when bitmaps
> are added or removed. For configurations like virtio-dataplane, failing to
> acquire this lock will abort QEMU when disk IO occurs.
>
> We used to acquire aio_context as part of t
On 2/12/19 3:03 AM, David Hildenbrand wrote:
> -uint64_t HELPER(cegb)(CPUS390XState *env, int64_t v2, uint32_t m3)
> +uint64_t HELPER(cegb)(CPUS390XState *env, int64_t v2, uint32_t m)
> {
> -int old_mode = s390_swap_bfp_rounding_mode(env, m3);
> +int old_mode = s390_swap_bfp_rounding_mode(
On 2/12/19 3:03 AM, David Hildenbrand wrote:
> With the floating-point extension facility, LOAD ROUNDED has
> a rounding mode specification and the inexact-exception control (XxC).
>
> Handle them just like e.g. LOAD FP INTEGER.
>
> Signed-off-by: David Hildenbrand
> ---
Modulo the comments for
On 2/12/19 3:03 AM, David Hildenbrand wrote:
> PoP describes "Round to nearest with ties away from 0" as
> "The candidate nearest to the input value is selected. In case of a tie,
>the candidate selected is the one that is larger in magnitude."
>
> While float_round_ties_away is according to
On 2/12/19 9:25 AM, Cédric Le Goater wrote:
> On 2/12/19 5:34 AM, David Gibson wrote:
>> On Mon, Jan 28, 2019 at 10:46:09AM +0100, Cédric Le Goater wrote:
>>> The PowerNV machine can perform indirect loads and stores on the TIMA
>>> on behalf of another CPU. The PIR of the CPU is controlled by a se
cppcheck reports:
[hw/tpm/tpm_tis.c:113]: (warning) %d in format string (no. 2) requires 'int'
but the argument type is 'unsigned int'
Rather than just converting the format specifier to use '%u", the
tpm_tis_show_buffer() function is converted to use trace points and
the two debug callers use t
Assert that the address passed in results in a valid locality value.
Current callers pass a valid address so this is just a defensive check
to prevent a future caller passing an incorrect address or catch if the
MMIO address parameters were not all modified correctly. This is to
help static code a
In tpm_tis_mmio_write() if the requesting locality is seizing
access, any seizure by a lower locality is cancelled. However the
loop doing the seizure had an off-by-one error and the locality
immediately preceding the requesting locality was not being cleared.
This is fixed by adjusting the test i
On 2/12/19 3:48 PM, Liam Merwick wrote:
cppcheck reports:
[hw/tpm/tpm_tis.c:113]: (warning) %d in format string (no. 2) requires 'int'
but the argument type is 'unsigned int'
Rather than just converting the format specifier to use '%u", the
tpm_tis_show_buffer() function is converted to use tr
On 1/11/19 7:00 AM, Max Reitz wrote:
On 12.11.18 08:06, Marc Olson wrote:
Add a new rule type for blkdebug that instead of returning an error, can
inject latency to an IO.
Signed-off-by: Marc Olson
---
block/blkdebug.c | 79 +++---
docs/deve
Patches posted:
https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg02863.html
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net
Commit 3ebee3b191e defined assert() as g_assert(), but when we build
the VSS DLL component of QGA (to handle fsfreeze) we do not include
glib, which results in breakage when building with VSS support enabled.
Fix this by including glib. Since the VSS DLL is built statically,
this introduces an add
These fix a couple build regressions that have slipped in over that past
couple months and hopefully will help avoid future breakages.
qga/vss-win32/Makefile.objs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Tested-by: Helge Deller
Tested-by: Sven Schnelle
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 131 +--
target/hppa/insns.decode | 34 +-
2 files changed, 63 insertions(+), 102 deletions(-)
diff --git a/target/hppa/translate.c b/ta
On 2/12/19 3:16 PM, Eric Blake wrote:
> On 2/12/19 2:07 PM, John Snow wrote:
>> When bitmaps are persistent, they may incur a disk read or write when bitmaps
>> are added or removed. For configurations like virtio-dataplane, failing to
>> acquire this lock will abort QEMU when disk IO occurs.
>>
ommit 0b5e750bea635b167eb03d86c3d9a09bbd43bc06:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into
staging (2019-02-12 10:53:37 +)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-hppa-20190212
for you to fetc
Commit 7be41675f7c set -std=gnu99 for C code via QEMU_CFLAGS. Currently
we generate a "custom" QEMU_CXXFLAGS for VSS DLL C++ build by
filtering out some options from QEMU_CFLAGS and adding some others.
Since we don't filter out -std=gnu99 currently this breaks builds when
VSS support is enabled.
W
On 2/12/19 12:31 AM, Laurent Vivier wrote:
> I know nothing about ARM, but in kernel we have also a "v5t"
> (cpu_elf_name) and in QEMU we have a ARM_FEATURE_V4T which is set with
> ARM_FEATURE_V5. Is it related?
>From the ARM ARM (DDI 0406C, page A1-30):
The valid variants of ARMv4, ARMv5, and AR
Per the GDB remote protocol documentation
https://sourceware.org/gdb/current/onlinedocs/gdb/Packets.html#index-vKill-packet
the debug stub is expected to send a reply to the 'vKill' packet. At
least some versions of GDB crash if the gdb stub simply exits without
sending a reply. This patch fixe
spapr_possible_cpu_arch_ids() counts only cores, and so
the number of available CPUs is the number of vCPU divided
by smp_threads.
... -smp 4,maxcpus=8,cores=2,threads=2,sockets=2 -numa node,cpus=0,cpus=1 \
-numa node,cpus=3,cpus=4 \
Change the existing message to an error and exit.
This message was a warning and comes with the information
it will be removed in the future since May 10 2017
(ec78f8114bc4 "numa: use possible_cpus for not mapped CPUs check").
Update tests/numa-test to remove the incomplete CPU mapping test.
Sig
There are inconsistencies between the command line using
"-numa node,cpus=XX" and what is checked internally:
the XX is supposed to be a CPU number, but for SPAPR
it's taken as a core number, ignoring the threads.
(See the description message of PATCH 1 for more details)
This series fixes this pro
This will allow to use it in more functions in the future.
As we change the prototype to take directly CpuInstanceProperties
instead of CPUArchId, rename the function to cpu_props_to_string().
Signed-off-by: Laurent Vivier
---
hw/core/machine.c | 44 ++--
A core cannot be split between two nodes.
To check if a thread of the same core has already been assigned to a node,
this patch reverses the numa topology checking order and exits if the
topology is not valid.
Update test/numa-test accordingly.
Fixes: 722387e78daf ("spapr: get numa node mapping f
On 2/12/19 3:37 PM, John Snow wrote:
>
>
> On 2/12/19 3:16 PM, Eric Blake wrote:
>> On 2/12/19 2:07 PM, John Snow wrote:
>>> When bitmaps are persistent, they may incur a disk read or write when
>>> bitmaps
>>> are added or removed. For configurations like virtio-dataplane, failing to
>>> acquir
This is the 4th version of the patch set. Updated as per the review
from Alistair, it has the riscv_csrrw_debug function added, and
Reviewed-By lines added. Otherwise it is the same as the 3rd version.
Jim
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 43
gdb-xml/riscv-32bit-csr.xml | 250
gdb-xml/riscv-32bit-fpu.xml | 46
4 files changed, 340 insertions
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/target/ris
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
Signed-off-by: Jim Wilson
---
target/riscv/cpu.c | 9 +-
target/riscv/cpu.h | 2
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
configure | 1 +
gdb-xml/riscv-64bit-cpu.xml | 43
gdb-xml/riscv-64bit-csr.xml | 250
gdb-xml/riscv-64bit-fpu.xml | 52 +
4 files changed, 346 insertion
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 +
target/riscv/csr.c | 34 ++
2 files changed
On Wed, 23 Jan 2019 01:25:03 PST (-0800), Bastian Koppelmann wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in four major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-16]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 3
On Tue, Feb 12, 2019 at 3:10 PM Jim Wilson wrote:
>
> The gdb CSR xml file has registers in documentation order, not numerical
> order, so we need a table to map the register numbers. This also adds
> fairly standard gdb hooks to access xml specified registers.
>
> Signed-off-by: Jim Wilson
Rev
On Mon, Jan 28, 2019 at 10:46:13AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> There's no point in going out of translation on an SMT OR with
> mttcg since the backend won't do anything useful such as pausing,
> it's only useful on traditional TCG to give time to other
> pro
On Mon, Jan 28, 2019 at 10:46:14AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> Those instructions currently raise an exception from within
> the helper. This tends to result in a bogus nip value in
> the env context (typically the beginning of the TB). Such
> a helper needs
On Mon, Jan 28, 2019 at 10:46:15AM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> When issuing a power management instruction, we set MSR:EE
> to force ppc_hw_interrupt() into calling powerpc_excp()
> to deal with the fact that on P7 and P8, the system reset
> caused by the wak
On Tue, 2019-02-12 at 17:02 +1100, David Gibson wrote:
> On Mon, Jan 28, 2019 at 10:46:14AM +0100, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt
> >
> > Those instructions currently raise an exception from within
> > the helper. This tends to result in a bogus nip value in
> > the env
On Tue, 2019-02-12 at 16:59 +1100, David Gibson wrote:
> On Mon, Jan 28, 2019 at 10:46:13AM +0100, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt
> >
> > There's no point in going out of translation on an SMT OR with
> > mttcg since the backend won't do anything useful such as pausing,
On Tue, 12 Feb 2019, Philippe Mathieu-Daudé wrote:
On 2/11/19 5:01 AM, BALATON Zoltan wrote:
Add (partial) emulation of the on-board GPU of the machine. This
allows the PMON2000 firmware to run and should also work with Linux
console but probably not with X yet.
Signed-off-by: BALATON Zoltan
-
Hello,
On Tue, 12 Feb 2019, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
Thanks for the quick review and testing. I'll use your suggestions for the
other (mips) patches in a v2. For this one I'm not convinced.
On 2/11/19 4:19 AM, BALATON Zoltan wrote:
[...]
+
+static void ati_reg_write_offs(
On Tue, Feb 12, 2019 at 9:39 AM Fabien Chouteau wrote:
>
> QEMU model of the GPIO device on the SiFive E300 series SOCs.
>
> The pins are not used by a board definition yet, however this
> implementation can already be used to trigger GPIO interrupts from the
> software by configuring a pin as bot
Commit caa1ee43 "vhost-user-blk: add discard/write zeroes features
support" added fields to struct virtio_blk_config. This changes
the size of the config space and breaks migration from QEMU 3.1
and older:
qemu-system-ppc64: get_pci_config_device: Bad config data: i=0x10 read: 41
device: 1 cmask:
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Tuesday, February 12, 2019 11:11 PM
> To: Liu, Changpeng
> Cc: qemu-devel@nongnu.org; stefa...@redhat.com; sgarz...@redhat.com;
> dgilb...@redhat.com; ldok...@redhat.com
> Subject: Re: [PATCH v3] virtio-blk
I recently ran into an issue where I found I couldn't combine the
-loadvm and -snapshot flags, nor any conceivable combination of
alternate approaches like loadvm via the monitor. Independently, both
options work as expected, but together I get this error:
qemu-system-x86_64: Device 'virtio0' does
On Wed, Feb 13, 2019 at 09:48:57AM +0800, Changpeng Liu wrote:
> Commit caa1ee43 "vhost-user-blk: add discard/write zeroes features
> support" added fields to struct virtio_blk_config. This changes
> the size of the config space and breaks migration from QEMU 3.1
> and older:
>
> qemu-system-ppc64
On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt wrote:
> On Wed, 23 Jan 2019 01:25:03 PST (-0800), Bastian Koppelmann wrote:
> > Hi,
> >
> > this patchset converts the RISC-V decoder to decodetree in four major
> steps:
> >
> > 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> > Man
On Tue, Feb 12, 2019 at 10:57:49AM +0100, Paolo Bonzini wrote:
[...]
> +Writing and modifying default configurations
> +
> +
> +In addition to the Kconfig files under hw/, each target also includes
> +a file called ``default-configs/TARGETNAME-softmmu.m
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