Dave, I tried to review the error paths, in particular resource cleanup,
but there's a lot going on, and I'm not feeling confident. Please have
a close look.
Fei Li writes:
> From: Fei Li
>
> Update qemu_thread_create()'s callers by
> - setting an error on qemu_thread_create() failure for call
On 2/1/19 7:45 AM, Cornelia Huck wrote:
We currently don't migrate any state for zpci devices, which are
coupled with standard pci devices. This means funny things happen
when we e.g. try to migrate with a virtio-pci device but the s390x-
specific zpci state is not migrated (vfio-pci is not affec
I can confirm this, KDE Neon using the command line similar to yours
crashes QEMU to me too. I will test with Mageia 7 later to see if it
behaves differently.
But this is a completely different crash. This crash is happening
earlier, what I reported first is a crash when the login screen should
lo
On Fri, 1 Feb 2019 at 02:34, Stefan Hajnoczi wrote:
>
> v4:
> * assert(offset + size <= s->flash_size) [Peter]
> v3:
> * Fix endianness of s->storage[], tested by Joel Stanley on
>big-endian ppc [Peter]
> * Fix off-by-one that prevented clearing the last page of flash
> * Add missing memo
On 2/1/19 4:18 AM, David Hildenbrand wrote:
On 01.02.19 09:35, Cornelia Huck wrote:
On Thu, 31 Jan 2019 15:43:16 -0500
Collin Walling wrote:
On 1/30/19 10:57 AM, David Hildenbrand wrote:
These are all the patches that are not yet upstream (@Conny you might
already picked some, including them
31.01.2019 16:46, Andrey Shinkevich wrote:
> A new test file 239 added to the qemu-iotests set. It checks
> the output format of 'qemu-img info' for bitmaps extension of
> qcow2 specific information.
>
> Signed-off-by: Andrey Shinkevich
> ---
> tests/qemu-iotests/239 | 74 +
From: kumar sourav
set object owner in memory_region_init_ram() instead
of NULL.
Signed-off-by: kumar sourav
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
Message-id: 20190125155630.17430-1-sourav.jb1...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/nrf51_soc.c | 3 ++
6:09 +)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20190201
for you to fetch changes up to 7743b70ffe7a8ce168adce2cf50ad156b1fefb8c:
tests/microbit-test: Add tests for nRF51 NVMC (2019-02-01 15:3
On 01.02.19 16:41, Collin Walling wrote:
> On 2/1/19 7:45 AM, Cornelia Huck wrote:
>> We currently don't migrate any state for zpci devices, which are
>> coupled with standard pci devices. This means funny things happen
>> when we e.g. try to migrate with a virtio-pci device but the s390x-
>> speci
The SSE-200 gives each CPU a register bank to use to control its
L1 instruction cache. Put in an unimplemented-device stub for this.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-18-peter.mayd...@linaro.org
---
include/hw/arm/armsse.h | 1 +
hw/ar
The Arm SSE-200 Subsystem for Embedded is a revised and
extended version of the older IoTKit SoC. Prepare for
adding a model of it by refactoring the IoTKit code into
an abstract base class which contains the functionality,
driven by a class data block specific to each subclass.
(This is the same a
Rather than just creating the CPUs with object_new, make them child
objects of the armv7m container. This will allow the cluster code to
find the CPUs if an armv7m object is made a child of a cluster object.
object_new_with_props() will do the parenting for us.
Signed-off-by: Peter Maydell
Review
Currently the ARMv7M NVIC object's realize method assumes that the
CPU the NVIC is attached to is CPU 0, because it thinks there can
only ever be one CPU in the system. To allow a dual-Cortex-M33
setup we need to remove this assumption; instead the armv7m
wrapper object tells the NVIC its CPU, in t
The Arm IoTKit was effectively the forerunner of a series of
subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200:
https://developer.arm.com/products/system-design/subsystems
These are generally quite similar, though later iterations have
extra devices that earlier ones do not.
We
Expose "start-powered-off" as a property of the ARMv7M container,
which we just pass through to the CPU object in the same way that we
do for "init-svtor" and "idau". (We want this for the SSE-200, which
powers up only the first CPU at reset and leaves the second powered
down.)
As with the other C
In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.
Reported-by: Laurent Desnogues
Signed-off-by: Peter Maydell
Reviewed-by: Laurent Desnogues
Message-id: 20190125182626.9
Create a cluster object to hold each CPU in the SSE. They are
logically distinct and may be configured differently (for instance
one may not have an FPU where the other does).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-14-peter.mayd...@linaro.org
Instantiate a copy of the CPU_IDENTITY register block for each CPU
in an SSE-200.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-21-peter.mayd...@linaro.org
---
include/hw/arm/armsse.h | 3 +++
hw/arm/armsse.c | 28 +
In the AdvSIMD scalar x indexed element and vector x indexed element
encoding group, the SDOT and UDOT instructions are vector only,
and their opcode is unallocated in the scalar group. Correctly
UNDEF this unallocated encoding.
Reported-by: Laurent Desnogues
Signed-off-by: Peter Maydell
Reviewe
Add a model of the SSE-200, now we have put in all
the code that lets us make it different from the IoTKit.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-22-peter.mayd...@linaro.org
---
include/hw/arm/armsse.h | 19 ---
hw/arm/armss
In the AdvSIMD load/store multiple structures encodings,
the non-post-indexed case should have zeroes in [20:16]
(which is the Rm field for the post-indexed case).
Correctly UNDEF the currently unallocated encodings which
have non-zeroes in those bits.
Reported-by: Laurent Desnogues
Signed-off-by
From: Aaron Lindsay OS
Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
Message-id: 20190124162401.5111-2-aa...@os.amperecomputi
From: Richard Henderson
Initialize the keys to a non-zero value on process start.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
linux-user/aarch64/target_syscall.h | 2 ++
linux-user/aarch64/cpu_loop.c | 31 +++--
From: Steffen Görtz
Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC.
Signed-off-by: Steffen Görtz
Reviewed-by: Peter Maydell
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Stefan Hajnoczi
Message-id: 20190201023357.22596-3-stefa...@redhat.com
Signed-off-by: Peter Maydell
---
include/hw/a
Rename various internal uses of 'iotkit' in hw/arm/iotkit.c to
'armsse', for consistency. The remaining occurences are:
* related to the devices TYPE_IOTKIT_SYSCTL, TYPE_IOTKIT_SYSINFO,
etc, which this refactor is not touching
* references that apply specifically to the IoTKit (like
the lac
Give each CPU its own container memory region. This is necessary
for two reasons:
* some devices are instantiated one per CPU and the CPU sees only
its own device
* since a memory region can only be put into one container, we must
give each armv7m object a different MemoryRegion as its 'mem
The "system instructions" and "system register move" subcategories
of "branches, exception generating and system instructions" for A64
only apply if bits [23:22] are zero; other values are currently
unallocated. Correctly UNDEF these unallocated encodings.
Reported-by: Laurent Desnogues
Signed-of
From: Steffen Görtz
Signed-off-by: Steffen Görtz
Signed-off-by: Stefan Hajnoczi
Acked-by: Thomas Huth
Reviewed-by: Peter Maydell
Message-id: 20190201023357.22596-4-stefa...@redhat.com
Signed-off-by: Peter Maydell
---
tests/microbit-test.c | 108 ++
1
In the encoding groups
* floating-point data-processing (1 source)
* floating-point data-processing (2 source)
* floating-point data-processing (3 source)
* floating-point immediate
* floating-point compare
* floating-ponit conditional compare
* floating-point conditional select
bit 31 is M
The SSE-200 has 4 banks of SRAM, each with its own internal
Memory Protection Controller. The interrupt status for these
extra MPCs appears in the same security controller SECMPCINTSTATUS
register as the MPC for the IoTKit's single SRAM bank. Enhance the
iotkit-secctl device to allow 4 MPCs. (If th
The SSE-200 has a "CPU local security control" register bank; add an
unimplemented-device stub for it. (The register bank has only one
interesting register, which allows the guest to lock down changes
to various CPU registers so they cannot be modified further. We
don't support that in our Cortex-M
The SSE-200 has four banks of SRAM, each with its own
Memory Protection Controller, where the IoTKit has only one.
Make the number of SRAM banks a field in ARMSSEInfo.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-10-peter.mayd...@linaro.org
---
in
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Laurent Vivier
Signed-off-by: Peter Maydell
---
linux-user/elfload.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 4cff9e1a313..3c7a7c2836f 100644
--- a/linux
The SYS_VERSION and SYS_CONFIG register values differ between the
IoTKit and SSE-200. Make them configurable via QOM properties rather
than hard-coded, and set them appropriately in the ARMSSE code that
instantiates the IOTKIT_SYSINFO device.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hend
From: Richard Henderson
Drop the pac properties. This approach cannot work as written
because the properties are applied before arm_cpu_reset, which
zeros SCTLR_EL1 (amongst everything else).
We can re-introduce the properties if they turn out to be useful.
But since linux 5.0 enables all of th
From: Julia Suvorova
Until now, the set_pc logic was unclear, which raised questions about
whether it should be used directly, applying a value to PC or adding
additional checks, for example, set the Thumb bit in Arm cpu. Let's set
the set_pc logic for “Configure the PC, as was done in the ELF fi
Add unimplemented-device stubs for the various Power Policy Unit
devices that the SSE-200 has.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-17-peter.mayd...@linaro.org
---
include/hw/arm/armsse.h | 11
hw/arm/armsse.c | 58 +++
From: Remi Denis-Courmont
A flawed test lead to the instructions always being treated as
unallocated encodings.
Fixes: https://bugs.launchpad.net/bugs/1813460
Signed-off-by: Remi Denis-Courmont
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
target/arm/translate-a64.c | 2 +-
Add a model of the MPS2 FPGA image described in Application Note
AN521. This is identical to the AN505 image, except that it uses
the SSE-200 rather than the IoTKit and so has two Cortex-M33 CPUs.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-24-pet
The tcg_register_iommu_notifier() code has a GArray of
TCGIOMMUNotifier structs which it has registered by passing
memory_region_register_iommu_notifier() a pointer to the embedded
IOMMUNotifier field. Unfortunately, if we need to enlarge the
array via g_array_set_size() this can cause a realloc(),
From: Steffen Görtz
The nRF51 contains three regions of non-volatile memory (NVM):
- CODE (R/W): contains code
- FICR (R): Factory information like code size, chip id etc.
- UICR (R/W): Changeable configuration data. Lock bits, Code
protection configuration, Bootloader address, Nordic SoftRadio
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
linux-user/elfload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 3c7a7c2836f..775a36ccdda 100644
--- a/linux-user/elfl
Rename the files that used to be iotkit.[ch] to
armsse.[ch] to reflect the fact they new cover
multiple Arm subsystems for embedded.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-8-peter.mayd...@linaro.org
---
h
The PRFM prefetch insn in the load/store with imm9 encodings
requires idx field 0b00; we were underdecoding this by
only checking !is_unpriv (which is equivalent to idx != 2).
Correctly UNDEF the unallocated encodings where idx == 0b01
and 0b11 as well as 0b10.
Reported-by: Laurent Desnogues
Sign
On 1/31/19 4:26 PM, Cleber Rosa wrote:
>
>
> On 1/31/19 3:21 PM, Cleber Rosa wrote:
>>
>>
>> On 1/31/19 3:02 PM, Wainer dos Santos Moschetta wrote:
>>>
>>> On 01/17/2019 04:56 PM, Cleber Rosa wrote:
Just like the previous tests, boots a Linux kernel on a aarch64 target
using the virt
In disas_simd_indexed(), for the case of "complex fp", each indexable
element is a complex pair, so the total size is twice that indicated
in the 'size' field in the encoding. We were trying to do this
"double the size" operation with a left shift by 1, but this is
incorrect because the 'size' fiel
From: Remi Denis-Courmont
Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address,
extension (yet), the VA address space is 48-bits plus a sign bit. User
mode can only handle the positive half of the address space, so that
makes a limit of 48 bits.
(With LVA, it would be 53 and 52 bit
The FCMLA (by element) instruction exists in the
"vector x indexed element" encoding group, but not in
the "scalar x indexed element" group. Correctly UNDEF
the unallocated encodings.
Reported-by: Laurent Desnogues
Signed-off-by: Peter Maydell
Reviewed-by: Laurent Desnogues
Message-id: 20190129
On 2/1/19 4:21 AM, Kevin Wolf wrote:
> Am 31.01.2019 um 19:43 hat Eric Blake geschrieben:
>> On 1/31/19 11:55 AM, Kevin Wolf wrote:
>>> This adds external data file to the qcow2 spec as a new incompatible
>>> feature.
>>>
>>> Signed-off-by: Kevin Wolf
>>> ---
>>> docs/interop/qcow2.txt | 19 +
For the IoTKit the SRAM bank size is always 32K (15 bits); for the
SSE-200 this is a configurable parameter, which defaults to 32K but
can be changed when it is built into a particular SoC. For instance
the Musca-B1 board sets it to 128K (17 bits).
Make the bank size a QOM property. We follow the
From: Aaron Lindsay OS
Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.
Signed-off-by: Aaron Lindsay
Reviewed-by: Richard Henderson
Message-id: 20190124162401.5111-3
From: Richard Henderson
These bits become writable with the ARMv8.3-PAuth extension.
Signed-off-by: Richard Henderson
Message-id: 20190129143511.12311-1-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 6 ++
1 file changed, 6
On Fri, 1 Feb 2019 at 16:19, Alex Bennée wrote:
> It reports:
>
> Documentation no
>
> But then proceeds to barf:
>
> https://travis-ci.org/stsquad/qemu/jobs/487512292#L1395
>
> with:
>
> /bin/sh: 1: sphinx-build: not found
> Makefile:871: recipe for target 'docs/devel/index.html' fail
The SSE-200 has two Message Handling Units (MHUs), which sit behind
the APB PPC0. Wire up some unimplemented-device stubs for these,
since we don't yet implement a real model of this device.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20190121185118.18550-16-peter.may
In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.
Reported-by:
On 2/1/19 12:32 AM, Aleksandar Markovic wrote:
>>> I think, the term "arch" is a little problematic in QEMU parlance. IMHO,
>>> "target" should be used instead. ("arch" is used in Linux kernel community)
>
>> Naming things is hard, so this is a valid discussion. But, I have to
>> say that I al
The SSE-200 has a CPU_IDENTITY register block, which is a set of
read-only registers. As well as the usual PID/CID registers, there
is a single CPUID register which indicates whether the CPU is CPU 0
or CPU 1. Implement a model of this register block.
Signed-off-by: Peter Maydell
Reviewed-by: Ric
If QEMU was configured with a driver in --block-drv-ro-whitelist, trying
to use that driver read-write resulted in an error message even if
auto-read-only=on was set.
Consider auto-read-only=on for the whitelist checking and use it to
automatically degrade to read-only for block drivers on the rea
In preparation for adding support for the AN521 MPS2 image, we need
to handle wiring up the MPS2 device interrupt lines to both CPUs in
the SSE-200, rather than just the one that the IoTKit has.
Abstract out a "connect to the IoTKit interrupt line" function
and make it connect to a splitter which
Peter Maydell writes:
> Add support to our configure and makefile machinery for building
> our rST docs into HTML files.
>
> Building the documentation now requires that sphinx-build is
> available; this seems better than allowing half the docs to
> be built if it is not present but having half
The SSE-200 has two Cortex-M33 CPUs. These see the same view
of memory, with the exception of the "private CPU region" which
has per-CPU devices. Internal device interrupts for SSE-200
devices are mostly wired up to both CPUs, with the exception of
a few per-CPU devices. External GPIO inputs on the
From: Thomas Huth
The last user of blk_attach_dev_legacy() was the code in xen_disk which
has recently been reworked. Now there is no user for this legacy function
anymore. Thus we can finally remove all code related to the "legacy_dev"
flag, too, and turn the related "void *" in block-backend.c
Peter Maydell writes:
> Convert the memory API documentation from plain text
> to restructured text format.
>
> This is a very minimal conversion: all I had to change
> was to mark up the ASCII art parts as Sphinx expects
> for 'literal blocks', and fix up the bulleted lists
> (Sphinx expects n
Peter Maydell writes:
> sphinx-build complains:
>
> docs/cpu-hotplug.rst:67: ERROR: Unexpected indentation.
> docs/cpu-hotplug.rst:69: ERROR: Unexpected indentation.
> docs/cpu-hotplug.rst:74: WARNING: Block quote ends without a blank line;
> unexpected unindent.
> docs/cpu-hotplug.rst:75: WAR
bdrv_co_invalidate_cache() clears the BDRV_O_INACTIVE flag before
actually activating a node so that the correct permissions etc. are
taken. In case of errors, the flag must be restored so that the next
call to bdrv_co_invalidate_cache() retries activation.
Restoring the flag was missing in the er
The following changes since commit cfe6c547690b06fbce54a6d0f7b05dd7f18e36ea:
Merge remote-tracking branch 'remotes/xanclic/tags/pull-block-2019-01-31'
into staging (2019-01-31 19:26:09 +)
are available in the Git repository at:
git://repo.or.cz/qemu/kevin.git tags/for-upstream
for you
Clarify that the number of extents provided in BlockdevCreateOptionsVmdk
must match the number of extents that will actually be used. Providing
more extents will result in an error now.
This requires adapting the test case to provide the right number of
extents.
Signed-off-by: Kevin Wolf
Reviewe
From: Fam Zheng
The extracted vmdk_init_extent takes a BlockBackend object and
initializes the format metadata. It is the common part between "qemu-img
create" and "blockdev-create".
Add a "BlockBackend *pbb" parameter to vmdk_create_extent, to return the
opened BB to the caller in the next patc
From: Alberto Garcia
The mirror_start_job() function used for the commit-active job blocks
the source, target and all intermediate nodes for the duration of the
job.
target <- intermediate <- source
Since 4ef85a9c2339 this function creates a dummy mirror_top_bs that
goes on top of the source
From: Markus Armbruster
Patch created mechanically by rerunning:
$ spatch --sp-file scripts/coccinelle/qobject.cocci \
--macro-file scripts/cocci-macro-file.h \
--dir block --in-place
Signed-off-by: Markus Armbruster
Reviewed-by: Alberto Garcia
Reviewed-by: Eric Bla
From: Alberto Garcia
At the moment I don't see how to make this function fail after the
dirty bitmap has been created, but if that was possible then we would
hit the assert(QLIST_EMPTY(&bs->dirty_bitmaps)) in bdrv_close().
Signed-off-by: Alberto Garcia
Signed-off-by: Kevin Wolf
---
block/mirr
In the block layer, synchronous APIs are often implemented by creating a
coroutine that calls the asynchronous coroutine-based implementation and
then waiting for completion with BDRV_POLL_WHILE().
For this to work with iothreads (more specifically, when the synchronous
API is called in a thread t
From: Peter Maydell
Taking the address of a field in a packed struct is a bad idea, because
it might not be actually aligned enough for that pointer type (and
thus cause a crash on dereference on some host architectures). Newer
versions of clang warn about this.
Instead of passing UUID related f
From: Peter Maydell
Taking the address of a field in a packed struct is a bad idea, because
it might not be actually aligned enough for that pointer type (and
thus cause a crash on dereference on some host architectures). Newer
versions of clang warn about this. Avoid the bug by generating the
UU
From: Alberto Garcia
This fixes a crash when attaching two disks with the same blockdev to
a SCSI device that is using iothreads. Test case included.
Signed-off-by: Alberto Garcia
Signed-off-by: Kevin Wolf
---
hw/scsi/scsi-disk.c| 23 ---
tests/qemu-iotests/240
From: Markus Armbruster
We define 54 macros for the powers of two >= 1024. We use six, in six
macro definitions. Four of them could just as well use the common MiB
macro, so do that. The remaining two can't, because they get passed
to stringify. Replace the macro by the literal number there.
From: Fam Zheng
Signed-off-by: Fam Zheng
Signed-off-by: Kevin Wolf
---
tests/qemu-iotests/common.filter | 1 +
tests/qemu-iotests/iotests.py| 1 +
2 files changed, 2 insertions(+)
diff --git a/tests/qemu-iotests/common.filter b/tests/qemu-iotests/common.filter
index 2031e353a5..1aa7d57140
From: John Snow
It's not enough to order the kwargs for consistent QMP log output,
we must also sort any sub-dictionaries in lists that appear as values.
Reported-by: Kevin Wolf
Signed-off-by: John Snow
Reviewed-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Kevin Wo
scsi-disk includes in the Device Identification VPD page, depending on
configuration amongst others, a vendor specific designator that consists
either of the serial number if given or the BlockBackend name (which is
a host detail that better shouldn't have been leaked to the guest, but
now we have
Signed-off-by: Fam Zheng
Signed-off-by: Kevin Wolf
---
tests/qemu-iotests/237 | 233 +
tests/qemu-iotests/237.out | 347 +
tests/qemu-iotests/group | 1 +
3 files changed, 581 insertions(+)
create mode 100755 tests/qemu-iotests
From: Max Reitz
Without this filter, this test sometimes fails.
Signed-off-by: Max Reitz
Reviewed-by: John Snow
Signed-off-by: Kevin Wolf
---
tests/qemu-iotests/229 | 6 +-
tests/qemu-iotests/229.out | 1 -
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/tests/qemu-iot
From: Alberto Garcia
This patch forbids attaching a disk to a SCSI device if its using a
different AioContext. Test case included.
Signed-off-by: Alberto Garcia
Signed-off-by: Kevin Wolf
---
hw/scsi/virtio-scsi.c | 7 +++
tests/qemu-iotests/240 | 22 ++
tests
The new device_id property specifies which value to use for the vendor
specific designator in the Device Identification VPD page.
In particular, this is necessary for libvirt to maintain guest ABI
compatibility when no serial number is given and a VM is switched from
-drive (where the BlockBackend
From: Alberto Garcia
Refcount table entries have a field to store the offset of the
refcount block. The rest of the bits of the entry are currently
reserved.
The offset is always taken from the entry using REFT_OFFSET_MASK to
ensure that we only use the bits that belong to that field.
While tha
From: yuchenlin
Recently, some bugs in dmg file have been fixed. To prevent reading dmg
is broken someday in the future, add a simple test which ensures the
conversion from dmg to raw should not hang or face any I/O error.
Signed-off-by: yuchenlin
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Ke
Peter Maydell writes:
> Sphinx defaults to including all the rST source files
> in the HTML build and making each HTML page link to the
> source file. Disable that.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
> ---
> docs/conf.py | 3 +++
> 1 file changed, 3 insertions(+)
>
>
From: Alberto Garcia
The cmd() method of the QEMUQtestProtocol class sends a qtest command
to QEMU but doesn't wait for the return message ("OK", "FAIL", "ERR").
Because of this, it can return control to the caller before the
command has actually finished.
In cases like clock_step or clock_set t
From: Peter Maydell
Currently qemu_uuid_bswap() takes a pointer to the QemuUUID to
be byte-swapped. This means it can't be used when the UUID
to be swapped is in a packed member of a struct. It's also
out of line with the general bswap*() functions we provide
in bswap.h, which take the value to b
Peter Maydell writes:
> sphinx-build complains about using :option: to mark up option
> flags that it doesn't know about (because they were not defined
> using the "option::" directive):
> docs/pr-manager.rst:68: WARNING: unknown option: -d
>
> Suppress these warnings. This way we get the seman
From: Fam Zheng
This makes VMDK support blockdev-create. The implementation reuses the
image creation code in vmdk_co_create_opts which now acceptes a callback
pointer to "retrieve" BlockBackend pointers from the caller. This way we
separate the logic between file/extent acquisition and initializ
From: Max Reitz
This test waits for a MIGRATION event with status=completed on the
source VM before querying the migration status on both source and
destination. However, just because the source says migration has
completed does not mean the destination thinks the same. Therefore, in
some cases
Peter Maydell writes:
> Don't hard-code the QEMU version number into conf.py. Instead
> we either pass it to sphinx-build on the command line, or
> (if doing a standalone Sphinx run in a readthedocs.org setup)
> extract it from the VERSION file.
>
> Signed-off-by: Peter Maydell
Ahh the perils
Am 01.02.2019 um 17:17 hat Eric Blake geschrieben:
> On 2/1/19 4:21 AM, Kevin Wolf wrote:
> > Am 31.01.2019 um 19:43 hat Eric Blake geschrieben:
> >> On 1/31/19 11:55 AM, Kevin Wolf wrote:
> >>> This adds external data file to the qcow2 spec as a new incompatible
> >>> feature.
> >>>
> >>> Signed-o
Peter Maydell writes:
> We don't yet have any custom static files, so disable this
> config file setting to avoid a warning from sphinx about
> not being able to find the directory.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
> docs/conf.py | 6 +-
> 1 file changed, 5 in
From: Alberto Garcia
This fixes a crash when attaching a disk to a SCSI device using
iothreads, then detaching it and reattaching it again. Test case
included.
Signed-off-by: Alberto Garcia
Signed-off-by: Kevin Wolf
---
hw/scsi/virtio-scsi.c | 6 +++
tests/qemu-iotests/240 | 89
Am 31.01.2019 um 14:46 hat Andrey Shinkevich geschrieben:
> Inform a user in case qcow2_get_specific_info fails to obtain
> QCOW2 image specific information. This patch is preliminary to
> the print of bitmap information in the 'qemu-img info' output.
>
> Signed-off-by: Andrey Shinkevich
> Review
On Fri, 1 Feb 2019 at 16:41, Alex Bennée wrote:
>
>
> Peter Maydell writes:
> > +# General information about the project.
> > +project = u'QEMU'
> > +copyright = u'2019, The QEMU Project Developers'
>
> Hmm I bet we forget to update this date. Does it have to be the date the
> text was last touc
Patchew URL:
https://patchew.org/QEMU/20190201145035.22739-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH 00/11] Enable build and install of our rST docs
Type: series
Message-id: 2019020
Patchew URL: https://patchew.org/QEMU/20190201163518.31157-1-kw...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] Block layer patches
Type: series
Message-id: 20190201163518.31157-1-kw...@redhat.co
Peter Maydell writes:
> ---
> docs/conf.py | 37 +++--
> docs/devel/conf.py | 15 +++
> docs/devel/index.rst | 21 +
> docs/index.rst | 9 ++---
> docs/interop/conf.py | 15 +++
> docs/in
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