On 2 November 2018 at 12:32, Alex Bennée wrote:
>
> Richard Henderson writes:
>
>> When populating id registers from kvm, on a host that doesn't support
>> aarch32 mode at all, neither arm_div nor jazelle will be supported either.
>>
>> Signed-off-by: Richard Henderson
>> ---
>>
>> v2: Test aa64
On 24 October 2018 at 12:37, Richard Henderson
wrote:
> The ID registers are replacing (some of) the feature bits.
> We need (some of) these values to determine the set of data
> to be handled during migration.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/kvm_arm.h | 1 +
> target/arm
On 24 October 2018 at 12:37, Richard Henderson
wrote:
> Assert that the value to be written is the correct size.
> No change in functionality here, just mirroring the same
> function from kvm64.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/kvm32.c | 41
Hi Aleksandar,
> It is now code freeze before 3.1, the code base is being stabilized, and
> only important fixes are allowed to be integrated - so, in that light, a
> separate patch, or a small series, that addresses only concerns from the
> original mail of this thread is needed. Such series shou
On 24 October 2018 at 12:37, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 6 +-
> linux-user/elfload.c | 2 +-
> target/arm/cpu.c | 4
> target/arm/helper.c | 2 +-
> target/arm/kvm32.c | 3 ---
> target/arm/machine.c | 3 +--
> 6 fil
On 11/2/18 2:30 PM, Peter Maydell wrote:
> (Confusingly, ENCODE_CP_REG and ARM_CP15_REG32 take the
> op1/crn/crm/op2 arguments in different orders.)
As Shaggy said, "It wasn't me". ;-)
r~
On 29 October 2018 at 16:03, Richard Henderson
wrote:
> On 10/29/18 2:58 PM, Peter Maydell wrote:
>> I think I would prefer it if we expanded the id_isar* fields
>> in the ARMISARegisters struct to uint64_t. If you dislike
>> that, I think we should make this code fail a bit more gracefully
>> in
On 2 November 2018 at 13:19, Edgar E. Iglesias
wrote:
> This patch series adds initial support for Xilinx's Versal SoC.
> Xilinx is introducing Versal, an adaptive compute acceleration platform
> (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
> Processing Engines, Adap
On 11/2/18 9:10 AM, Kevin Wolf wrote:
Am 02.11.2018 um 13:37 hat Philippe Mathieu-Daudé geschrieben:
Hi Kevin,
On 2/11/18 12:07, Kevin Wolf wrote:
Am 02.11.2018 um 09:58 hat Philippe Mathieu-Daudé geschrieben:
This definitions are QCow2 specific, there is no need to expose them
in the global
My previous patch set for replacing feature bits with id registers
failed to consider that these id registers are beginning to control
migration, and thus we must fill them in for KVM as well.
Thus, we want to initialize these values within CPU from the host.
Finally, re-send the T32EE conversion
Signed-off-by: Richard Henderson
---
target/arm/kvm64.c | 69 --
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 5de8ff0ac5..d4d4e63140 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
The ID registers are replacing (some of) the feature bits.
We need (some of) these values to determine the set of data
to be handled during migration.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 1 +
target/arm/kvm.c | 1 +
2 files changed, 2 inser
Assert that the value to be written is the correct size.
No change in functionality here, just mirroring the same
function from kvm64.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/kvm32.c | 41 -
1 file changed, 16 insertions
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 +-
linux-user/elfload.c | 2 +-
target/arm/cpu.c | 4
target/arm/helper.c | 2 +-
target/arm/kvm32.c | 3 ---
target/arm/machine.c | 3 +--
6 files changed, 8 insertions(+), 12 deletions(-)
Signed-off-by: Richard Henderson
---
target/arm/kvm32.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index de573f9aa8..9ededa3c73 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -44,7 +44
On Fri, Nov 02, 2018 at 11:54:21AM +0100, Kevin Wolf wrote:
> Am 02.11.2018 um 02:22 hat Li Qiang geschrieben:
> > Currently, the nvme_cmb_ops mr doesn't check the addr and size.
> > This can lead an oob access issue. This is triggerable in the guest.
> > Add check to avoid this issue.
> >
> > Fix
On 31 October 2018 at 00:25, Steffen Görtz wrote:
> This adds a model of the nRF51 GPIO peripheral.
>
> Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
>
> The nRF51 series microcontrollers support up to 32 GPIO pins in various
> configurations.
> The pins can be used as
Hi, Fredrik.
> From: Fredrik Noring
> Subject: Re: [Qemu-devel] Correction needed for R5900 instruction decoding
>
> Hi Aleksandar,
>
> > It is now code freeze before 3.1, the code base is being stabilized, and
> > only important fixes are allowed to be integrated - so, in that light, a
> > sep
Add a function to export error hint - a pair to error_get_pretty. It's
needed to handle errors by hand, where we can't just report it or
propagate.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/qapi/error.h | 5 +
util/error.c | 5 +
2 files changed, 10 insertions(+)
d
Reduce extra noise of nbd-client, change 083 correspondingly.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/nbd-client.c | 27 +++
block/trace-events | 4
tests/qemu-iotests/083.out | 28
3 files changed, 27 inser
These functions are used for formatting pretty trace points. We are
going to add some in block/nbd-client, so, let's publish all these
functions at once. Note, that nbd_reply_type_lookup is already
published, and constants, "named" by these functions live in
include/block/nbd.h too.
Signed-off-by:
Hi all.
It was discussed, that error messages, produced by error_reprt_err's,
added in f140e300 are
1. not really needed
2. subject to race conditions
And it was decided to drop them (switch to trace-points), look thread
https://lists.gnu.org/archive/html/qemu-devel/2018-08/msg00833.html
So, I'v
On 2 November 2018 at 15:03, Aleksandar Markovic wrote:
> Hi, Fredrik.
>
>> From: Fredrik Noring
>> Subject: Re: [Qemu-devel] Correction needed for R5900 instruction decoding
>>
>> Hi Aleksandar,
>>
>> > It is now code freeze before 3.1, the code base is being stabilized, and
>> > only important
Hello Kevin,
Kevin Wolf 于2018年11月2日周五 下午6:54写道：
> Am 02.11.2018 um 02:22 hat Li Qiang geschrieben:
> > Currently, the nvme_cmb_ops mr doesn't check the addr and size.
> > This can lead an oob access issue. This is triggerable in the guest.
> > Add check to avoid this issue.
> >
> > Fixes CVE-201
From: Laurent Vivier
On Sparc and PowerMac, the bit 0 of the address
selects the register type (control or data) and
bit 1 selects the channel (B or A).
On m68k Macintosh, the bit 0 selects the channel and
bit 1 the register type.
This patch introduces a new parameter (bit_swap) to
the device i
(MCA: here's the latest version of the q800 patchset. I've hope that I've
addressed most of the comments, plus this will now boot into the Debian
installer correctly when applied to git master.
Outstanding comments:
1) Should the comment blocks copied from the Linux headers be removed
from
From: Laurent Vivier
Co-developed-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
Reviewed-by: Hervé Poussineau
---
hw/misc/Makefile.objs | 1 +
hw/misc/mac_via.c | 666 ++
include/hw/misc/mac_via.h
Co-developed-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
Reviewed-by: Hervé Poussineau
---
hw/display/macfb.c | 56 ++
include/hw/display/macfb.h | 21 +
2 files changed, 77 insertions(+)
From: Laurent Vivier
Co-developed-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
Reviewed-by: Hervé Poussineau
---
arch_init.c| 4 +
hw/display/Makefile.objs | 1 +
hw/display/macfb.c | 419
From: Laurent Vivier
Co-developed-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
---
hw/Makefile.objs| 1 +
hw/nubus/Makefile.objs | 4 +
hw/nubus/mac-nubus-bridge.c | 45
hw/nubus/nubus-bridge.c
From: Laurent Vivier
Co-developed-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
Reviewed-by: Hervé Poussineau
---
hw/misc/mac_via.c | 190 ++
include/hw/misc/mac_via.h | 7 ++
2 files changed, 197 inse
From: Laurent Vivier
If you want to test the machine, it doesn't yet boot a MacROM, but you can
boot a linux kernel from the command line.
You can install your own disk using debian-installer with:
./qemu-system-m68k \
-M q800 \
-serial none -serial mon:stdio \
-m 1000M -drive f
From: Laurent Vivier
Co-developed-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
Reviewed-by: Hervé Poussineau
---
hw/block/Makefile.objs | 1 +
hw/block/swim.c | 415
include/hw/block/swim.h | 7
From: Laurent Vivier
Co-developed-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Laurent Vivier
---
hw/scsi/esp.c | 291 +-
include/hw/scsi/esp.h | 7 ++
2 files changed, 269 insertions(+), 29 deletions(-)
diff --
From: Laurent Vivier
This is needed by Quadra 800, this card can run on little-endian
or big-endian bus.
Signed-off-by: Laurent Vivier
Tested-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Hervé Poussineau
---
hw/net/dp8393x.c | 88
Am 02.11.2018 um 15:52 hat Eric Blake geschrieben:
> On 11/2/18 9:10 AM, Kevin Wolf wrote:
> > Am 02.11.2018 um 13:37 hat Philippe Mathieu-Daudé geschrieben:
> > > Hi Kevin,
> > >
> > > On 2/11/18 12:07, Kevin Wolf wrote:
> > > > Am 02.11.2018 um 09:58 hat Philippe Mathieu-Daudé geschrieben:
> > >
Hi Julia,
> Why do we need an extra file for this? nrf51_soc.h seemed like a good fit.
nrf51_soc.h is not included in the peripheral devices. It would be possible to
put the definitions into nrf51_soc.h but i just did not want to mix up the
dependency directions.
> What's the purpose of renam
Am 02.11.2018 um 16:22 hat Li Qiang geschrieben:
> Hello Kevin,
>
> Kevin Wolf 于2018年11月2日周五 下午6:54写道：
>
> > Am 02.11.2018 um 02:22 hat Li Qiang geschrieben:
> > > Currently, the nvme_cmb_ops mr doesn't check the addr and size.
> > > This can lead an oob access issue. This is triggerable in the
On Thu, Nov 01, 2018 at 06:22:43PM -0700, Li Qiang wrote:
> Currently, the nvme_cmb_ops mr doesn't check the addr and size.
> This can lead an oob access issue. This is triggerable in the guest.
> Add check to avoid this issue.
>
> Fixes CVE-2018-16847.
>
> Reported-by: Li Qiang
> Reviewed-by: P
Hi Peter,
> From the other side of things, as a submaintainer around release
> time there's often a lot of work to do and it's easy to confuse
> different patchsets or forget the status of them, so it's useful
> to have a patch series which is exactly the set of patches that
> the submitter thinks
Hi Stefan,
>
> Indentation is off here. One way of formatting it:
>
> address_space_write(&s->as, i * NRF51_PAGE_SIZE,
> MEMTXATTRS_UNSPECIFIED, s->empty_page,
> NRF51_PAGE_SIZE);
Good catch.
>> +static void
Hi Stefan,
> I'm a fan of '-' instead of '_' in qdev property names. There are more
> instances of '-' than '_', but it's up to you.
Agree. Changed.
Best,
Steffen
Hi Stefan,
>
> Indentation is off here. One way of formatting it:
>
> address_space_write(&s->as, i * NRF51_PAGE_SIZE,
> MEMTXATTRS_UNSPECIFIED, s->empty_page,
> NRF51_PAGE_SIZE);
Good catch.
>> +static void
This series amends the R5900 support with the following changes:
- MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead
of the generic gen_HILO.
- DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Fredrik Noring (2):
target/mips: Fix decoding
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 65 +
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translat
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 67 ++---
1 file changed, 56 insertions(+), 11 deletions(-)
diff --git a/target/mips/translate.c b/targe
Hi Stefan,
>
> gcc (GCC) 8.2.1 20181011 doesn't know that extract32(..., 3) can only
> result in values [0, 7] so it warns that state can be uninitialized.
>
> It might be simplest to include a default case that returns false (with
> a comment).
>
thank you for your remarks. Will be in the next v
On Fri, Nov 02, 2018 at 02:00:32PM +0100, Igor Mammedov wrote:
> On Fri, 2 Nov 2018 12:43:10 +0100
> David Hildenbrand wrote:
>
> > On 01.11.18 15:10, Igor Mammedov wrote:
> > > On Wed, 24 Oct 2018 12:19:25 +0200
> > > David Hildenbrand wrote:
> > >
> > >> For now, the hotplug handler is not
Hi Peter,
>
>
>> +static void reflect_dir_bit_in_cnf(NRF51GPIOState *s)
>> +{
>> +uint32_t value = s->dir;
>> +for (size_t i = 0; i < NRF51_GPIO_PINS; i++) {
>
> Similarly here, and I think I saw another use somewhere else
> in this patchset too.
I have removed the c99 style declaratio
On 19/10/2018 18:57, Peter Maydell wrote:
> From: Richard Henderson
>
> Instead of shifts and masks, use direct loads and stores from the neon
> register file. Mirror the iteration structure of the ARM pseudocode
> more closely. Correct the parameters of the VLD2 A2 insn.
>
> Note that this in
* Peter Xu (pet...@redhat.com) wrote:
> On Fri, Nov 02, 2018 at 11:00:24AM +0800, Fei Li wrote:
> >
> >
> > On 11/02/2018 10:37 AM, Peter Xu wrote:
> > > On Thu, Nov 01, 2018 at 06:17:11PM +0800, Fei Li wrote:
> > > > Set the migration state to "failed" instead of "setup" when failing
> > > > to
On 2 November 2018 at 14:54, Richard Henderson
wrote:
> My previous patch set for replacing feature bits with id registers
> failed to consider that these id registers are beginning to control
> migration, and thus we must fill them in for KVM as well.
>
> Thus, we want to initialize these values
On Thu, Nov 1, 2018 at 8:46 PM, Liran Alon wrote:
> Hmm this makes sense.
>
> This means though that the patch I have submitted here isn't good enough.
> My patch currently assumes that when it attempts to get nested state from KVM,
> QEMU should always set nested_state->size to max size supporte
ping
15.10.2018 19:06, Vladimir Sementsov-Ogievskiy wrote:
> Hi all!
>
> These series introduce backup-top driver. It's a filter-node, which
> do copy-before-write operation. Mirror uses filter-node for handling
> guest writes, let's move to filter-node (from write-notifiers) for
> backup too (pat
On Fri, Nov 2, 2018 at 5:59 AM, Liran Alon wrote:
>
>>> Therefore, I don't think that we want this versioning to be based on
>>> KVM_CAP at all.
>>> It seems that we would want the process to behave as follows:
>>> 1) Mgmt-layer at dest queries dest host max supported nested_state size.
>>> (W
Hi Stefan,
>
> Does anything rearm a running timer after live migration?
fixed in upcoming version.
Steffen
Chris Friesen writes:
> On 11/2/2018 1:51 AM, Alex Bennée wrote:
>>
>> Chris Friesen writes:
>>
>>> Hi all,
>>>
>>> I have an odd situation which occurs very infrequently and I'm hoping
>>> to get some advice on how to debug. Apologies for the length of this
>>> message, I tried to include as
On Fri, Nov 02, 2018 at 10:40:35AM +0100, Paolo Bonzini wrote:
> On 02/11/2018 04:46, Liran Alon wrote:
> >> On Thu, Nov1, 2018 at 09:45 AM, Jim Mattson wrote:
> >
> >>> On Thu, Nov 1, 2018 at 8:56 AM, Dr. David Alan Gilbert
> >>> wrote:
> >
> >>> So if I have matching host kernels it should a
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> On Fri, Nov 02, 2018 at 10:40:35AM +0100, Paolo Bonzini wrote:
> > On 02/11/2018 04:46, Liran Alon wrote:
> > >> On Thu, Nov1, 2018 at 09:45 AM, Jim Mattson wrote:
> > >
> > >>> On Thu, Nov 1, 2018 at 8:56 AM, Dr. David Alan Gilbert
> > >>> wr
On Fri, Nov 02, 2018 at 09:44:54AM -0700, Jim Mattson via Qemu-devel wrote:
> On Fri, Nov 2, 2018 at 5:59 AM, Liran Alon wrote:
> >
>
> >>> Therefore, I don't think that we want this versioning to be based on
> >>> KVM_CAP at all.
> >>> It seems that we would want the process to behave as follow
On Fri, Nov 2, 2018 at 9:58 AM, Daniel P. Berrangé wrote:
> On Fri, Nov 02, 2018 at 09:44:54AM -0700, Jim Mattson via Qemu-devel wrote:
>> On Fri, Nov 2, 2018 at 5:59 AM, Liran Alon wrote:
>> >
>>
>> >>> Therefore, I don't think that we want this versioning to be based on
>> >>> KVM_CAP at all.
Add a model of the NRF51 random number generator peripheral.
This is a simple random generator that continuously generates
new random values after startup.
Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
hw/
Use RNG in SOC.
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
hw/arm/nrf51_soc.c | 16
include/hw/arm/nrf51_soc.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 55f8eaafcb..d2a19b8ead 100644
--- a/h
This series contains additional peripheral devices for the nRF51822
microcontroller.
Included devices:
- Random Number Generator
- Non-volatile Memories
- General purpose I/O
- Timer
- Stub for clock peripheral
v4:
* Use int's instead of long's in set_irq_in, allow arbitrary base, fix
docu
The nRF51 contains three regions of non-volatile memory (NVM):
- CODE (R/W): contains code
- FICR (R): Factory information like code size, chip id etc.
- UICR (R/W): Changeable configuration data. Lock bits, Code
protection configuration, Bootloader address, Nordic SoftRadio
configuration, Firm
Adds a new qtest command "set_irq_in" which allows
to set qemu gpio lines to a given level.
Based on https://lists.gnu.org/archive/html/qemu-devel/2012-12/msg02363.html
which never got merged.
Signed-off-by: Steffen Görtz
Originally-by: Matthew Ogilvie
Reviewed-by: Stefan Hajnoczi
---
qtest.c
This stubs enables the microbit-micropython firmware to run
on the microbit machine.
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
hw/arm/nrf51_soc.c | 27 +++
include/hw/arm/nrf51_soc.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/hw/a
The microbit-test includes tests for the nRF51 NVMC
peripheral and will host future nRF51 peripheral tests
and board-level bbc:microbit tests.
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
tests/Makefile.include | 2 +
tests/microbit-test.c | 117 +
This adds a model of the nRF51 GPIO peripheral.
Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
The nRF51 series microcontrollers support up to 32 GPIO pins in various
configurations.
The pins can be used as input pins with pull-ups or pull-down.
Furthermore, three diffe
Instantiates UICR, FICR and NVMC in nRF51 SOC.
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
hw/arm/nrf51_soc.c | 37 ++---
include/hw/arm/nrf51_soc.h | 2 ++
2 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/hw/arm/nrf51_so
The test suite for the nRF51 GPIO peripheral for now
only tests initial state. Additionally a set of
tests testing an implementation detail of the model
are included.
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
tests/microbit-test.c | 137 ++
Instantiates GPIO peripheral model
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
hw/arm/nrf51_soc.c | 16
include/hw/arm/nrf51_soc.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index d11bb2b99f..2c4e80
Adds a header that provides definitions that are used
across nRF51 peripherals
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
hw/arm/nrf51_soc.c | 33 ++
include/hw/arm/nrf51.h | 45
include/hw/char/nrf5
On 11/2/2018 10:55 AM, Alex Bennée wrote:
Chris Friesen writes:
Given the "not initialized" message on the console, I wasn't sure
whether the kernel had even started yet.
There will be a lot that happens between the kernel decompressing and
some sort of video hardware output being started. Y
From: Prasad J Pandit
The high[31:28] bits of 'direction' and 'state' registers of
SA-1100/SA-1110 device are reserved. Setting them may lead to
OOB 's->handler[]' array access issue. Mask off [31:28] bits to
avoid it.
Reported-by: Moguofang
Signed-off-by: Prasad J Pandit
Message-id: 201810301
This patch adds the model for the nRF51 timer peripheral.
Currently, only the TIMER mode is implemented.
Signed-off-by: Steffen Görtz
---
hw/timer/Makefile.objs | 1 +
hw/timer/nrf51_timer.c | 368 +
hw/timer/trace-events | 5 +
includ
From: Julia Suvorova
Not implemented: CTS/NCTS, PSEL*.
Signed-off-by: Julia Suvorova
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Peter Maydell
---
hw/char/Makefile.objs| 1 +
include/hw/char/nrf51_uart.h | 78 +
hw/char/nrf51_uart.c | 330 ++
From: Eric Auger
We are missing the VIRT_COMPAT_3_0 definition and setting.
Let's add them.
Signed-off-by: Eric Auger
Reviewed-by: Andrew Jones
Message-id: 20181024085602.16611-1-eric.au...@redhat.com
Signed-off-by: Peter Maydell
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
d
Instantiates TIMER0 - TIMER2
Signed-off-by: Steffen Görtz
Reviewed-by: Stefan Hajnoczi
---
hw/arm/nrf51_soc.c | 27 +++
include/hw/arm/nrf51_soc.h | 4
2 files changed, 31 insertions(+)
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 2c4e80892b.
From: "Edgar E. Iglesias"
Add a virtual Xilinx Versal board.
This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to auto-discover
periphera
.git
tags/pull-target-arm-20181102
for you to fetch changes up to 6f16da53ffe4567c0353f85055df04860eb4e6fc:
hw/arm: versal: Add a virtual Xilinx Versal board (2018-11-02 14:11:31 +)
target-arm queue:
* microbit: Add the U
From: "Edgar E. Iglesias"
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias
Message-id: 20181102131913.1535-2-edgar.igles...@xilinx.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/Makefile.objs| 1 +
include/hw/arm/xlnx-versal.h
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/xilinx_zynq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xilinx_
From: Richard Henderson
When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, neither arm_div nor jazelle will be supported either.
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Message-id: 20181102102025.3546-1-richard.h
From: Philippe Mathieu-Daudé
Shannon Zhao's email at Huawei is bouncing: remove it.
X-Failed-Recipients: zhaoshengl...@huawei.com
** Address not found **
Your message wasn't delivered to zhaoshengl...@huawei.com because the
address couldn't be found, or is unable to receive mail.
N
From: Julia Suvorova
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova
Acked-by: Thomas Huth
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Peter Maydell
---
tests/boot-serial-test.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tests/boot-serial
From: Julia Suvorova
Wire up nRF51 UART in the corresponding SoC.
Signed-off-by: Julia Suvorova
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/arm/nrf51_soc.h | 3 +++
hw/arm/microbit.c | 2 ++
hw
Hi Peter,
On 2/11/18 12:52, Peter Maydell wrote:
Currently tests/acpi-test-data contains data files used by the
bios-tables-test, and configure individually symlinks those
data files into the build directory using a wildcard.
Using a wildcard like this is a bad idea, because if a new
data file
On 11/01/2018 03:14 AM, aditya bhardwaj wrote:
> Respected Sir,
>
> I followed https://wiki.qemu.org/Hosts/Linux to build qemu from source
> code. Its installed successfully with Ubuntu 16.04 VM created using VNC
> server.
>
> *Now, Could you please suggest me how to migrate VM from one host t
On 2/11/18 12:52, Peter Maydell wrote:
This patchset fixes a problem with our build infrastructure
that meant that MST's recent 'pci, pc, virtio' pullreq failed
tests.
Currently our configure script has a wildcard loop that creates
symlinks for every data file in tests/acpi-test-data from the
so
On 2 November 2018 at 17:38, Philippe Mathieu-Daudé wrote:
> Hi Peter,
>
> On 2/11/18 12:52, Peter Maydell wrote:
>> We can remove entirely the note in rebuild-expected-aml.sh
>> about copying any new data files, because now they will
>> be in the source directory, not the build directory, and
>>
On 11/02/2018 04:11 AM, Dongli Zhang wrote:
> Hi,
>
> Is there any way to emulate I/O timeout on qemu side (not fault injection in
> VM
> kernel) without modifying qemu source code?
>
> For instance, I would like to observe/study/debug the I/O timeout handling of
> nvme, scsi, virtio-blk (not
* Chris Friesen (chris.frie...@windriver.com) wrote:
> On 11/2/2018 10:55 AM, Alex Bennée wrote:
> >
> > Chris Friesen writes:
> > > Given the "not initialized" message on the console, I wasn't sure
> > > whether the kernel had even started yet.
> >
> > There will be a lot that happens between t
Hi Aleksandar,
On 1/11/18 12:06, Aleksandar Markovic wrote:
Hi, Fridrik,
I did some closer code inspection of R5900 in last few days, and I noticed some
sub-optimal implementation in the area where R5900-specific opcodes overlap
with the rest-of-MIPS-CPUs opcodes.
The right implementation sh
Ping for code review, please?
thanks
-- PMM
On 16 October 2018 at 10:37, Peter Maydell wrote:
> This small patchset fixes a couple of bugs in our ATS insn
> handling:
> * for faults reported to the 64-bit PAR we were not
>setting the S and PTW bits to indicate stage 2
>fault information
On 11/2/18 10:49 AM, John Snow wrote:
On 11/02/2018 04:11 AM, Dongli Zhang wrote:
Hi,
Is there any way to emulate I/O timeout on qemu side (not fault injection in VM
kernel) without modifying qemu source code?
For instance, I would like to observe/study/debug the I/O timeout handling of
nvme,
On 2/11/18 18:42, Peter Maydell wrote:
On 2 November 2018 at 17:38, Philippe Mathieu-Daudé wrote:
Hi Peter,
On 2/11/18 12:52, Peter Maydell wrote:
We can remove entirely the note in rebuild-expected-aml.sh
about copying any new data files, because now they will
be in the source directory, not
On 2/11/18 17:08, Fredrik Noring wrote:
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Aleksandar, if you are OK with this patch, can you add:
Fixes: 8d927f7cb4b
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
tar
On 2/11/18 17:08, Fredrik Noring wrote:
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Fixes: be9c42c90d1 (R5900-specific opcodes overlap with generic opcodes)
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translat
On 11/02/2018 01:55 PM, Marc Olson wrote:
> On 11/2/18 10:49 AM, John Snow wrote:
>> On 11/02/2018 04:11 AM, Dongli Zhang wrote:
>>> Hi,
>>>
>>> Is there any way to emulate I/O timeout on qemu side (not fault
>>> injection in VM
>>> kernel) without modifying qemu source code?
>>>
>>> For instanc
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