This patch extends the qemu-kvm state sync logic with support for
KVM_GET/SET_VCPU_EVENTS, giving access to yet missing SError exception.
And also it can support the exception state migration.
The SError exception states include SError pending state and ESR value,
the kvm_put/get_vcpu_events() wil
Update our kernel headers to mainline commit
815f0ddb346c196018d4d8f8f55c12b83da1de3f
(include/linux/compiler*.h: make compiler-*.h mutually exclusive)
Signed-off-by: Dongjiu Geng
---
include/standard-headers/linux/input.h | 9 +
linux-headers/asm-arm/kvm.h| 13 +
Support KVM_GET/SET_VCPU_EVENTS to get/set the SError exception state, and
support the state migration.
Now the VCPU event only includes the SError exception status, it can be
extended if needed. When do migration, If source machine has serror pending,
the target machine is also needed to pend th
I can't do bisect, but I have installed qemu version 3.0.50
(v3.0.0-614-g19b599f766-dirty) from git and this works fine.
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https://bugs.launchpad.net/bugs/1792193
Title:
AMD Athlon(tm)
Add the ability for the user to display help for a certain command.
Example: qemu-img create --help
What is printed is all the options available to this command and an example.
Signed-off-by: John Arbuckle
---
v2 changes:
Removed block of string comparison code for each command.
Added a help_fu
This is something we talked about in the context of enabling sve in
system mode. We don't want to replicate info between these two locations.
I'm not 100% happy with this, thus the RFC. In particular, there are
several places in id_isar0, id_isar2, and id_isar4 that expose micro-
architectural d
??? The assertion does fire for the old cpus; they may be existing bugs.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 36
1 file changed, 36 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 379d6a08a4..2b199845fc 100644
--- a/t
??? The assertion does fire for quite a lot of cpus,
??? but quite a few of them appear to be existing bugs.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 37 -
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/a
??? Test with -machine none -cpu foo.
??? The assertion does fire for quite a lot of cpus,
??? but quite a few of them appear to be existing bugs.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 45 +
1 file changed, 45 insertions(+)
diff --gi
These insns have been removed from the ISA, but are also not
present on some cpus with V7VE.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 +
linux-user/elfload.c | 3 ++-
target/arm/cpu.c | 10 ++
target/arm/translate.c | 4
4 files changed, 17 insertio
??? The assertion does fire for old cpus; they may be existing bugs.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c227044946..0151c278e8 100644
--- a/target/arm/cpu
??? The assertion does fire for the old cpus; they may be existing bugs.
??? Willfully provide a value for SWP_frac that matches our implementation.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 44
1 file changed, 44 insertions(+)
diff --g
??? The assertion does fire for the old cpus; they may be existing bugs.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a477e722af..379d6a08a4 100644
--- a
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0151c278e8..4fb3e0a9ea 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -992,6 +992,31 @@ static uint32_t resol
This is a prerequisite to removing the now-redundant
initializations from within the individual cpus.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 41 +++--
1 file changed, 7 insertions(+), 34 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1c51b9f631..a9724f3bb1 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1062,6 +1062,24 @@ static uint64_t resolve_id_a
Unlike the other id_sar registers, these contain post-v8.0 features
that are not included with any existing cpu models. They would be
enabled by -cpu max when we enable them for system mode.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 46 +
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a9724f3bb1..2ec71104c9 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1080,6 +1080,31 @@ static uint64_t res
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 49
1 file changed, 49 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4fb3e0a9ea..1c51b9f631 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1017,6 +1017,51 @@
Hi qemu-devel,
So we're using QEMU 2.12 for recent Android Emulator canaryies, and we're
seeing a lot of hangs on mac in flatview_translate in qemu 2.12.
What would be some pointers for diagnosing excessive I/O?
Especially, metrics to see if a system is on the verge of getting into main
loop spi
> On 14 Sep 2018, at 18:08, Paolo Bonzini wrote:
>
> On 14/09/2018 16:31, Liran Alon wrote:
>>> There is still a problem, however, in that the same input stream would
>>> be parsed differently depending on the kernel version. In particular,
>>> if in the future the maximum nested state size g
> On 15 Sep 2018, at 23:48, Liran Alon wrote:
>
>
>
>> On 14 Sep 2018, at 18:08, Paolo Bonzini wrote:
>>
>> On 14/09/2018 16:31, Liran Alon wrote:
There is still a problem, however, in that the same input stream would
be parsed differently depending on the kernel version. In par
I notice at least two commits in upstream QEMU that might impact this:
https://github.com/qemu/qemu/commit/ce3a9eaff4e5f29514dba35a001894cb7a238e07#diff-8bfe2ea13d8c6dab17a555f300ac2f66
https://github.com/qemu/qemu/commit/45641dba38f6f44c3ea44c2d1c37b31619276ce3#diff-a9288ea1a561573c7d3036de7d7048
On 15 September 2018 at 17:17, Richard Henderson
wrote:
> These insns have been removed from the ISA, but are also not
> present on some cpus with V7VE.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 1 +
> linux-user/elfload.c | 3 ++-
> target/arm/cpu.c | 10 ++
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