This is something we talked about in the context of enabling sve in system mode. We don't want to replicate info between these two locations.
I'm not 100% happy with this, thus the RFC. In particular, there are several places in id_isar0, id_isar2, and id_isar4 that expose micro- architectural details of the cpus. We cannot infer these values. We'll not be able to replicate the exact id values without additional changes. But I'll also note that with ARM_FEATURE_SWP, we're now at 60 feature bits, which means that we only have 4 remaining before we have to come up with another solution there. I do wonder if we should instead introduce some little inline functions to test each of the current feature bits, and once that's done convert those to test cpu->id_* bits. Most, but not all, of the feature bits would go away. We'd have the exact id values one would expect for a given cpu without having to replicate the info. Thoughts, one way or the other? r~ Richard Henderson (13): target/arm: Add ARM_FEATURE_SWP target/arm: Derive id_isar0 from features target/arm: Derive id_isar1 from features target/arm: Derive id_isar2 from features target/arm: Derive id_isar3 from features target/arm: Derive id_isar4 from features target/arm: Derive id_isar5 and id_isar6 from features target/arm: Derive id_pfr0 from features target/arm: Derive id_pfr1 from features target/arm: Derive id_aa64isar0 from features target/arm: Derive id_aa64isar1 from features target/arm: Derive id_aa64pfr0 from features target/arm: Remove assertions from resolve_id_regs target/arm/cpu.h | 1 + linux-user/elfload.c | 3 +- target/arm/cpu.c | 381 +++++++++++++++++++++++++++++++++++++++++ target/arm/translate.c | 4 + 4 files changed, 388 insertions(+), 1 deletion(-) -- 2.17.1
