Hi Chao,
Yes, virtio blk isn't supported by current COLO, you can try the "-drive
if=ide ".
Thanks
Zhang Chen
On Fri, Jul 27, 2018 at 12:53 PM, WANG Chao
wrote:
> Hi, Zhang Chen
>
> It seems virtio blk isn't working.
>
> I test coloft against https://github.com/zhangckid/qemu/tree/qemu
[ ... ]
>> +static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
>> +{
>> +MachineState *machine = MACHINE(spapr);
>> +sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
>> +int nr_irqs = smc->irq->nr_irqs;
>> +Error *local_err = NULL;
>> +
>> +/* Init
On 07/27/2018 12:36 AM, Benjamin Herrenschmidt wrote:
> On Thu, 2018-07-26 at 11:03 +0200, Cédric Le Goater wrote:
>> Ben,
>>
>> I have found out recently that the QEMU PowerNV could hang while accessing
>> the disk.
>>
>> The issue seems to be the phb3_msi_try_send() routine when called from
>>
>>> That said... shouldn't you filter our invalid or read-only regs before
>>> updating the cache?
>>
>> hmm, the current model relies on the fact that some registers have
>> their value implicitly updated. But I guess, we can dump which are
>> accessed and implement a default behavior for these. I
On Wed, 07/18 11:04, Alex Bennée wrote:
> When building on non-x86 systems the base system will be correct so if
> we avoid too many x86'isms in the install we can still use the image.
>
> Signed-off-by: Alex Bennée
> ---
> .../dockerfiles/{debian-amd64.docker => debian-host.docker} | 4 ++--
>
On Fri, 27 Jul 2018 15:27:24 +1000
David Gibson wrote:
> On Wed, Jul 25, 2018 at 04:45:26PM +0200, Greg Kurz wrote:
> > Commit b585395b655 fixed a regression introduced by some recent changes
> > in the XICS code, that was causing QEMU to crash instantly during CPU
> > hotplug with KVM. This is t
Le 27/07/2018 à 06:47, Richard Henderson a écrit :
> On 07/26/2018 10:39 AM, Laurent Vivier wrote:
>> Le 26/07/2018 à 19:15, Richard Henderson a écrit :
>>> On 07/25/2018 11:48 PM, Shivaprasad G Bhat wrote:
r11 is a volatile register on PPC as per calling conventions.
The safe_syscall cod
On 07/26/2018 05:09 PM, Juan Quintela wrote:
> Thomas Huth wrote:
>> On 17.07.2018 13:33, Juan Quintela wrote:
[...]
>>> @@ -347,8 +347,8 @@ check-qtest-ppc64-y += tests/usb-hcd-ohci-test$(EXESUF)
>>> gcov-files-ppc64-y += hw/usb/hcd-ohci.c
>>> check-qtest-ppc64-y += tests/usb-hcd-uhci-test$(EXE
On 07/27/2018 09:54 AM, Greg Kurz wrote:
> On Fri, 27 Jul 2018 15:27:24 +1000
> David Gibson wrote:
>
>> On Wed, Jul 25, 2018 at 04:45:26PM +0200, Greg Kurz wrote:
>>> Commit b585395b655 fixed a regression introduced by some recent changes
>>> in the XICS code, that was causing QEMU to crash inst
From: Prasanna Kumar Kalever
New versions of Glusters libgfapi.so have an updated glfs_ftruncate()
function that returns additional 'struct stat' structures to enable
advanced caching of attributes. This is useful for file servers, not so
much for QEMU. Nevertheless, the API has changed and needs
On Fri, 2018-07-27 at 09:16 +0200, Cédric Le Goater wrote:
> > I'd have to remember how PQ works on P8 ... my gut feeling is that we
> > should resend if P=1 but I'm no 100% certain.
>
> This is not exactly what the code does. To force a resend, it ignores
> P but if Q=1, it bails out without doi
On 07/27/2018 10:08 AM, Benjamin Herrenschmidt wrote:
> On Fri, 2018-07-27 at 15:32 +1000, David Gibson wrote:
>>
What is this pci bridge representing? I know PCI-e PHBs typically
have a pseudo P2P bridge right under them, but isn't that represnted
by the root complex above?
>>>
>>>
On Wed, 07/18 11:04, Alex Bennée wrote:
> Hi,
>
> Our existing support for docker is fairly x86 centric. While docker
> itself has support for multiple architectures not all architectures
> are equal. For example Debian only packages the widest range of
> cross-compilers in it's x86 images (althou
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Fam Zheng
---
tests/vm/Makefile.include | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/vm/Makefile.include b/tests/vm/Makefile.include
index 5daa2a3b73..9e19f8662f 100644
--- a/tests/vm/Makefile.include
+++ b/tests/vm/Makefile.inc
On Fri, 2018-07-27 at 10:25 +0200, Cédric Le Goater wrote:
> Each PHB creates a pci-bridge device and the PCI bus that comes with it.
> It makes things easier to define PCI devices.
>
> It is still quite complex ... Here is a sample :
>
> qemu-system-ppc64 -m 2G -machine powernv \
> -cpu POWE
On Fri, 27 Jul 2018 10:18:14 +0200
Thomas Huth wrote:
> On 07/27/2018 09:54 AM, Greg Kurz wrote:
> > On Fri, 27 Jul 2018 15:27:24 +1000
> > David Gibson wrote:
> >
> >> On Wed, Jul 25, 2018 at 04:45:26PM +0200, Greg Kurz wrote:
> >>> Commit b585395b655 fixed a regression introduced by some
Am 27.07.2018 um 08:53 hat Fam Zheng geschrieben:
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Fam Zheng
Thanks, applied to the block branch.
Kevin
On Thu, 06/21 09:26, Philippe Mathieu-Daudé wrote:
> Force one config to build 'out-of-tree' (object files and executables
> are created in a tree outside the project source code).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> I noticed various out-of-tree issue in the last 2 merge windows.
>
On 21 June 2018 at 13:26, Philippe Mathieu-Daudé wrote:
> Force one config to build 'out-of-tree' (object files and executables
> are created in a tree outside the project source code).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> I noticed various out-of-tree issue in the last 2 merge windo
On Fri, 07/27 14:53, Fam Zheng wrote:
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Fam Zheng
Actually cc qemu-sta...@nongnu.org
On 07/27/2018 10:43 AM, Benjamin Herrenschmidt wrote:
> On Fri, 2018-07-27 at 10:25 +0200, Cédric Le Goater wrote:
>> Each PHB creates a pci-bridge device and the PCI bus that comes with it.
>> It makes things easier to define PCI devices.
>>
>> It is still quite complex ... Here is a sample :
>>
On Tue, 07/24 16:47, Fam Zheng wrote:
> Something has locked /dev/null on my system (I still don't know what to do
> with
> the annoying incapability of lslocks, or more precisely /proc/locks, on
> inspecting OFD lock information), and as a result 226 cannot pass due to the
> unexpected image lock
On 26 July 2018 at 20:49, Daniel P. Berrangé wrote:
> On Thu, Jul 26, 2018 at 02:23:46PM +0200, Laszlo Ersek wrote:
>> On 07/26/18 13:13, Andrew Jones wrote:
>> > On Thu, Jul 26, 2018 at 12:56:22PM +0200, Ard Biesheuvel wrote:
>> >> On 26 July 2018 at 12:52, Peter Maydell wrote:
>> >>> On 26 July
On Fri, 2018-07-27 at 15:32 +1000, David Gibson wrote:
>
> > > What is this pci bridge representing? I know PCI-e PHBs typically
> > > have a pseudo P2P bridge right under them, but isn't that represnted
> > > by the root complex above?
> >
> > This is the legacy pci bridge under the pcie bus.
>
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 23 ++-
Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
a VMState.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 42b946c
Implement the maintenance interrupt generation that is part of the GICv2
virtualization extensions.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 97 +++
1 file changed, 97 insertions(+)
diff --git a/hw/intc/arm_gic.c b
Add the register definitions for the virtual interface of the GICv2.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/gic_internal.h | 65 ++
1 file changed, 65 insertions(+)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
in
Implement virtualization extensions in the gic_deactivate_irq() and
gic_complete_irq() functions.
When the guest writes an invalid vIRQ to V_EOIR or V_DIR, since the
GICv2 specification is not entirely clear here, we adopt the behaviour
observed on real hardware:
* When V_CTRL.EOIMode is false (
Add some helper macros and functions related to the virtualization
extensions to gic_internal.h.
The GICH_LR_* macros help extracting specific fields of a list register
value. The only tricky one is the priority field as only the MSB are
stored. The value must be shifted accordingly to obtain the
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 61 +++
1 file chan
v2:
- Add VMSTATE_UINT16_SUB_ARRAY to vmstate.h
- Keep backward compatibility on the GIC VMState by storing vCPUs
state in the virt VMState subsection.
- Use h_apr to store APR value for vCPUs, instead of increasing apr 2D
array. This adds a little complexity to the implementation (a
An access to the CPU interface is non-secure if the current GIC instance
implements the security extensions, and the memory access is actually
non-secure. Until then, it was checked with tests such as
if (s->security_extn && !attrs.secure) { ... }
in various places of the CPU interface code.
Wit
Implement virtualization extensions in gic_activate_irq() and
gic_drop_prio() and in gic_get_prio_from_apr_bits() called by
gic_drop_prio().
When the current CPU is a vCPU:
- Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt
counterparts,
- the vCPU APR is stored in the vir
Add the gic_update_virt() function to update the vCPU interface states
and raise vIRQ and vFIQ as needed. This commit renames gic_update() to
gic_update_internal() and generalizes it to handle both cases, with a
`virt' parameter to track whether we are updating the CPU or vCPU
interfaces.
The main
Implement virtualization extensions in the gic_acknowledge_irq()
function. This function changes the state of the highest priority IRQ
from pending to active.
When the current CPU is a vCPU, modifying the state of an IRQ modifies
the corresponding LR entry. However if we clear the pending flag bef
This commit improve the way the GIC is realized and connected in the
ZynqMP SoC. The security extensions are enabled only if requested in the
machine state. The same goes for the virtualization extensions.
All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ,
vIRQ and vFIQ. The mis
Implement the read and write functions for the virtual interface of the
virtualization extensions in the GICv2.
One mirror region per CPU is also created, which maps to that specific
CPU id. This is required by the GIC architecture specification.
Signed-off-by: Luc Michel
Reviewed-by: Peter Mayd
Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 20 +++-
1
Add support for GICv2 virtualization extensions by mapping the necessary
I/O regions and connecting the maintenance IRQ lines.
Declare those additions in the device tree and in the ACPI tables.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/arm/virt-acpi-build.c | 6 +++--
hw/arm
Add the read/write functions to handle accesses to the vCPU interface.
Those accesses are forwarded to the real CPU interface, with the CPU id
being converted to the corresponding vCPU id (vCPU id = CPU id +
GIC_NCPU).
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 37
Add some traces to the ARM GIC to catch register accesses (distributor,
(v)cpu interface and virtual interface), and to take into account
virtualization extensions (print `vcpu` instead of `cpu` when needed).
Also add some virtualization extensions specific traces: LR updating
and maintenance IRQ
Add some helper functions to gic_internal.h to get or change the state
of an IRQ. When the current CPU is not a vCPU, the call is forwarded to
the GIC distributor. Otherwise, it acts on the list register matching
the IRQ in the current CPU virtual interface.
gic_clear_active can have a side effect
When use cluster_size=1M qcow2 newly created to test "32k rand write" in the
VM,We get low performance within VM。But there are huge “write” requests in HOST
which falls into qemu stack of"perform_cow".
We found three scene to use cow.
1. write cluster have snapshot
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off-by: Luc Michel
Revie
Add the necessary parts of the virtualization extensions state to the
GIC state. We choose to increase the size of the CPU interfaces state to
add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way,
we'll be able to reuse most of the CPU interface code for the vCPUs.
The only except
Am 27.07.2018 um 11:24 hat Fam Zheng geschrieben:
> On Tue, 07/24 16:47, Fam Zheng wrote:
> > Something has locked /dev/null on my system (I still don't know what to do
> > with
> > the annoying incapability of lslocks, or more precisely /proc/locks, on
> > inspecting OFD lock information), and as
Am 27.07.2018 um 05:33 hat Fam Zheng geschrieben:
> Kevin pointed out that both glibc and kernel provides a slow fallback of
> copy_file_range which hurts thin provisioning. This is particularly true for
> thin LVs, because host_device driver cannot get allocation info from the
> volume, and copy_f
On 25/07/18 14:03, Paolo Bonzini wrote:
It's possible as long as you don't add any members. You can add a new
const char* argument to ide_bus_new, and call it from cmd646.
However, another possibility is to implement the FWPathProvider
interface in the sun4u machine type. See hw/ppc/spapr.c f
On 27/07/2018 12:43, Mark Cave-Ayland wrote:
> The issue here seems to be that according to "info qtree" there is
> *always* an ide-cd device plugged into the location equivalent to that
> of -cdrom, and so with the above command QEMU ends up adding a second
> ide-cd device to the ide.1 bus which c
On 27/07/18 11:47, Paolo Bonzini wrote:
On 27/07/2018 12:43, Mark Cave-Ayland wrote:
The issue here seems to be that according to "info qtree" there is
*always* an ide-cd device plugged into the location equivalent to that
of -cdrom, and so with the above command QEMU ends up adding a second
id
On 07/27/2018 11:00 AM, Greg Kurz wrote:
> On Fri, 27 Jul 2018 10:18:14 +0200
> Thomas Huth wrote:
>
>> On 07/27/2018 09:54 AM, Greg Kurz wrote:
>>> On Fri, 27 Jul 2018 15:27:24 +1000
>>> David Gibson wrote:
>>>
On Wed, Jul 25, 2018 at 04:45:26PM +0200, Greg Kurz wrote:
> Commit b5
I believe this same bug affects me on Linux Mint 18.3 Sylvia which is based on
Ubuntu Xenial.
The suggestion from #12 helped me. Thank you @bruno-clisp!
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/
The vmstate save/load code insists that subsections of a VMState must
have names which include their parent VMState's name as a leading
substring. Unfortunately it neither documents this nor checks it on
device init or state save, but instead fails state load with a
confusing error message ("Missi
This patchset fixes a couple of bugs I found in the v8M
and MPS board code:
* migration wasn't working because of an incorrect
subsection name in the NVIC vmstate
* the timer1 IRQ line was miswired in the iotkit
Neither of these are strictly speaking regressions
from 2.12, but because they're
A cut-and-paste error meant we were incorrectly wiring up the timer1
IRQ to IRQ3. IRQ3 is the interrupt for timer0 -- move timer0 to
IRQ4 where it belongs.
Signed-off-by: Peter Maydell
---
hw/arm/iotkit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/iotkit.c b/hw/ar
On Thu, Jul 26, 2018 at 06:55:44PM +0200, Halil Pasic wrote:
> Sorry I did not have any time for this last days. And this
> to make it worse this is a follow up to something that was
> half a year ago. That means I have to re-familiarize myself
> with the topic.
>
> If I don't get around to answer
On Fri, 27 Jul 2018 13:25:33 +0200
Thomas Huth wrote:
> On 07/27/2018 11:00 AM, Greg Kurz wrote:
> > On Fri, 27 Jul 2018 10:18:14 +0200
> > Thomas Huth wrote:
> >
> >> On 07/27/2018 09:54 AM, Greg Kurz wrote:
> >>> On Fri, 27 Jul 2018 15:27:24 +1000
> >>> David Gibson wrote:
> >>>
> >
On 07/27/2018 08:38 AM, Peter Maydell wrote:
> A cut-and-paste error meant we were incorrectly wiring up the timer1
> IRQ to IRQ3. IRQ3 is the interrupt for timer0 -- move timer0 to
> IRQ4 where it belongs.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
(ARM-ECM-0601256 Ta
On Fri, Jul 27, 2018 at 6:29 PM Kevin Wolf wrote:
>
> Am 27.07.2018 um 05:33 hat Fam Zheng geschrieben:
> > Kevin pointed out that both glibc and kernel provides a slow fallback of
> > copy_file_range which hurts thin provisioning. This is particularly true for
> > thin LVs, because host_device dr
On Fri, Jul 27, 2018 at 6:04 PM Kevin Wolf wrote:
>
> Am 27.07.2018 um 11:24 hat Fam Zheng geschrieben:
> > On Tue, 07/24 16:47, Fam Zheng wrote:
> > > Something has locked /dev/null on my system (I still don't know what to
> > > do with
> > > the annoying incapability of lslocks, or more precise
On 07/27/2018 05:34 AM, Fam Zheng wrote:
> Suggested-by: Philippe Mathieu-Daudé
> Signed-off-by: Fam Zheng
Thanks
Reviewed-by: Philippe Mathieu-Daudé
> ---
> tests/vm/Makefile.include | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/tests/vm/Makefile.include b/tests/vm/Makefile.in
From: "Dr. David Alan Gilbert"
Fix missing terminator in VMStateDescription
Fixes: d811d61fbc6ca5f2be2185fd7cfa916e7ba613ce
Signed-off-by: Dr. David Alan Gilbert
---
hw/misc/macio/pmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
index e246b0fd
On 27/07/18 02:10, David Gibson wrote:
Right, I agree. Migrating shouldn't advance the time if we've already
explicitly stopped. But it's not really clear how to accomplish that
:/.
This topic is obviously of interest to me because it relates to various
discussions in the past relating to m
On 27/07/18 13:31, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
Fix missing terminator in VMStateDescription
Fixes: d811d61fbc6ca5f2be2185fd7cfa916e7ba613ce
Signed-off-by: Dr. David Alan Gilbert
---
hw/misc/macio/pmu.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
On Fri, Jul 13, 2018 at 03:48:27PM +0800, FelixYao wrote:
> Hi all:
>
> Max threads in thread pool is fixed at 64 before which is not
> propriate in some situations. For public cloud environment,
> there are lots of VMs in one host machine. We should limit the worker thread
> numbers for each mach
On Mon, Jul 16, 2018 at 12:47:43PM +0200, Steffen Görtz wrote:
> Signed-off-by: Steffen Görtz
> ---
> Changes in v2:
>- Only call QEMU GPIO update handlers if value changes
>- Code style changes
>- Removed unused includes
>
> hw/gpio/Makefile.objs| 1 +
> hw/gpio/nrf51_gpi
On 07/27/2018 06:54 AM, Luc Michel wrote:
> Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
> a VMState.
>
> Signed-off-by: Luc Michel
> Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/migration/vmstate.h | 3 +++
> 1 file changed, 3 in
On 07/27/2018 06:54 AM, Luc Michel wrote:
> An access to the CPU interface is non-secure if the current GIC instance
> implements the security extensions, and the memory access is actually
> non-secure. Until then, it was checked with tests such as
> if (s->security_extn && !attrs.secure) { ... }
On 07/27/2018 06:54 AM, Luc Michel wrote:
> Add some helper functions to gic_internal.h to get or change the state
> of an IRQ. When the current CPU is not a vCPU, the call is forwarded to
> the GIC distributor. Otherwise, it acts on the list register matching
> the IRQ in the current CPU virtual i
On Fri, Jul 27, 2018 at 11:18:26AM +0100, Stefan Hajnoczi wrote:
> On Fri, Jul 13, 2018 at 03:48:27PM +0800, FelixYao wrote:
> > Hi all:
> >
> > Max threads in thread pool is fixed at 64 before which is not
> > propriate in some situations. For public cloud environment,
> > there are lots of VMs i
On Wed, Jul 18, 2018 at 03:47:56PM +0800, junyan...@gmx.com wrote:
> From: Junyan He
>
> QEMU writes to vNVDIMM backends in the vNVDIMM label emulation and live
> migration.
> If the backend is on the persistent memory, QEMU needs to take proper
> operations to
> ensure its writes persistent on
On 27/07/2018 14:31, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Fix missing terminator in VMStateDescription
>
> Fixes: d811d61fbc6ca5f2be2185fd7cfa916e7ba613ce
> Signed-off-by: Dr. David Alan Gilbert
> ---
> hw/misc/macio/pmu.c | 1 +
> 1 file changed, 1 insertio
On Wed, Jul 18, 2018 at 11:13:18PM +0200, Emanuele wrote:
>
>
> On 07/18/2018 09:28 PM, Paolo Bonzini wrote:
> > On 18/07/2018 16:23, Stefan Hajnoczi wrote:
> > > > > > +struct QOSGraphObject {
> > > > > > +/* for produces, returns void * */
> > > > > > +QOSGetDriver get_driver;
> > > > >
On Wed, 25 Jul 2018 11:12:33 +0200
David Hildenbrand wrote:
> The "max" CPU model behaves like "-cpu host" when KVM is enabled, and like
> a CPU with the maximum possible feature set when TCG is enabled.
>
> While the "host" model can not be used under TCG ("kvm_required"), the
> "max" model can
On Thu, Jul 19, 2018 at 08:42:05AM +0200, Markus Armbruster wrote:
> Peter Maydell writes:
>
> > On 17 July 2018 at 20:50, Eduardo Habkost wrote:
> Instead, we've repeatedly wasted time on debating which kind of ugly we
> hate less, and all we can show for our troubles is CODING_STYLE. Which
>
On Fri, Jul 27, 2018 at 01:49:17PM +0100, Stefan Hajnoczi wrote:
> On Wed, Jul 18, 2018 at 03:47:56PM +0800, junyan...@gmx.com wrote:
> > From: Junyan He
> >
> > QEMU writes to vNVDIMM backends in the vNVDIMM label emulation and live
> > migration.
> > If the backend is on the persistent memory,
On Fri, Jul 27, 2018 at 02:03:17PM +0100, Stefan Hajnoczi wrote:
> On Thu, Jul 19, 2018 at 08:42:05AM +0200, Markus Armbruster wrote:
> > Peter Maydell writes:
> >
> > > On 17 July 2018 at 20:50, Eduardo Habkost wrote:
> > Instead, we've repeatedly wasted time on debating which kind of ugly we
>
On 27 July 2018 at 14:03, Stefan Hajnoczi wrote:
> On Thu, Jul 19, 2018 at 08:42:05AM +0200, Markus Armbruster wrote:
>> That the code shows anything resembling consistency at all is a
>> testament to humanity's yearning for order within a chaotic world.
>
> Going back to something concrete after
On 07/27/2018 01:22 AM, Markus Armbruster wrote:
Signed-off-by: Markus Armbruster
---
qobject/qstring.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Eric Blake
diff --git a/qobject/qstring.c b/qobject/qstring.c
index 18b8eb82f8..1bb7784a88 100644
--- a/qobject
On 07/27/2018 03:19 AM, Niels de Vos wrote:
From: Prasanna Kumar Kalever
New versions of Glusters libgfapi.so have an updated glfs_ftruncate()
s/Glusters/Gluster's/
function that returns additional 'struct stat' structures to enable
advanced caching of attributes. This is useful for file se
Since 86f0a186d6f the TYPE_ARM_HOST_CPU is only compiled when CONFIG_KVM
is enabled.
Remove the now redundant special-case introduced in a96c0514ab7, to avoid:
$ qemu-system-aarch64 -machine virt -cpu \? | fgrep host
host
host (only available in KVM mode)
Signed-off-by: Philippe Mathieu-Da
On 07/27/2018 03:19 AM, Niels de Vos wrote:
From: Prasanna Kumar Kalever
New versions of Glusters libgfapi.so have an updated glfs_ftruncate()
function that returns additional 'struct stat' structures to enable
advanced caching of attributes. This is useful for file servers, not so
much for QEM
On Mon, Jul 23, 2018 at 12:43:42PM +0200, Emanuele Giuseppe Esposito wrote:
> The current layout of struct QPCIBusPC provides only one field,
> QPCIBus bus, so passing a NULL pointer to qpci_free_pc()
> makes container_of(NULL, QPCIBusPC, bus)
> returning 0 (NULL), that is correctly handled by g_fr
On Mon, Jul 23, 2018 at 12:42:02PM -0400, Farhan Ali wrote:
>
>
> On 07/23/2018 12:30 PM, Stefan Hajnoczi wrote:
> > On Fri, Jul 20, 2018 at 03:11:14PM -0400, Farhan Ali wrote:
> > > I am seeing another issue pop up, in a different test. Even though it's a
> > > different assertion, it might be r
On Wed, Jul 25, 2018 at 11:21:03AM +0200, Markus Armbruster wrote:
> liujunjie writes:
> > diff --git a/qobject/qstring.c b/qobject/qstring.c
> > index afca54b..18b8eb8 100644
> > --- a/qobject/qstring.c
> > +++ b/qobject/qstring.c
> > @@ -37,7 +37,7 @@ size_t qstring_get_length(const QString *qst
On Fri, Jul 27, 2018 at 3:15 PM Fam Zheng wrote:
> On Fri, Jul 27, 2018 at 6:29 PM Kevin Wolf wrote:
> >
> > Am 27.07.2018 um 05:33 hat Fam Zheng geschrieben:
> > > Kevin pointed out that both glibc and kernel provides a slow fallback
> of
> > > copy_file_range which hurts thin provisioning. Thi
* Mark Cave-Ayland (mark.cave-ayl...@ilande.co.uk) wrote:
> On 27/07/18 13:31, Dr. David Alan Gilbert (git) wrote:
>
> > From: "Dr. David Alan Gilbert"
> >
> > Fix missing terminator in VMStateDescription
> >
> > Fixes: d811d61fbc6ca5f2be2185fd7cfa916e7ba613ce
> > Signed-off-by: Dr. David Alan
From: "Dr. David Alan Gilbert"
The 'vmstate_smmuv3_queue' is missing the end-of-list marker.
Fixes: 10a83cb9887
Signed-off-by: Dr. David Alan Gilbert
---
hw/arm/smmuv3.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 39fbcbf577..40a86c1895 100644
Hi, Zhang Chen
It seems virtio blk isn't working.
I test coloft against https://github.com/zhangckid/qemu/tree/qemu-colo-
18jul22, got the following error on very early stage:
On primary:
qemu-system-x86_64: Can't receive COLO message: Input/output error
On secondary:
qemu-system-x86_64: block.
Yes, ide works.
And by the way, how about other virtio devices or vhost-xxx? Are they
supported by COLO?
Do you know the working set of devices? My preliminary test shows ide,
e1000, rtl8139 work.
Thanks
WANG Chao
--
You received this bug notification because you are a member of qemu-
devel-ml
Kevin Wolf (3):
block/qapi: Add 'qdev' field to query-blockstats result
block/qapi: Include anonymous BBs in query-blockstats
qemu-iotests: Test query-blockstats with -drive and -blockdev
qapi/block-core.json | 5 ++-
block/qapi.c | 16 ++-
tests/qemu-iotests/227
Make sure that query-blockstats returns information for every
BlockBackend that is named or attached to a device model (or both).
Signed-off-by: Kevin Wolf
---
tests/qemu-iotests/227 | 101 +
tests/qemu-iotests/227.out | 42 +++
te
Consistent with query-block, query-blockstats should not only include
named BlockBackends, but also those that are anonmyous, but belong to a
device model.
Signed-off-by: Kevin Wolf
---
block/qapi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/block/qapi.c b/block/qap
Like for query-block, the client needs to identify which BlockBackend
the returned data is for. Anonymous BlockBackends are identified by the
device model they are attached to. Add a 'qdev' field that contains the
qdev ID or QOM path of the attached device model.
Signed-off-by: Kevin Wolf
---
qa
Clock gating and reset of uart0 and uart1 is controlled by
UART_CLK_CTRL and UART_RST_CTRL.
Uart0 and uart1 links are kept in properties to allow taking action.
The CLKACT bit in UART_CLK_CTRL is used to driver the clock gating.
In order to implement the reset behavior, which can be hold: when
re
The default methods are overriden to add the activation/deactivation
of the memory regions according to the gating state: Regions are
enabled only when powered and clocked.
As powering-up triggers a reset call, memory regions should
be reset in specialized sysbus devices.
Signed-off-by: Damien Hed
Add the link between the clock controller _slcr_ and the two
uarts _uart0_ and _uart1_ so that the controller can do the gating.
Signed-off-by: Damien Hedde
---
hw/arm/xilinx_zynq.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/h
Only discard input characters when unpowered/unclocked.
As it is a sysbus device, mmio are already disabled when unpowered
or unclocked.
Signed-off-by: Damien Hedde
---
hw/char/cadence_uart.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/hw/char/ca
Add two boolean new fields _powered_ and _clocked_ to hold the gating
state. Also add methods to act on each gating change.
The power/clock gating is controlled by 2 functions *device_set_power* and
*device_set_clock*.
Add a default behavior to do a device_reset at power-up.
Signed-off-by: Damien
1 - 100 of 193 matches
Mail list logo
