Thomas Huth writes:
> We've never documented this option in our qemu-doc, so unless the users
> used qemu-kvm before, they never should never have been aware of this
You're serious about "never", aren't you? ;->
> option. It's been marked as deprecated in the source code since a long
s/since/
On 05/03/2018 08:21 AM, David Gibson wrote:
> There are some fields in the cpu state which need to be updated when the
> LPCR register is changed, which is done by ppc_hash64_update_rmls() and
> ppc_hash64_update_vrma(). Code which alters env->spr[SPR_LPCR] needs to
> call them afterwards to make
Thomas Huth writes:
> Deprecated since the beginning when it was added for compatibility with
> the ancient qemu-kvm fork of QEMU, and it even printed out the deprecation
> warning since right from the start (i.e. QEMU v1.3.0), so it's really time
> to remove this now.
>
> Signed-off-by: Thomas H
Thomas Huth writes:
> We've never documented this option in our qemu-doc, so unless the users
> used qemu-kvm before, they never should never have been aware of this
> option. It's been marked as deprecated in the source code since a long
> time already, and officially marked as deprecated in the
Current POWER cpus allow for a VRMA, a special mapping which describes a
guest's view of memory when in real mode (MMU off, from the guest's point
of view). Older cpus didn't have that which meant that to support a guest
a special host-contiguous region of memory was needed to give the guest its
R
On Fri, Apr 27, 2018 at 01:53:35PM +0800, Jason Wang wrote:
[...]
> > +int it_tree_remove(ITTree *tree, ITValue start, ITValue end)
> > +{
> > +ITRange range = { .start = start, .end = end }, *overlap, and;
> > +GTree *gtree;
> > +
> > +g_assert(tree);
> > +
> > +gtree = tree->tre
On 05/03/2018 08:21 AM, David Gibson wrote:
> This makes several minor cleanups to these functions:
> * Follow usual convention of an early exit on error, rather than having
> most of the body in an if
> * Clearer naming of cpu and cpu_. Now callcpu is the cpu from which the
> RTAS cal
On 05/03/2018 08:21 AM, David Gibson wrote:
> rtas_start_cpu() calls spapr_cpu_update_tb_offset() and
> spapr_cpu_set_endianness() to initialize certain things in the new cpu's
> state. This is the only caller of those helpers, and they're each only
> a few lines long, so we might as well just fol
On 03.05.2018 09:10, David Gibson wrote:
> Current POWER cpus allow for a VRMA, a special mapping which describes a
> guest's view of memory when in real mode (MMU off, from the guest's point
> of view). Older cpus didn't have that which meant that to support a guest
> a special host-contiguous re
On 2018年05月03日 14:04, Peter Xu wrote:
IMHO the guest can't really detect this, but it'll found that the
device is not working functionally if it's doing something like what
Jason has mentioned.
Actually now I have had an idea if we really want to live well even
with Jason's example: maybe we'l
On 2018年05月03日 15:10, Peter Xu wrote:
On Fri, Apr 27, 2018 at 01:53:35PM +0800, Jason Wang wrote:
[...]
+int it_tree_remove(ITTree *tree, ITValue start, ITValue end)
+{
+ITRange range = { .start = start, .end = end }, *overlap, and;
+GTree *gtree;
+
+g_assert(tree);
+
+gtree
On Wed, May 02, 2018 at 09:02:00AM +0100, Daniel P. Berrangé wrote:
> On Wed, May 02, 2018 at 09:44:03AM +0200, Gerd Hoffmann wrote:
> > Hi,
> >
> > > > If we bump the major version each year anyway, why not go the whole way
> > > > and use 2018.1, 2018.2, ... (or even .)? The nice thing
> > > >
On 05/03/2018 08:21 AM, David Gibson wrote:
> There are several places in spapr_hcall.c where we need to update the LPCR
> value on all CPUs. We do this with the set_spr() helper. That's not
> really correct because this directly sets the SPR value, without going
> through the ppc_store_lpcr() he
On 05/03/2018 08:21 AM, David Gibson wrote:
> In cpu_ppc_set_papr() the UPRT and GTSE bits of the LPCR default value are
> initialized based on on ppc64_radix_guest(). Which seems reasonable,
> except that ppc64_radix_guest() is based on spapr->patb_entry which is
> only set up in spapr_machine_re
On Thu, May 03, 2018 at 03:20:11PM +0800, Jason Wang wrote:
>
>
> On 2018年05月03日 14:04, Peter Xu wrote:
> > IMHO the guest can't really detect this, but it'll found that the
> > device is not working functionally if it's doing something like what
> > Jason has mentioned.
> >
> > Actually now I h
On Thu, May 03, 2018 at 03:21:13PM +0800, Jason Wang wrote:
>
>
> On 2018年05月03日 15:10, Peter Xu wrote:
> > On Fri, Apr 27, 2018 at 01:53:35PM +0800, Jason Wang wrote:
> >
> > [...]
> >
> > > > +int it_tree_remove(ITTree *tree, ITValue start, ITValue end)
> > > > +{
> > > > +ITRange range =
On 05/03/2018 08:21 AM, David Gibson wrote:
> cpu_ppc_set_papr() does several things:
> 1) it sets up the virtual hypervisor interface
> 2) it prevents the cpu from ever entering hypervisor mode
> 3) it tells KVM that we're emulating a cpu in PAPR mode
> and 4) it configures the LPCR an
On Thu, May 03, 2018 at 09:06:42AM +0200, Cédric Le Goater wrote:
> On 05/03/2018 08:21 AM, David Gibson wrote:
> > There are some fields in the cpu state which need to be updated when the
> > LPCR register is changed, which is done by ppc_hash64_update_rmls() and
> > ppc_hash64_update_vrma(). Cod
On Fri, 04/27 17:23, Stefan Hajnoczi wrote:
> v2:
> * Add comment on !__linux__ situation [Fam]
> * Add file-posix.c x-check-cache-dropped=on|off option [DaveG, Kevin]
Reviewed-by: Fam Zheng
On 2018年05月03日 15:28, Peter Xu wrote:
On Thu, May 03, 2018 at 03:20:11PM +0800, Jason Wang wrote:
On 2018年05月03日 14:04, Peter Xu wrote:
IMHO the guest can't really detect this, but it'll found that the
device is not working functionally if it's doing something like what
Jason has mentioned.
On 05/03/2018 08:21 AM, David Gibson wrote:
> To prevent spurious wakeups on cpus that are supposed to be disabled, we
> need to clear the LPCR bits which control certain wakeup events.
> spapr_cpu_reset() has separate cases here for boot and non-boot (initially
> inactive) cpus. rtas_start_cpu()
On Thu, May 03, 2018 at 03:43:35PM +0800, Jason Wang wrote:
>
>
> On 2018年05月03日 15:28, Peter Xu wrote:
> > On Thu, May 03, 2018 at 03:20:11PM +0800, Jason Wang wrote:
> > >
> > > On 2018年05月03日 14:04, Peter Xu wrote:
> > > > IMHO the guest can't really detect this, but it'll found that the
> >
On 05/03/2018 08:36 AM, David Gibson wrote:
> On Thu, May 03, 2018 at 07:52:32AM +0200, Cédric Le Goater wrote:
>> On 05/03/2018 02:58 AM, David Gibson wrote:
>>> On Tue, Apr 24, 2018 at 02:41:47PM +0200, Cédric Le Goater wrote:
On 04/24/2018 02:03 PM, Cédric Le Goater wrote:
>> +hwaddr pp
From: Xiao Guangrong
QEMU 2.13 enables strict check for compression & decompression to
make the migration more robust, that depends on the source to fix
the internal design which triggers the unexpected error conditions
To make it work for migrating old version QEMU to 2.13 QEMU, we
introduce th
On 05/03/2018 04:06 PM, guangrong.x...@gmail.com wrote:
From: Xiao Guangrong
QEMU 2.13 enables strict check for compression & decompression to
make the migration more robust, that depends on the source to fix
the internal design which triggers the unexpected error conditions
To make it work fo
On Thu, May 03, 2018 at 04:06:11PM +0800, guangrong.x...@gmail.com wrote:
> From: Xiao Guangrong
>
> QEMU 2.13 enables strict check for compression & decompression to
> make the migration more robust, that depends on the source to fix
> the internal design which triggers the unexpected error cond
Max Reitz writes:
> (Sorry, Markus, sorry, Kevin, if this series makes you angry.)
Anger? Nah. Gallows humor :)
> The subject says it all, I think. The original issue I was assigned to
> solve is this:
>
> $ ./qemu-img info --image-opts driver=null-co,size=42
> image: json:{"driver":
02.05.2018 00:13, Eric Blake wrote:
The NBD spec is clarifying [1] that a server may want to advertise
different limits for READ/WRITE (in our case, 32M) than for
TRIM/ZERO (in our case, nearly 4G). Add the constants and name
lookups for new NBD_INFO_ fields used during handshake to convey
this
02.05.2018 00:13, Eric Blake wrote:
The next patch will ask the server for more items of NBD_INFO.
However, the server is free to respond with INFO items in a
different order than what we request, so performing any sanity
checks about constraints that occur between multiple INFO items
must be don
On 05/03/2018 04:29 AM, David Gibson wrote:
> On Thu, Apr 26, 2018 at 10:17:13AM +0200, Cédric Le Goater wrote:
>> On 04/26/2018 07:36 AM, David Gibson wrote:
>>> On Thu, Apr 19, 2018 at 07:40:09PM +0200, Cédric Le Goater wrote:
On 04/16/2018 06:26 AM, David Gibson wrote:
> On Thu, Apr 12,
Hello,
This short series implements a minimal definition of the Nordic
Semiconductor nRF51, a Cortex-M0 ARM SoC, and the BBC micro:bit, a
machine that will use this SoC.
This work will serve as the base for our Google Summer of Code and
Outreachy interns who will work on implementing a number of
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
plus other common ARM SoC peripherals.
http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
This defines a basic model of the CPU and memory, with no peripherals
implemented at this stage.
Signed-off-by: Joel Stanley
---
This adds the base for a machine model of the BBC micro:bit:
https://en.wikipedia.org/wiki/Micro_Bit
This is a system with a nRF51 SoC containing the main processor, with
various peripherals on board.
Signed-off-by: Joel Stanley
---
hw/arm/Makefile.objs | 2 +-
hw/arm/microbit.c| 33 +++
On Thu, May 03, 2018 at 08:21:00AM +0100, Stefan Hajnoczi wrote:
> On Wed, May 02, 2018 at 09:02:00AM +0100, Daniel P. Berrangé wrote:
> > On Wed, May 02, 2018 at 09:44:03AM +0200, Gerd Hoffmann wrote:
> > > Hi,
> > >
> > > > > If we bump the major version each year anyway, why not go the whole
On Thu, May 03, 2018 at 09:25:45AM +0800, Fam Zheng wrote:
> HMP "info usernet" has been available but it isn't ideal for programmed
> use cases. This closes the gap in QMP by adding a counterpart
> "query-usernet" command. It is basically translated from
> the HMP slirp_connection_info() loop, whi
02.05.2018 00:13, Eric Blake wrote:
The NBD spec is clarifying [1] that a server may want to advertise
different limits for READ/WRITE (in our case, 32M) than for
TRIM/ZERO (in our case, nearly 4G). Implement the client
side support for these alternate limits, by always requesting
the new inform
Hi,
This series failed docker-build@min-glib build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180503090532.3113-1-j...@jms.id.au
Subject: [Qemu-devel] [PATCH 0/2] arm: Add nRF51 So
From: "Edgar E. Iglesias"
Use bool instead of int to represent flags.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/transl
From: "Edgar E. Iglesias"
Use bool instead of unsigned int to represent flags.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/t
From: "Edgar E. Iglesias"
This series adds support for Extended Addressing to our MicroBlaze
models. It adds both the non-MMU load/store EA and the extended MMU
addressing.
There are several ways to implement this but since there are further
64-bit extensions in the pipe, I've chosen to convert
On 3 May 2018 at 10:05, Joel Stanley wrote:
> The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
> plus other common ARM SoC peripherals.
>
> http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
>
> This defines a basic model of the CPU and memory, with no peripherals
> imp
From: "Edgar E. Iglesias"
Use bool instead of unsigned int to represent flags.
Also, use extract32 instead of open coding the bit extract.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
dif
From: "Edgar E. Iglesias"
Conditionalize setting of PVR11_USE_MMU on the use_mmu
CPU property, otherwise we may incorrectly advertise an
MMU via PVR when the core in fact has none.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
From: "Edgar E. Iglesias"
Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index a9f4ca93e3.
From: "Edgar E. Iglesias"
Correct special register array sizes.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 4 ++--
target/microblaze/translate.c | 5 ++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
From: "Edgar E. Iglesias"
Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when
TCGv_i32 should be used.
This is in preparation for adding 64bit addressing support.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/helper.c| 2 +-
target/microblaze/tra
From: "Edgar E. Iglesias"
Today, when running QEMU in linux-user or with boards that don't
select a specific CPU version, we treat it as an invalid version
and log a message.
Instead, if no specific version was selected, fallback to our
latest CPU version.
Signed-off-by: Edgar E. Iglesias
---
From: "Edgar E. Iglesias"
Implement MFSE EAR to enable access to the upper part of EAR.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
i
From: "Edgar E. Iglesias"
Use TCGv for load/store addresses, allowing for future
computation of 64-bit load/store address.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 2 +-
target/microblaze/helper.h| 4 +--
target/microblaze/op_helper.c |
From: "Edgar E. Iglesias"
Correct the PVR array size, there are 13 PVR registers.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 994496515f..2304c24b7d 1006
From: "Edgar E. Iglesias"
Name special registers we support.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index c971fe3b72..57cd00ab3e 100
From: "Edgar E. Iglesias"
Add explicit handling for MMU_R_TLBX and log accesses to
invalid MMU registers. We can now remove the state for
all regs but PID, ZPR and TLBX (0 - 2).
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/mmu.c | 7 +--
target/microblaze/mmu.h | 2 +-
2 files ch
From: "Edgar E. Iglesias"
Break out trap_illegal() to handle illegal operation traps.
We now generally stop translation of the current insn if
it's not valid.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 75 ---
1 file changed, 27
From: "Edgar E. Iglesias"
We already have a CPU property to control if a core has
an MMU or not. Remove USE_MMU PVR checks in favor of
looking at the property.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/helper.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
di
From: "Edgar E. Iglesias"
Break out trap_userspace() to avoid open coding it everywhere.
For privileged insns, we now always stop translation of the
current insn for cores without exceptions.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 76 +++---
From: "Edgar E. Iglesias"
Use bool and extract32 to represent the to, clr and
clrset flags.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/microblaze/translate.
From: "Edgar E. Iglesias"
Add a configurable output address mask, used to mimic the
configurable physical address bit width.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.c | 1 +
target/microblaze/mmu.c | 1 +
target/microblaze/mmu.h | 1 +
3 files changed, 3 insertions(+)
diff
From: "Edgar E. Iglesias"
Make compute_ldst_addr always use a temp. This simplifies
the code a bit in preparation for adding support for
64bit addresses.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 111 ++
From: "Edgar E. Iglesias"
Setup MicroBlaze builds for 64bit addressing.
No functional change since the translator does not yet
emit 64bit addresses.
Signed-off-by: Edgar E. Iglesias
---
configure | 1 +
target/microblaze/cpu.h | 6 +++---
2 files changed, 4 insertions(+), 3 delet
From: "Edgar E. Iglesias"
Extend special registers to 64-bits. This is in preparation for
MFSE/MTSE, moves to and from extended special registers.
Signed-off-by: Edgar E. Iglesias
---
linux-user/microblaze/cpu_loop.c | 4 +-
target/microblaze/cpu.h | 2 +-
target/microblaze/helper.c
On 2018年05月03日 15:53, Peter Xu wrote:
On Thu, May 03, 2018 at 03:43:35PM +0800, Jason Wang wrote:
On 2018年05月03日 15:28, Peter Xu wrote:
On Thu, May 03, 2018 at 03:20:11PM +0800, Jason Wang wrote:
On 2018年05月03日 14:04, Peter Xu wrote:
IMHO the guest can't really detect this, but it'll found
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index daed0b7e1f..5cc53eb035 100644
--- a/tar
From: "Edgar E. Iglesias"
Allow address sizes between 32 and 64 bits.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index d0649fdaaa..8c1f850ab1 100644
---
On 3 May 2018 at 10:05, Joel Stanley wrote:
> Hello,
>
> This short series implements a minimal definition of the Nordic
> Semiconductor nRF51, a Cortex-M0 ARM SoC, and the BBC micro:bit, a
> machine that will use this SoC.
>
> This work will serve as the base for our Google Summer of Code and
> O
From: "Edgar E. Iglesias"
Fix moves to FSR. Not only bit 31 is accessible.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 05449fb941..9
From: "Edgar E. Iglesias"
Add a R_TBLX_MISS MASK and SHIFT macros.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/mmu.c | 5 +++--
target/microblaze/mmu.h | 4
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 00
On Thu, May 03, 2018 at 10:26:40AM +0100, Peter Maydell wrote:
> On 3 May 2018 at 10:07, Daniel P. Berrangé wrote:
> > On Thu, May 03, 2018 at 08:21:00AM +0100, Stefan Hajnoczi wrote:
> >> I don't see an issue with time-based numbering schemes. Ubuntu made it
> >> popular and other projects (like
From: "Edgar E. Iglesias"
Add support for extended access to TLBLO's upper 32 bits.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/helper.h| 4 ++--
target/microblaze/mmu.c | 18 ++
target/microblaze/mmu.h | 4 ++--
target/microblaze/op_helper.c | 8 +
From: "Edgar E. Iglesias"
Reuse more code when decoding register numbers.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 38 +-
1 file changed, 9 insertions(+), 29 deletions(-)
diff --git a/target/microblaze/tra
On Wed, May 02, 2018 at 01:05:21PM +0100, Peter Maydell wrote:
> On 2 May 2018 at 12:58, Daniel P. Berrangé wrote:
> > I'm curious what is the compelling benefit of having a single fat QEMU
> > binary that included all archiectures at once ?
>
> The motivation is "I want to model a board with an
From: "Edgar E. Iglesias"
Prepare for 64-bit addresses.
This makes no functional difference as the upper parts of
the 64-bit addresses are not yet reachable.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/mmu.c | 14 +++---
target/microblaze/mmu.h | 6 +++---
2 files changed,
On Thu, 3 May 2018 10:07:27 +0100
Daniel P. Berrangé wrote:
> On Thu, May 03, 2018 at 08:21:00AM +0100, Stefan Hajnoczi wrote:
> > On Wed, May 02, 2018 at 09:02:00AM +0100, Daniel P. Berrangé wrote:
> > > On Wed, May 02, 2018 at 09:44:03AM +0200, Gerd Hoffmann wrote:
> > > > Hi,
> > > >
On 3 May 2018 at 10:05, Joel Stanley wrote:
> This adds the base for a machine model of the BBC micro:bit:
>
> https://en.wikipedia.org/wiki/Micro_Bit
>
> This is a system with a nRF51 SoC containing the main processor, with
> various peripherals on board.
>
> Signed-off-by: Joel Stanley
> ---
On Thu, 05/03 10:12, Daniel P. Berrangé wrote:
> On Thu, May 03, 2018 at 09:25:45AM +0800, Fam Zheng wrote:
> > HMP "info usernet" has been available but it isn't ideal for programmed
> > use cases. This closes the gap in QMP by adding a counterpart
> > "query-usernet" command. It is basically tran
* Juan Quintela (quint...@redhat.com) wrote:
> Either for quit, sync or packet, we first wake them.
>
> Signed-off-by: Juan Quintela
> ---
> migration/ram.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/migration/ram.c b/migration/ram.c
> index 0f1340b4
On 3 May 2018 at 10:07, Daniel P. Berrangé wrote:
> On Thu, May 03, 2018 at 08:21:00AM +0100, Stefan Hajnoczi wrote:
>> I don't see an issue with time-based numbering schemes. Ubuntu made it
>> popular and other projects (like DPDK) are doing the same thing now.
>>
>> The convention is YY.MM thou
On 03.05.2018 11:33, Daniel P. Berrangé wrote:
> On Wed, May 02, 2018 at 01:05:21PM +0100, Peter Maydell wrote:
>> On 2 May 2018 at 12:58, Daniel P. Berrangé wrote:
>>> I'm curious what is the compelling benefit of having a single fat QEMU
>>> binary that included all archiectures at once ?
>>
>>
On Thu, May 03, 2018 at 11:42:23AM +0200, Thomas Huth wrote:
> On 03.05.2018 11:33, Daniel P. Berrangé wrote:
> > On Wed, May 02, 2018 at 01:05:21PM +0100, Peter Maydell wrote:
> >> On 2 May 2018 at 12:58, Daniel P. Berrangé wrote:
> >>> I'm curious what is the compelling benefit of having a singl
On 03.05.2018 11:31, Daniel P. Berrangé wrote:
> On Thu, May 03, 2018 at 10:26:40AM +0100, Peter Maydell wrote:
>> On 3 May 2018 at 10:07, Daniel P. Berrangé wrote:
>>> On Thu, May 03, 2018 at 08:21:00AM +0100, Stefan Hajnoczi wrote:
I don't see an issue with time-based numbering schemes. Ub
On Thu, May 03, 2018 at 05:22:03PM +0800, Jason Wang wrote:
>
>
> On 2018年05月03日 15:53, Peter Xu wrote:
> > On Thu, May 03, 2018 at 03:43:35PM +0800, Jason Wang wrote:
> > >
> > > On 2018年05月03日 15:28, Peter Xu wrote:
> > > > On Thu, May 03, 2018 at 03:20:11PM +0800, Jason Wang wrote:
> > > > >
On Wed, May 02, 2018 at 05:03:09PM +0100, Paul Durrant wrote:
> > -Original Message-
> > From: Anthony PERARD [mailto:anthony.per...@citrix.com]
> > Sent: 02 May 2018 16:58
> > To: Paul Durrant
> > Cc: xen-de...@lists.xenproject.org; qemu-bl...@nongnu.org; qemu-
> > de...@nongnu.org; Stefa
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180503090532.3113-1-j...@jms.id.au
Subject: [Qemu-devel] [PATCH 0/2] arm: Add nRF51 SoC
* Juan Quintela (quint...@redhat.com) wrote:
> Once there add tracepoints.
>
> Signed-off-by: Juan Quintela
> ---
> migration/ram.c| 49 +-
> migration/trace-events | 2 ++
> 2 files changed, 46 insertions(+), 5 deletions(-)
>
> diff --git a/migr
Abdallah Bouassida writes:
> Generate an XML description for the cp-regs.
> Register these regs with the gdb_register_coprocessor().
> Add arm_gdb_get_sysreg() to use it as a callback to read those regs.
> Add a dummy arm_gdb_set_sysreg().
>
> Signed-off-by: Abdallah Bouassida
> ---
> gdbstub.
On 2 May 2018 at 12:13, Greg Kurz wrote:
> The following changes since commit 26bd8d98c4b3284a4c6fe3b67c98b1edd00e9beb:
>
> Merge remote-tracking branch
> 'remotes/vivier/tags/m68k-for-2.13-pull-request' into staging (2018-05-01
> 15:26:06 +0100)
>
> are available in the Git repository at:
>
>
On 3 May 2018 at 11:19, Alex Bennée wrote:
>
> Abdallah Bouassida writes:
>
>> Generate an XML description for the cp-regs.
>> Register these regs with the gdb_register_coprocessor().
>> Add arm_gdb_get_sysreg() to use it as a callback to read those regs.
>> Add a dummy arm_gdb_set_sysreg().
>>
>
On Wed 02 May 2018 04:12:49 PM CEST, Max Reitz wrote:
> On 2018-05-02 15:07, Alberto Garcia wrote:
>> On Wed 25 Apr 2018 04:03:22 PM CEST, Max Reitz wrote:
> But the question stands whether we need simple node replacement when
> we want bdrv_reopen() anyway. In addition, we don't need just
* Juan Quintela (quint...@redhat.com) wrote:
> We synchronize all threads each RAM_SAVE_FLAG_EOS. Bitmap
> synchronizations don't happen inside a ram section, so we are safe
> about two channels trying to overwrite the same memory.
OK, that's quite neat - so you don't need any extra flags in the
On 03/05/2018 08:22, Alexey Kardashevskiy wrote:
> On 2/5/18 7:50 pm, Paolo Bonzini wrote:
>> On 02/05/2018 11:33, Alexey Kardashevskiy wrote:
+# Note: the handler creates an object, enumerates properties and
destroys
+# the object so it only lists properties created in
For v8M the instructions VLLDM and VLSTM support lazy saving
and restoring of the secure floating-point registers. Even
if the floating point extension is not implemented, these
instructions must act as NOPs in Secure state, so they can
be used as part of the secure-to-nonsecure call sequence.
Fix
Le 03/05/2018 à 12:24, GitHub a écrit :
...
> Compare: https://github.com/qemu/qemu/compare/26bd8d98c4b3...98bae9c4afb4
> **NOTE:** This service been marked for deprecation:
> https://developer.github.com/changes/2018-04-25-github-services-deprecation/
>
> Functionality will be remove
The qemu-doc already states that this option is only maintained for
backward compatibility and "-device virtconsole" should be used
instead. So let's take the next step and mark this option officially
as deprecated.
Signed-off-by: Thomas Huth
---
qemu-doc.texi | 5 +
qemu-options.hx | 2 +-
Submitted this patch for review which should fix this bug:
https://patchwork.ozlabs.org/patch/907959/
** Changed in: qemu
Status: New => In Progress
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/b
This patch removes the current hackery where IOREQ_TYPE_PCI_CONFIG
reqyests are handled by faking PIO to 0xcf8 and 0xcfc and replaces it
with direct calls to pci_host_config_read/write_common().
Doing so necessitates mapping BDFs to PCIDevices but maintaining a simple
QLIST in xen_device_realize/un
On Tue, 1 May 2018 16:29:10 +0100
Daniel P. Berrangé wrote:
> On Fri, Apr 27, 2018 at 05:05:17PM +0200, Igor Mammedov wrote:
> > New option will be used to allow commands, which are prepared/need
> > to run, during preconfig state. Other commands that should be able
> > to run in preconfig state,
* Peter Xu (pet...@redhat.com) wrote:
> On Wed, Apr 25, 2018 at 01:27:19PM +0200, Juan Quintela wrote:
> > The function still don't use multifd, but we have simplified
> > ram_save_page, xbzrle and RDMA stuff is gone. We have added a new
> > counter.
> >
> > Signed-off-by: Juan Quintela
> >
> >
Thomas Huth writes:
> The qemu-doc already states that this option is only maintained for
> backward compatibility and "-device virtconsole" should be used
> instead. So let's take the next step and mark this option officially
> as deprecated.
>
> Signed-off-by: Thomas Huth
> ---
> qemu-doc.tex
On Tue, 1 May 2018 16:07:23 +0100
Daniel P. Berrangé wrote:
> On Fri, Apr 27, 2018 at 05:05:15PM +0200, Igor Mammedov wrote:
> > This option allows pausing QEMU in the new RUN_STATE_PRECONFIG state,
> > allowing the configuration of QEMU from QMP before the machine jumps
> > into board initializa
Thomas Huth writes:
> When running qtests with -nodefaults, we are not interested in
> these 'XYZ has no peer' messages.
>
> Signed-off-by: Thomas Huth
> ---
> net/net.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/net/net.c b/net/net.c
> index 29f8398.
On 03/05/2018 13:18, Paul Durrant wrote:
> This patch removes the current hackery where IOREQ_TYPE_PCI_CONFIG
> reqyests are handled by faking PIO to 0xcf8 and 0xcfc and replaces it
> with direct calls to pci_host_config_read/write_common().
> Doing so necessitates mapping BDFs to PCIDevices but ma
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