On 30 October 2015 at 19:45, Eric Blake wrote:
> Loaded question in response to
> https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg06988.html, but
> posting as a new thread to call attention to it:
>
> Libvirt uses libyajl to parse and format JSON. Would it be worth
> dragging in yet anoth
On 30 October 2015 at 20:03, Eric Blake wrote:
> On 10/30/2015 01:47 PM, Peter Maydell wrote:
>> On 30 October 2015 at 15:42, Markus Armbruster wrote:
>
>>> char: Convert to new qapi union layout
>
>> Hi; I'm afraid this doesn't build on w32:
>>
>> /home/petmay01/linaro/qemu-for-merges/qemu
On 28 October 2015 at 23:02, Jean-Christophe Dubois
wrote:
> i.MX25 SOC has a different CCM device than i.MX31.
>
> Qemu i.MX25 emulation was built with i.MX31 CCM driver. This allows
> Linux to work on top of the i.MX25 emultion but this is not correct.
>
> Furthermore, other SOC we could emulat
On 10/30/2015 06:41 PM, Stefan Hajnoczi wrote:
On Wed, Oct 28, 2015 at 06:01:02PM +0300, Denis V. Lunev wrote:
+int rfifolock_is_locked(RFifoLock *r);
Please use bool instead of int.
diff --git a/util/rfifolock.c b/util/rfifolock.c
index afbf748..8ac58cb 100644
--- a/util/rfifolock.c
+++ b/u
On 29 October 2015 at 20:16, Soren Brinkmann wrote:
> Add BANK_ #defines to index banked registers.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Soren Brinkmann
> ---
> v2:
> - move #defines from cpu.h to internals.h
> - drop ARM_ prefix in #defines
> ---
> target-arm/helper.c| 37 +++
From: Chen Gang
Originally, tilegx qemu only implement prefetch instructions in pipe x1,
did not implement them in pipe y2.
Signed-off-by: Chen Gang
Signed-off-by: Richard Henderson
---
target-tilegx/translate.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
di
0100)
are available in the git repository at:
git://github.com/rth7680/qemu.git tags/pull-tile-20151030
for you to fetch changes up to 2a080ce26682f35517b0e20f4ad10559e9270b5d:
target-tilegx: Implement prefetch instructions in pipe y2 (2015-10-22
07:5
On 30 October 2015 at 05:34, Peter Crosthwaite
wrote:
> Hi,
>
> This adds support for machine-specific primary boot blobs. This can be
> used to install little bits of firmware or boot code without having
> to throw the whole QEMU bootloader out and BYO (with device drivers
> and all).
>
> It is t
On 30 October 2015 at 05:34, Peter Crosthwaite
wrote:
> Add a flag that when set, will cause the primary CPU to start in secure
> mode, even if the overall boot in non-secure. This is useful for when
"is non-secure".
> there is a board-setup blob that needs to run from secure mode, but
> device
On Fri, Oct 30, 2015 at 1:24 PM, Peter Maydell wrote:
> On 28 October 2015 at 23:02, Jean-Christophe Dubois
> wrote:
>> i.MX25 SOC has a different CCM device than i.MX31.
>>
>> Qemu i.MX25 emulation was built with i.MX31 CCM driver. This allows
>> Linux to work on top of the i.MX25 emultion but
On 10/29/2015 12:31 AM, Xiao Guangrong wrote:
> These instructions are used by NVDIMM drivers and the specification
> locates at:
> https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
>
> There instructions are available on Skylake Server
>
> Signed-off-by: Xiao Guangrong
On Fri, Oct 30, 2015 at 1:49 PM, Peter Maydell wrote:
> On 30 October 2015 at 05:34, Peter Crosthwaite
> wrote:
>> Add a flag that when set, will cause the primary CPU to start in secure
>> mode, even if the overall boot in non-secure. This is useful for when
>
> "is non-secure".
>
>> there is a
On 30 October 2015 at 05:35, Peter Crosthwaite
wrote:
> Firstly, enable monitor mode and PSCI, both are which are features of
> this board.
>
> In addition to PSCI, this board also uses SMC for cache maintainence
> ops. This means we need a secure monitor to catch these and nop them.
> Use the ARM
"arm: stellaris: " prefix in subject line.
On Sun, Oct 11, 2015 at 8:36 PM, Michael Davidsaver
wrote:
> Add GPIO in for the stellaris board which calls
> qemu_system_reset_request() on reset request.
>
> Signed-off-by: Michael Davidsaver
Otherwise,
Reviewed-by: Peter Crosthwaite
Regards,
Pet
On 30.10.2015 20:25, Jeff Cody wrote:
> Commit 934659c switched the iotests to run qemu and qemu-nbd from a bash
> subshell, in order to catch segfaults. Unfortunately, this means the
> process PID cannot be captured via '$!'. We stopped killing qemu and
> qemu-nbd processes, leaving a lot of orph
On 30 October 2015 at 20:59, Peter Crosthwaite
wrote:
> On Fri, Oct 30, 2015 at 1:49 PM, Peter Maydell
> wrote:
>> I thought you were planning to have the generic code do the
>> S->NS transition; but I guess it works better in the board
>> code (we have to go up into Monitor and back down again,
On 30.10.2015 20:25, Jeff Cody wrote:
> Commit 934659c switched the iotests to run qemu-io from a bash subshell,
> in order to catch segfaults. This method is incompatible with the
> current valgrind_qemu_io() bash function.
>
> Move the valgrind usage into the exec subshell in _qemu_io_wrapper()
On Sun, Oct 11, 2015 at 8:36 PM, Michael Davidsaver
wrote:
> Implement the SYSRESETREQ bit of the AIRCR register
> for armv7-m (ie. cortex-m3) to trigger a GPIO out.
>
> Signed-off-by: Michael Davidsaver
Reviewed-by: Peter Crosthwaite
> ---
> hw/intc/armv7m_nvic.c | 9 -
> 1 file chan
Missing CC of Alistair for STM32F205.
On Sun, Oct 11, 2015 at 8:36 PM, Michael Davidsaver
wrote:
> Change armv7m_init to return the DeviceState* for the NVIC.
> This allows access to all GPIO blocks, not just the IRQ inputs.
> Move qdev_get_gpio_in() calls out of armv7m_init() into
> board code f
This series looks good, up to Peter if is qualifies for 2.5. It was
clearly on list well before soft freeze and really my tardiness as to
why it is late with review. So I'll make a case for inclusion.
It does seem to be missing a cover, and/or the in-reply-to looks a bit
strange. Maybe patches mis
On Fri, Oct 30, 2015 at 2:14 PM, Peter Maydell wrote:
> On 30 October 2015 at 20:59, Peter Crosthwaite
> wrote:
>> On Fri, Oct 30, 2015 at 1:49 PM, Peter Maydell
>> wrote:
>>> I thought you were planning to have the generic code do the
>>> S->NS transition; but I guess it works better in the bo
On 27 October 2015 at 04:02, Peter Crosthwaite
wrote:
> This patch series adds bare-minimum Allwinner SATA support.
>
> P1 is a trivial to help debug AHCI.
>
> Changed since RFC:
> Addressed Beniamino review.
> Rebased to avoid bad deps (John Snow review)
>
> Regards,
> Peter
>
>
> Peter Crosthwai
On Fri, Oct 30, 2015 at 2:10 PM, Peter Maydell wrote:
> On 30 October 2015 at 05:35, Peter Crosthwaite
> wrote:
>> Firstly, enable monitor mode and PSCI, both are which are features of
>> this board.
>>
>> In addition to PSCI, this board also uses SMC for cache maintainence
>> ops. This means we
On Fri, Oct 30, 2015 at 2:28 PM, Peter Maydell wrote:
> On 27 October 2015 at 04:02, Peter Crosthwaite
> wrote:
>> This patch series adds bare-minimum Allwinner SATA support.
>>
>> P1 is a trivial to help debug AHCI.
>>
>> Changed since RFC:
>> Addressed Beniamino review.
>> Rebased to avoid bad
On 10/30/2015 05:33 PM, Peter Crosthwaite wrote:
> On Fri, Oct 30, 2015 at 2:28 PM, Peter Maydell
> wrote:
>> On 27 October 2015 at 04:02, Peter Crosthwaite
>> wrote:
>>> This patch series adds bare-minimum Allwinner SATA support.
>>>
>>> P1 is a trivial to help debug AHCI.
>>>
>>> Changed sin
On 30 October 2015 at 21:20, Peter Crosthwaite
wrote:
> This series looks good, up to Peter if is qualifies for 2.5. It was
> clearly on list well before soft freeze and really my tardiness as to
> why it is late with review. So I'll make a case for inclusion.
>
> It does seem to be missing a cove
On 30 October 2015 at 21:34, John Snow wrote:
>
>
> On 10/30/2015 05:33 PM, Peter Crosthwaite wrote:
>> On Fri, Oct 30, 2015 at 2:28 PM, Peter Maydell
>> wrote:
>>> On 27 October 2015 at 04:02, Peter Crosthwaite
>>> wrote:
Peter Crosthwaite (4):
ahci: Add some MMIO debug printfs
>>>
On 10/30/2015 05:37 PM, Peter Maydell wrote:
> On 30 October 2015 at 21:34, John Snow wrote:
>>
>>
>> On 10/30/2015 05:33 PM, Peter Crosthwaite wrote:
>>> On Fri, Oct 30, 2015 at 2:28 PM, Peter Maydell
>>> wrote:
On 27 October 2015 at 04:02, Peter Crosthwaite
wrote:
> Peter Cros
On 24 October 2015 at 13:21, Dmitry Osipenko wrote:
> Changelog for ARM MPTimer QEMUTimer to ptimer conversion:
>
> V2: Fixed changing periodic timer counter value "on the fly". I added a
> test to the gist to cover that issue.
>
> V3: Fixed starting the timer with load = 0 and cou
On 30 October 2015 at 21:40, John Snow wrote:
> On 10/30/2015 05:37 PM, Peter Maydell wrote:
>> Given the diffstat, are you planning to take this through
>> the IDE tree? I'm happy for you to do that, I can just take
>> this off my to-review list then :-)
> If nobody has objections, I assumed tha
On 30 October 2015 at 17:37, Peter Maydell wrote:
> On 30 October 2015 at 14:19, Markus Armbruster wrote:
>> Peter Maydell writes:
>>> I get an error on 64-bit ARM running the ivshmem tests:
>>>
>>> TEST: tests/ivshmem-test... (pid=22948)
>>> /i386/ivshmem/single:
On 30 October 2015 at 21:24, Peter Crosthwaite
wrote:
> On Fri, Oct 30, 2015 at 2:14 PM, Peter Maydell
> wrote:
>> The other question is what happens on a board like this if
>> the user says -enable-kvm -cpu cortex-a15 ? Does that get us
>> a CPU without the EL3 property? (I forget...) In any ca
On Fri, Oct 30, 2015 at 3:04 PM, Peter Maydell wrote:
> On 30 October 2015 at 21:24, Peter Crosthwaite
> wrote:
>> On Fri, Oct 30, 2015 at 2:14 PM, Peter Maydell
>> wrote:
>>> The other question is what happens on a board like this if
>>> the user says -enable-kvm -cpu cortex-a15 ? Does that ge
On 30 October 2015 at 21:32, Peter Crosthwaite
wrote:
> On Fri, Oct 30, 2015 at 2:10 PM, Peter Maydell
> wrote:
>> This still confuses me. What I was expecting to see was something like:
>>
>> /* Monitor mode vector table; entry points which will only be reached
>> * if the guest kernel
On 10/27/2015 12:02 AM, Peter Crosthwaite wrote:
> This patch series adds bare-minimum Allwinner SATA support.
>
> P1 is a trivial to help debug AHCI.
>
> Changed since RFC:
> Addressed Beniamino review.
> Rebased to avoid bad deps (John Snow review)
>
> Regards,
> Peter
>
>
> Peter Crosthwa
31.10.2015 00:52, Peter Maydell пишет:
On 24 October 2015 at 13:21, Dmitry Osipenko wrote:
Changelog for ARM MPTimer QEMUTimer to ptimer conversion:
V2: Fixed changing periodic timer counter value "on the fly". I added a
test to the gist to cover that issue.
V3: Fixed start
Le 30/10/2015 21:50, Peter Crosthwaite a écrit :
On Fri, Oct 30, 2015 at 1:24 PM, Peter Maydell wrote:
On 28 October 2015 at 23:02, Jean-Christophe Dubois
wrote:
i.MX25 SOC has a different CCM device than i.MX31.
Qemu i.MX25 emulation was built with i.MX31 CCM driver. This allows
Linux to w
Le 12/10/2015 15:42, Riku Voipio a écrit :
> On perjantaina 11. syyskuuta 2015 13.59.29 EEST, Peter Maydell wrote:
>> On 6 September 2015 at 00:56, Timothy E Baldwin
>> wrote:
>>> Check array bounds in host_to_target_errno() and target_to_host_errno().
>>>
>>> Signed-off-by: Timothy Edward Baldw
On Fri, Oct 30, 2015 at 2:14 PM, Peter Maydell wrote:
> On 30 October 2015 at 20:59, Peter Crosthwaite
> wrote:
>> On Fri, Oct 30, 2015 at 1:49 PM, Peter Maydell
>> wrote:
>>> I thought you were planning to have the generic code do the
>>> S->NS transition; but I guess it works better in the bo
Hello Jason,
Thanks for reviewing. See my answers inline.
> On 30 Oct 2015, at 07:28 AM, Jason Wang wrote:
>
>
>
> On 10/28/2015 01:44 PM, Jason Wang wrote:
>>
>> On 10/26/2015 01:00 AM, Leonid Bloch wrote:
>>> Hello qemu-devel,
>>>
>>> This patch series is an RFC for the new networking de
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