On Sun, Oct 11, 2015 at 8:36 PM, Michael Davidsaver
<mdavidsa...@gmail.com> wrote:
> Implement the SYSRESETREQ bit of the AIRCR register
> for armv7-m (ie. cortex-m3) to trigger a GPIO out.
>
> Signed-off-by: Michael Davidsaver <mdavidsa...@gmail.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.pe...@gmail.com>
> ---
> hw/intc/armv7m_nvic.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 3ec8408..6fc167e 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -28,6 +28,7 @@ typedef struct {
> MemoryRegion gic_iomem_alias;
> MemoryRegion container;
> uint32_t num_irq;
> + qemu_irq sysresetreq;
> } nvic_state;
>
> #define TYPE_NVIC "armv7m_nvic"
> @@ -348,10 +349,13 @@ static void nvic_writel(nvic_state *s, uint32_t offset,
> uint32_t value)
> break;
> case 0xd0c: /* Application Interrupt/Reset Control. */
> if ((value >> 16) == 0x05fa) {
> + if (value & 4) {
> + qemu_irq_pulse(s->sysresetreq);
> + }
> if (value & 2) {
> qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");
> }
> - if (value & 5) {
> + if (value & 1) {
> qemu_log_mask(LOG_UNIMP, "AIRCR system reset
> unimplemented\n");
> }
> if (value & 0x700) {
> @@ -535,11 +539,14 @@ static void armv7m_nvic_instance_init(Object *obj)
> * value in the GICState struct.
> */
> GICState *s = ARM_GIC_COMMON(obj);
> + DeviceState *dev = DEVICE(obj);
> + nvic_state *nvic = NVIC(obj);
> /* The ARM v7m may have anything from 0 to 496 external interrupt
> * IRQ lines. We default to 64. Other boards may differ and should
> * set the num-irq property appropriately.
> */
> s->num_irq = 64;
> + qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
> }
>
> static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
> --
> 2.1.4
>
