Hello,
Problem solved, there was bug in my gmac model, that cause writes
outside my gmac device state structure.
That leads to such (undefined) behaviour.
Regards,
Marcin
W dniu 10.10.2015 o 22:34, mar.krzeminski pisze:
Hello,
I have my own virtual machine (already asked some questions abo
On Wed, 2015-10-07 at 18:06 +0300, Marcel Apfelbaum wrote:
> On 09/12/2015 03:36 PM, Knut Omang wrote:
> > This patch provides the building blocks for creating an SR/IOV
> > PCIe Extended Capability header and register/unregister
> > SR/IOV Virtual Functions.
> >
> > Signed-off-by: Knut Omang
> >
Looks great. But I think you want to split this into staged patches.
Use git reset HEAD^ to undo the git commit (but keep the file changes)
then git add -p to select hunks to stage. Then commit the logically
sequential groups of changes as indiv. patches. A general rule is you
should try and avoid
On Fri, Oct 9, 2015 at 6:28 AM, Michael Davidsaver
wrote:
> The M series MPU is almost the same as the already
> implemented R series MPU. So use the M series
> and translate as best we can.
>
There is some work on list for this that never got a respin:
https://lists.gnu.org/archive/html/qemu-d
On Fri, Oct 9, 2015 at 6:28 AM, Michael Davidsaver
wrote:
> Handlers will not be entered unless v7m.exception is updated.
> For example, an invalid instruction won't invoke UsageError,
> but rather re-executes the invalid instruction forever.
>
> Add warn and fix of mis-aligned handlers.
>
> Ensur
From: >
msix->mmio is added to XenPCIPassthroughState's object as property.
object_finalize_child_property is called for XenPCIPassthroughState's
object, which calls object_property_del_all, which is going to try to
delete msix->mmio. object_finalize_child_property() will access
msix->mmio's obj.
Add a Sysbus AHCI subclass for the Allwinner AHCI. It has a few extra
vendor specific registers that are used for phy and power init.
Signed-off-by: Peter Crosthwaite
---
hw/ide/ahci.c | 98 +++
hw/ide/ahci.h | 16 ++
2 files change
Hi John and Beniamino,
This patch series adds bear-minimum Allwinner SATA support.
P1 is a trivial to help debug AHCI.
Regards,
Peter
Peter Crosthwaite (4):
ahci: Add some MMIO debug printfs
ahci: split realize and init
ahci: Add allwinner AHCI
arm: allwinner-a10: Add SATA
hw/arm/allw
These are useful for bringup of AHCI.
Signed-off-by: Peter Crosthwaite
---
hw/ide/ahci.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 796be15..4cfce8f 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -378,17 +378,
Do the init level tasks asap and the realize later (mainly when
num_ports is available). This allows sub-class realize routines
to work with the device post-init.
Signed-off-by: Peter Crosthwaite
---
hw/ide/ahci.c | 36 +++-
hw/ide/ahci.h | 3 ++-
hw/ide/ich.c |
Add the Allwinner A10 AHCI controller module to the SoC.
Signed-off-by: Peter Crosthwaite
---
hw/arm/allwinner-a10.c | 11 +++
include/hw/arm/allwinner-a10.h | 5 +
2 files changed, 16 insertions(+)
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 56e924d.
On Sun, Oct 4, 2015 at 9:09 PM, Guenter Roeck wrote:
> On 10/04/2015 07:21 PM, Peter Crosthwaite wrote:
>>
>> On Sun, Oct 4, 2015 at 6:08 PM, Guenter Roeck wrote:
>>>
>>> On 10/04/2015 02:38 PM, Beniamino Galvani wrote:
On Sun, Oct 04, 2015 at 02:11:35PM -0700, Guenter Roeck wrote:
On Sun, Oct 4, 2015 at 12:56 PM, Beniamino Galvani wrote:
> On Sat, Oct 03, 2015 at 02:31:08PM -0700, Peter Crosthwaite wrote:
>> QEMU cubieboard has no usable storage media, but the real hardware
>> does have AHCI sata. I added sysbus-ahci at the right place but turns
>> out the SATA controller h
I'm starting to doubt my diagnosis. The bug may be in my understanding of
the interrupt priorities. I'll have to do another test program.
On Oct 11, 2015 11:25 AM, "Peter Crosthwaite"
wrote:
> On Fri, Oct 9, 2015 at 6:28 AM, Michael Davidsaver
> wrote:
> > Handlers will not be entered unless v
On 11 October 2015 at 19:58, Michael Davidsaver wrote:
> I'm starting to doubt my diagnosis. The bug may be in my understanding of
> the interrupt priorities. I'll have to do another test program.
Note that our handling of prioritization of the internal
exceptions is pretty badly broken. The fi
(sorry for the late answer)
On 2015-08-26 14:12, Petar Jovanovic wrote:
> From: Petar Jovanovic
>
> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
> they require any particular mode for its FPU. This patch removes the checks
> that may break a program that uses these
Public bug reported:
The WineTestBot (https://testbot.winehq.org/) uses QEmu live snapshots
to ensure the Wine tests are always run in a pristine Windows
environment. However the revert times keep increasing linearly with the
age of the snapshot, going from tens of seconds to thousands. While the
Xiao,
Are these patches present in any git tree so that they can be easily tried out.
Regards,
Bharata.
On Sun, Oct 11, 2015 at 9:22 AM, Xiao Guangrong
wrote:
> Changelog in v3:
> There is huge change in this version, thank Igor, Stefan, Paolo, Eduardo,
> Michael for their valuable comments, th
On 10/12/2015 10:59 AM, Bharata B Rao wrote:
Xiao,
Are these patches present in any git tree so that they can be easily tried out.
Sorry, currently no git tree out of my workspace is available :(
BTW, this patchset is based on top of the commit b37686f7e on qemu tree:
commit b37686f7e84b22
Implement the SYSRESETREQ bit of the AIRCR register
for armv7-m (ie. cortex-m3) to trigger a GPIO out.
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 3ec84
Add GPIO in for the stellaris board which calls
qemu_system_reset_request() on reset request.
Signed-off-by: Michael Davidsaver
---
hw/arm/stellaris.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 82a4ad5..0114e0a 100644
--- a/hw/
Change armv7m_init to return the DeviceState* for the NVIC.
This allows access to all GPIO blocks, not just the IRQ inputs.
Move qdev_get_gpio_in() calls out of armv7m_init() into
board code for stellaris and stm32f205 boards.
Signed-off-by: Michael Davidsaver
---
hw/arm/armv7m.c| 9 ++-
Public bug reported:
QEMU version: 2.4, also tested b37686f (2015-10-09 12:18:13 +0100) not working.
Requires KVM and SDL, possibly others.
Kernel version: 4.1 working, 4.2 not working.
Architecture: x86_64
Target: x86_64, also tested i386 not working.
Step 0: Install versions listed above.
Step
On 10/11/2015 11:23 AM, Peter Crosthwaite wrote:
> On Fri, Oct 9, 2015 at 6:28 AM, Michael Davidsaver
> wrote:
>> The M series MPU is almost the same as the already
>> implemented R series MPU. So use the M series
>> and translate as best we can.
>>
> There is some work on list for this that neve
On 10/11/2015 05:17 AM, Dan Williams wrote:
On Sat, Oct 10, 2015 at 8:52 PM, Xiao Guangrong
wrote:
[..]
== Test ==
In host
1) create memory backed file, e.g # dd if=zero of=/tmp/nvdimm bs=1G count=10
2) append "-object memory-backend-file,share,id=mem1,
mem-path=/tmp/nvdimm -devic
On 10/07/2015 01:32 PM, Denis V. Lunev wrote:
This patchset provides simplified guest-exec functionality. The
idea is simple. We drop original guest-pipe-open etc stuff and provides
simple and dumb API:
- spawn process (originally with stdin/stdout/stderr as /dev/null)
- later simple buffer is ad
Mark Pizzolato writes:
> Public bug reported:
>
> On any host platform where SOCK_CLOEXEC is defined (Linux at least), a
> socket is leaked on each call to qemu_socket() AND the socket returned
> hasn't been created with the desired SOCK_CLOEXEC attribute. The
> qemu_socket routine is:
>
> Line
Hi!
> It looks like the only thing in the gicv3 code that is using
> a define from the arm_gic_common.h file is "GIC_INTERNAL",
> so we can just put a suitable define of that into the v3 header
> (maybe giving it a better name in the process).
Yes, indeed. Actually, first versions of my GICv3 p
28 matches
Mail list logo
