On 05/07/2015 02:13 AM, Markus Armbruster wrote:
> John Snow writes:
>
>> On 05/06/2015 11:19 AM, Markus Armbruster wrote:
>>> John Snow writes:
>>>
On 05/06/2015 02:25 AM, Markus Armbruster wrote:
> John Snow writes:
>
>> Instead of letting printf and friends do this for us
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> +#define DATA_SIZE (1 << SHIFT)
> +
> +#if DATA_SIZE == 8
> +#define SUFFIX q
> +#define LSUFFIX q
> +#define SDATA_TYPE int64_t
> +#define DATA_TYPE uint64_t
Duplicating all of the stuff from softmmu_template.h is Just Wrong.
> +/* For the benefit o
On 05/06/2015 08:38 AM, Alvise Rigo wrote:
> +/* An output operand to return the StoreConditional result */
> +static void gen_stcond_i32(TCGOpcode opc, TCGv_i32 is_dirty, TCGv_i32 val,
> + TCGv addr, TCGMemOp memop, TCGArg idx)
> +{
> +tcg_gen_op5ii_i32(opc, is_dirty, v
Im replying this cause i made a mistake asking to someones private mail,
sorry:
> OK, another question. How come if Cortex-M3 doesnt support DSP
instructions
> qemu understand them? I tried some of them with an stellaris lm3s6965evb.
I
> do understand that they were implemented for the A profile co
On (Thu) 07 May 2015 [13:45:26], Peter Maydell wrote:
> On 7 May 2015 at 12:50, Juan Quintela wrote:
> >
> >
> > Hi again
> >
> > For v2
> >
> > - fix 32bit compilation (as said, compiling for 64bit linux, 64bit
> > windows and 32bit windows was not enough)
> >
> > - Now, we have versions 2.4 ev
On 05/06/2015 10:20 PM, Wen Congyang wrote:
> On 05/02/2015 12:47 AM, John Snow wrote:
>>
>>
>> On 04/03/2015 07:05 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 03/04/2015 12:01, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
On 7 May 2015 at 17:46, Juan Quintela wrote:
> Hi again (2)
>
> And now on v3
>
> - I fix not using of atomic with 64 bit values.
> Notice that the code was wrong in any architecture, someplaces used atomics,
> someothers used something different.
>
> Praying $deity_in_32bits of the day
>
> Pl
On 02/27/2015 12:24 PM, Vladimir Sementsov-Ogievskiy wrote:
> Signed-off-by: John Snow
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> tests/qemu-iotests/iotests.py | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests
I used the -nographic option as well, but lost it in the copy and paste.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/623852
Title:
PPC emulation loops on booting a FreeBSD kernel
Status in QEMU:
Latest version from git, using FreeBSD10.0:
qemu-system-ppc64 -cdrom FreeBSD-10.0-RELEASE-powerpc-disc1.iso -hda
freebsd10.0-ppc -m 256 -boot d -k en-us:
SLOF **
QEMU Starting
Build Date = Mar 13 2015 22:37:28
FW Version = git
On 05/07/2015 11:51 AM, John Snow wrote:
> Instead of converting each byte one-at-a-time and then sending each byte
> over the wire, use sprintf() to pre-compute all of the hex nibs into a
> single buffer, then send the entire buffer all at once.
>
> This gives a moderate speed boost to memread()
On 05/07/2015 04:21 PM, Eric Blake wrote:
> On 05/07/2015 11:51 AM, John Snow wrote:
>> Instead of converting each byte one-at-a-time and then sending
>> each byte over the wire, use sprintf() to pre-compute all of the
>> hex nibs into a single buffer, then send the entire buffer all at
>> once.
On 05/06/2015 10:18 AM, John Snow wrote:
>> To find out, add just buffering. Something like this in your patch
>> instead of byte2hex():
>>
>> for (i = 0; i < len; i++) {
>> -qtest_sendf(chr, "%02x", data[i]);
>> +snprintf(&enc[i * 2], 2, "%02x", data[i]);
>>
Since no response, I assume that it is not suitable to send patches
before finish printing hello world successfully (when sending patches,
we should be sure of the patches are valuable enough).
And sorry, I delayed too much for developing tilegx qemu, next I shall
try to print hello world success
On 07.05.15 07:33, David Gibson wrote:
> Hi Alex (et al),
>
> Here's my current batch of -machine pseries related patches which I
> think are ready to merge. Sorry this is a resend pretty close after
> the last batch I sent out - I wanted to make sure I sent out the queue
> because I'm going to
On 05.05.15 09:18, Paolo Bonzini wrote:
> Patches 1 and 2 enable support from more than 8 MMU modes in TCG (patch
> 1 is in the targets, patch 2 is in cpu-defs.h). The TLB size is reduced
> proportionally on targets where that is necessary.
>
> Patch 3 uses the new support in the PPC target.
>
On 05.05.15 11:43, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> Reviewed-by: Max Reitz
> ---
[...]
> +void surface_gl_create_texture(ConsoleGLState *gls,
> + DisplaySurface *surface)
> +{
> +assert(gls);
> +assert(surface_stride(surface) % surfac
On 07.05.15 07:33, David Gibson wrote:
> From: Michael Roth
>
> This device emulates a firmware abstraction used by pSeries guests to
> manage hotplug/dynamic-reconfiguration of host-bridges, PCI devices,
> memory, and CPUs. It is conceptually similar to an SHPC device,
> complete with LED indi
At Alex Graf's request I'm now acting as sub-maintainer for the sPAPR
(-machine pseries) code. This updates MAINTAINERS accordingly.
While we're at it, change the label to mention pseries since that's the
actual name of the machine type, even if most of the C files use the sPAPR
name.
Signed-off
On Fri, May 08, 2015 at 12:39:20AM +0200, Alexander Graf wrote:
>
>
> On 07.05.15 07:33, David Gibson wrote:
> > From: Michael Roth
> >
> > This device emulates a firmware abstraction used by pSeries guests to
> > manage hotplug/dynamic-reconfiguration of host-bridges, PCI devices,
> > memory,
On Thu, May 7, 2015 at 6:59 AM, Peter Maydell wrote:
> On 6 May 2015 at 23:50, Peter Crosthwaite
> wrote:
>> GIC generally uses a 4k memory region for the various subregions, such
>> as GICC, GICD, GICV and GICH. Macroify this number in the publicly
>> visible header.
>
>> +#define ARM_GIC_REGIO
On Thu, May 7, 2015 at 7:02 AM, Peter Maydell wrote:
> On 6 May 2015 at 23:50, Peter Crosthwaite
> wrote:
>> Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
>> under-decoded through a 64k address region so implement aliases
>> accordingly.
>
>> +assert(ARRAY_SIZE(xlnx_zy
On 08.05.15 02:11, David Gibson wrote:
> At Alex Graf's request I'm now acting as sub-maintainer for the sPAPR
> (-machine pseries) code. This updates MAINTAINERS accordingly.
>
> While we're at it, change the label to mention pseries since that's the
> actual name of the machine type, even if
On 05/08/2015 02:32 AM, John Snow wrote:
>
>
> On 05/06/2015 10:20 PM, Wen Congyang wrote:
>> On 05/02/2015 12:47 AM, John Snow wrote:
>>>
>>>
>>> On 04/03/2015 07:05 AM, Paolo Bonzini wrote:
On 03/04/2015 12:01, Wen Congyang wrote:
> Signed-off-by: Wen Congyang
> Signed-o
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
board.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs added. The
pre-existing models for GEM and UART are not SoC friendly (no visible
Add the ARM Cortex-A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.
Ac
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use macro for GIC_INTERNAL
hw/arm/xlnx-zynqmp.c | 17 +
1 file changed, 17 insertions(
Rename some A57 CP register variables in preparation for support for
Cortex A53. Use "a57_a53" to describe the shareable features. Some of
the CP15 registers (such as ACTLR) are specific to implementation, but
we currently just RAZ them so continue with that as the policy for both
A57 and A53 proce
There are 4x Cadence GEMs in ZynqMP. Add them.
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Remove use of ERR_PROP_CHECK_RETURN
hw/arm/xlnx-zynqmp.c | 35 +++
include/hw/arm/xlnx-zynqmp.h
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
under-decoded through a 64k address region so implement aliases
accordingly.
Signed-off-by: Peter Crosthwaite
---
changed since v7:
Made GIC region size definition board specific
changed since v6:
Added aliases.
changed since v5
Cleanup some variable names in preparation for migrating the state
struct and type cast macro to a public header. The acronym "GEM" on
its own is not specific enough to be used in a more global namespace
so preface with "cadence". Fix the capitalisation of "gem" in the
state type while touching the
Create a new header for Cadence GEM to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
With quad Cortex-A53 CPUs.
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Tested-by: Alistair Francis
Reviewed-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
---
changed since v4 (PMM review):
Squashed in PSCI stuffs.
Add (c)
Clean up some variable names in preparation for migrating the state struct
and type cast macro to a public header. The acronym "UART" on it's own is
not specific enough to be used in a more global namespace so preface with
"cadence". Fix the capitalisation of "uart" in the state type while touching
Add a machine model for the Xilinx ZynqMP SoC EP108 board.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Chaned since v1:
Change board name to ep108
hw/arm/Makefile.objs | 2 +-
hw/ar
Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
There are 2x Cadence UARTs in Zynq MP. Add them.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Changed since v4:
Remove ERR_PROP_CHECK_RETURN usage.
Changed since v1:
Fixed "UARTSs" typo
hw/arm/xlnx-zynqmp.c
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use memory_region_allocate_system_memory
Change too-small warning to be qemu_log
changed since v1:
Add ram size cla
Add bootloader support using standard ARM bootloader.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Add loader_start field
Make commit message body standalone.
hw/arm/xlnx-ep108.c | 9 +
1 file changed, 9 insertions(+)
The function bdrv_clear_dirty_bitmap() is updated to use
faster hbitmap_reset_all() call.
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
Acked-by: Paolo Bonzini
---
block.c| 2 +-
include/qemu/hbitmap.h | 8
tests/test-hbitmap.c |
We're currently missing the laa and laag instructions in our emulation.
In fact, we're missing the complete "interlocked-access facility 1" which
is part of zEC12. However, I really only needed the laa instruction for now.
Signed-off-by: Alexander Graf
---
This really should implement all the o
I find it really hard to grasp what each field in the opcode list means.
Slowly walking through its semantics myself, I figured I'd write a small
summary at the top of the file to make life easier for me and whoever
looks at the file next.
Signed-off-by: Alexander Graf
---
target-s390x/insn-data
On 05.05.15 17:49, Richard Henderson wrote:
> On 05/05/2015 12:18 AM, Paolo Bonzini wrote:
>> Patches 1 and 2 enable support from more than 8 MMU modes in TCG (patch
>> 1 is in the targets, patch 2 is in cpu-defs.h). The TLB size is reduced
>> proportionally on targets where that is necessary.
>
On 2015/4/29 23:24, Shannon Zhao wrote:
> The private qdev properties of virtio devices are only used by
> themselves. As Peter suggested and like what virtio-blk has done, we
> should move the private qdev properties into devices and don't expose
> them to avoid wrongly use.
>
> This patchset is
On 2015/5/7 18:50, Alex Bennée wrote:
> Shannon Zhao writes:
>
>> > From: Shannon Zhao
>> >
>> > Introduce a preliminary framework in virt-acpi-build.c with the main
>> > ACPI build functions. It exposes the generated ACPI contents to
>> > guest over fw_cfg.
>> >
>> > The required ACPI v5.1 tabl
On 2015/5/7 23:44, Peter Maydell wrote:
> On 7 May 2015 at 10:29, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> Introduce a preliminary framework in virt-acpi-build.c with the main
>> ACPI build functions. It exposes the generated ACPI contents to
>> guest over fw_cfg.
>>
>> The required ACPI v
On 2015/5/7 23:51, Peter Maydell wrote:
> On 7 May 2015 at 10:29, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > Add aml_interrupt() for describing device interrupt in resource template.
>> > These can be used to generating DSDT table for ACPI on ARM.
>> > +/* Interrupt Number */
>> >
On Thu, 05/07 14:20, Stefan Hajnoczi wrote:
> On Wed, May 06, 2015 at 12:52:02PM +0800, Fam Zheng wrote:
> > v2: Fix typo and add Eric's rev-by in patch 3.
> > Add patch 1 to discard target in mirror job. (Paolo)
> > Add patch 6 to improve iotests.wait_ready. (John)
> >
> > This fixes the
On 7 May 2015 at 22:05, Chen Gang wrote:
>
> Since no response, I assume that it is not suitable to send patches
> before finish printing hello world successfully (when sending patches,
> we should be sure of the patches are valuable enough).
Er, I said you should send patches earlier rather than
John Snow writes:
> On 05/07/2015 08:22 AM, Peter Maydell wrote:
>> On 10 March 2015 at 17:45, Peter Maydell wrote:
>>> On 10 March 2015 at 17:43, John Snow wrote:
Wasn't aware we were actually going through with that; it had looked
like we were going to refrain from fiddling with it
On Fr, 2015-05-08 at 00:28 +0200, Alexander Graf wrote:
>
> On 05.05.15 11:43, Gerd Hoffmann wrote:
> > Signed-off-by: Gerd Hoffmann
> > Reviewed-by: Max Reitz
> > ---
>
> [...]
>
> > +void surface_gl_create_texture(ConsoleGLState *gls,
> > + DisplaySurface *surfa
Eric Blake writes:
> On 05/06/2015 10:18 AM, John Snow wrote:
>
>>> To find out, add just buffering. Something like this in your patch
>>> instead of byte2hex():
>>>
>>> for (i = 0; i < len; i++) {
>>> -qtest_sendf(chr, "%02x", data[i]);
>>> +snprintf(&enc[i * 2]
Paolo Bonzini writes:
> Right now, NBD includes potentially platform-specific error values in
> the wire protocol.
Design flaw.
> Luckily, most common error values are more or less universal: in
> particular, of all errno values <= 34 (up to ERANGE), they are all
> the same on supported platfor
Public bug reported:
Hi,
I'm running a freshly installed Windows 7 domU on an up-to-date Debian
jessie machine running Xen 4.4.1-9. When the Windows machine is idle,
I'm seeing upwards of 10% CPU usage from the qemu-system-i386 instance.
Other Linux and FreeBSD machines register negligable CPU u
Applied to -trivial, thank you!
/mjt
No, he is on vacation this week. Sorry for the delay!
Of you are doing cleanups in virtio, perhaps you can look into using alias
properties for virtio-balloon's QOM properties (for example the statistics).
The code is currently using object_property_add and manually-written
getters/setters.
Th
Hello!
> Hm, weren't there some patches for irqfd on arm?
Yes, there were. However, they had a design problem by breaking backwards
compatibility
with unmodified virtio. Their idea was to set up one more shared memory area
between
virtio and vhost-net and use it to pass ISR value, which helps
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