On Mi, 2015-03-04 at 19:12 +, Gordan Bobic wrote:
> On 2015-03-04 13:20, Gerd Hoffmann wrote:
> > On Di, 2015-03-03 at 10:32 +, Gordan Bobic wrote:
> >> I need to pass a custom e820 map to a virtual machine for
> >> troubleshooting purposes and working around IOMMU hardware
> >> bugs.
> >>
On Thu, Mar 05, 2015 at 01:51:26PM +1100, David Gibson wrote:
> On Tue, 3 Mar 2015 12:06:05 +0100
> Igor Mammedov wrote:
>
> > On Tue, 3 Mar 2015 12:03:26 +1100
> > David Gibson wrote:
> >
> > > On Mon, 2 Mar 2015 22:06:22 +0100
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Mon, Mar 02,
On Mon, Mar 02, 2015 at 10:45:37AM +1030, Rusty Russell wrote:
> "Michael S. Tsirkin" writes:
> > Fix up comment to match virtio 1.0 logic:
> > virtio_blk_outhdr isn't the first elements anymore,
> > the only requirement is that it comes first in
> > the s/g list.
> >
> > Signed-off-by: Michael S.
Gonglei writes:
> On 2015/3/4 21:16, Michael Tokarev wrote:
[...]
>> And a much more general solution is to actually test
>> patches before submitting them. You obviously did not
>> test this series, having 3 errors in 9 patches, ie,
>> 1/3 of your patches does not work...
>>
> Apologize earnes
Current DEFAULT_RAM_SIZE(128MB) enforced by QEMU would not work for
all machines. Introduce a default_ram_size as part of MachineClass.
The below patches has following behaviour:
1) If the user does not provide "-m" option, machine's default ram
size will be picked.
2) In case the user provid
Machines types can have different requirement for default ram
size. Introduce a member in the machine class and set the current
default_ram_size to 128MB.
For QEMUMachine types override the value during the registration of
the machine and for MachineClass introduce the generic class init
setting t
Signed-off-by: Nikunj A Dadhania
---
hw/ppc/spapr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 23cde20..c71ee4b 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -96,6 +96,7 @@ typedef struct sPAPRMachineState sPAPRMachineState;
#define SPAPR_MA
And here's Yet Another pull request, dropping one more patch
("microblaze: fix memory leak") which was broken and escaped
my testing coverage. I left the tag/subject intact, and again,
wont include all the individual patches, which is the same
set as in the original pull request minus 2 patches.
Hi,
I'm trying to implement GICv3 (actually GIC-500) in order to support more than
8 cores for ARM64.
Up to 24 cores I didn't notice any significant problems (just slow boot) but
with 64 or 32 cores the Linux kernel is usually got stuck, seldom it completes
the boot.
When examining the register
* David Gibson (da...@gibson.dropbear.id.au) wrote:
> On Wed, Feb 25, 2015 at 04:51:24PM +, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > Signed-off-by: Dr. David Alan Gilbert
> > ---
> > docs/migration.txt | 189
> >
On 2015/3/5 16:47, Markus Armbruster wrote:
> Hard-won personal experience: the more trivial a change is, the more
> likely I am to screw it up in some stupid way.
>
> In other words: no change is too trivial to screw it up.
>
> Corollary: no change is trivial enough to skip testing.
I can't agre
Gerd Hoffmann writes:
> From: Radim Krčmář
>
> We already have pow2floor, mirror it and use instead of a function with
> similar results (same in used domain), to clarify our intent.
>
> Signed-off-by: Radim Krčmář
> Signed-off-by: Gerd Hoffmann
[...]
> diff --git a/include/qemu-common.h b/inc
Nikunj A Dadhania writes:
> Current DEFAULT_RAM_SIZE(128MB) enforced by QEMU would not work for
> all machines. Introduce a default_ram_size as part of MachineClass.
>
> The below patches has following behaviour:
>
> 1) If the user does not provide "-m" option, machine's default ram
>size wil
Am 05.03.2015 um 01:40 schrieb Eric Blake:
> On 03/03/2015 10:32 AM, Paolo Bonzini wrote:
>>
>>
>> On 03/03/2015 18:19, Oliver Francke wrote:
>>>
>>> #0 __GI_exit (status=1) at exit.c:104
>>> #1 0x5575cf15 in os_daemonize () at os-posix.c:227
>>> #2 0x55773f2e in main (argc=50, a
* Stefan Weil (s...@weilnetz.de) wrote:
> Please see my comments below.
>
> Am 04.03.2015 um 14:31 schrieb Dr. David Alan Gilbert:
> >* Stefan Weil (s...@weilnetz.de) wrote:
> >>Fix type casts between pointers and 64 bit integers.
> >>Now 32 bit builds are possible again.
> >>
> >>Signed-off-by: S
Am 04.03.2015 um 23:06 hat Max Reitz geschrieben:
> On 2015-03-04 at 09:00, Kevin Wolf wrote:
> >Am 09.02.2015 um 18:11 hat Max Reitz geschrieben:
> >>The tray of an FDD is open iff there is no medium inserted (there are
> >>only two states for an FDD: "medium inserted" or "no medium inserted").
>
Hi,
> This patch's implementation of pow2ceil() is needlessly complicated,
> just like pow2floor() in master. Simpler:
>
> uint64_t pow2ceil2(uint64_t value)
> {
> int n = clz64(value - 1);
> return n ? 1ull << (64 - n) : 0;
> }
>
> I can rebase my patch on top of
On Wed, Mar 04, 2015 at 07:37:08AM -0600, Michael Roth wrote:
> Quoting Michael Roth (2015-03-03 23:50:34)
> > Quoting David Gibson (2015-03-02 23:33:39)
> > > On Mon, Mar 02, 2015 at 10:40:16PM -0600, Michael Roth wrote:
> > > > Quoting David Gibson (2015-03-02 01:02:46)
> > > > > On Thu, Feb 26,
On Thu, 5 Mar 2015 14:36:10 +0530
Nikunj A Dadhania wrote:
> Machines types can have different requirement for default ram
> size. Introduce a member in the machine class and set the current
> default_ram_size to 128MB.
>
> For QEMUMachine types override the value during the registration of
> t
On 2015-03-05 08:08, Gerd Hoffmann wrote:
On Mi, 2015-03-04 at 19:12 +, Gordan Bobic wrote:
On 2015-03-04 13:20, Gerd Hoffmann wrote:
> On Di, 2015-03-03 at 10:32 +, Gordan Bobic wrote:
>> I need to pass a custom e820 map to a virtual machine for
>> troubleshooting purposes and working a
On Thu, 5 Mar 2015 14:36:11 +0530
Nikunj A Dadhania wrote:
> Signed-off-by: Nikunj A Dadhania
Reviewed-by: Igor Mammedov
> ---
> hw/ppc/spapr.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 23cde20..c71ee4b 100644
> --- a/hw/ppc/spapr.c
>
Markus Armbruster writes:
> Nikunj A Dadhania writes:
>
>> Current DEFAULT_RAM_SIZE(128MB) enforced by QEMU would not work for
>> all machines. Introduce a default_ram_size as part of MachineClass.
>>
>> The below patches has following behaviour:
>>
>> 1) If the user does not provide "-m" option
* Stefan Weil (s...@weilnetz.de) wrote:
> Am 04.03.2015 um 13:44 schrieb Dr. David Alan Gilbert:
> >* Stefan Weil (s...@weilnetz.de) wrote:
> >>The current code won't compile on 32 bit hosts because there are lots
> >>of type casts between pointers and 64 bit integers.
> >>
> >>Fix some of them.
>
Hi Igor,
Thanks for the review.
Igor Mammedov writes:
> On Thu, 5 Mar 2015 14:36:10 +0530
> Nikunj A Dadhania wrote:
>
>> Machines types can have different requirement for default ram
>> size. Introduce a member in the machine class and set the current
>> default_ram_size to 128MB.
>>
>> For
On Thu, 05 Mar 2015 16:01:40 +0530
Nikunj A Dadhania wrote:
> Hi Igor,
>
> Thanks for the review.
>
> Igor Mammedov writes:
> > On Thu, 5 Mar 2015 14:36:10 +0530
> > Nikunj A Dadhania wrote:
> >
> >> Machines types can have different requirement for default ram
> >> size. Introduce a member
Hi,
> >> Thank you for responding. The situation I have is that my PCIe
> >> bridges are buggy and they seem to bypass the upstream PCIe hub
> >> IOMMU. The problem with this is that when the guest accesses
> >> RAM within it's emulated address space that overlaps with
> >> PCI I/O memory ranges
Thomas Huth writes:
> On Thu, 05 Mar 2015 16:01:40 +0530
> Nikunj A Dadhania wrote:
>
>> Hi Igor,
>>
>> Thanks for the review.
>>
>> Igor Mammedov writes:
>> > On Thu, 5 Mar 2015 14:36:10 +0530
>> > Nikunj A Dadhania wrote:
>> >
>> >> Machines types can have different requirement for defaul
On 2015-03-05 10:42, Gerd Hoffmann wrote:
Hi,
>> Thank you for responding. The situation I have is that my PCIe
>> bridges are buggy and they seem to bypass the upstream PCIe hub
>> IOMMU. The problem with this is that when the guest accesses
>> RAM within it's emulated address space that overl
On s390, we would like to load our "BIOS" s390-ccw.img to the end of the
RAM. Therefor we need the possibility to relocate the ELF file so that
it can also run from different addresses. This patch adds the necessary
code to the QEMU ELF loader function.
Signed-off-by: Thomas Huth
---
hw/core/loa
The current bios sits at location 0x7e0 in the guest RAM
and thus prevents loading of bigger ramdisks. By making the
image relocatable we can move it to the end of the RAM so that
it is getting out of the way.
Signed-off-by: Thomas Huth
---
hw/s390x/ipl.c| 23 ++
Currently, our s390-ccw.img sits at the fix address 126 MiB in memory.
This has two big disadvantages: 1) We can not start guests with less
than 128 MiB RAM and 2) if the guest uses a really huge ramdisk > 126 MiB,
the s390-ccw BIOS gets overwritten and the boot silently crashes.
These two patches
On 05.03.15 12:02, Thomas Huth wrote:
> Currently, our s390-ccw.img sits at the fix address 126 MiB in memory.
> This has two big disadvantages: 1) We can not start guests with less
> than 128 MiB RAM and 2) if the guest uses a really huge ramdisk > 126 MiB,
> the s390-ccw BIOS gets overwritten a
Hi,
> > Add "e820_add_entry(start, size, E820_RESERVED)" calls in qemu.
>
> Could you please point me at the correct file/function to add
> the relevant block into?
There are already calls (in hw/i386/pc.c I think) already, adding
entries for RAM. I'd try to place the code nearby, especially
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Igor Mammedov
---
hw/ppc/spapr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 23cde20..c71ee4b 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -96,6 +96,7 @@ typedef struct sPAPRMachineState sPAPRMac
Current DEFAULT_RAM_SIZE(128MB) enforced by QEMU would not work for
all machines. Introduce a default_ram_size as part of MachineClass.
The below patches has following behaviour:
1) If the user does not provide "-m" option, machine's default ram
size will be picked.
2) The default behaviour o
Machines types can have different requirement for default ram
size. Introduce a member in the machine class and set the current
default_ram_size to 128MB.
For QEMUMachine types override the value during the registration of
the machine and for MachineClass introduce the generic class init
setting t
On 5 March 2015 at 17:54, Shlomo Pongratz wrote:
> Hi,
>
> I'm trying to implement GICv3 (actually GIC-500) in order to support more
> than 8 cores for ARM64.
Fully emulated, or just using the kernel's GICv3 support under KVM?
I assume the former, given that you're talking about TCG below.
> Up
Markus Armbruster writes:
> I propose to route this through the migration tree, because that's
> where pow2floor() came from, and where the dead code is removed.
Self-NAK
There's a simple conflict with a patch from Radim that is in Gerd's
spice pull request: "[PULL 3/7] qxl: refactor rounding u
On 5 March 2015 at 19:24, Nikunj A Dadhania wrote:
> Rejection is also change of behaviour. Because till now, a VM would
> start with any memory size, even if it's less that 128MB
> (default_ram_size). With rejection, all those VMs would fail booting
> displaying the warning. Is this OK?
No. Not
Peter Crosthwaite writes:
> In preparation for support for Cortex a53. Use "axx" to describe the
> shareable features. Some of the CP15 registers (such as ACTLR) are
> specific to implementation, but we currently just RAZ them so continue
> with that as the policy for all cortex A processors und
Peter Crosthwaite writes:
> Similar to a53, but with different L1 I cache policy, phys addr size and
> different cache geometries. The cache sizes is implementation
> configurable, but use these values (from Xilinx MPSoC) as a default
> until cache size configurability is added.
>
> Signed-off-b
Peter Crosthwaite writes:
> In preparation for migrating the state struct and type cast macro to a public
> header. The acronym "GEM" on it's own is not specific enough to be used in a
> more global namespace so preface with "cadence". Fix the capitalisation of
> "gem" in the state type while to
Nikunj A Dadhania writes:
> Markus Armbruster writes:
>
>> Nikunj A Dadhania writes:
>>
>>> Current DEFAULT_RAM_SIZE(128MB) enforced by QEMU would not work for
>>> all machines. Introduce a default_ram_size as part of MachineClass.
>>>
>>> The below patches has following behaviour:
>>>
>>> 1) I
On 02/25/2015 04:14 PM, Bastian Koppelmann wrote:
Hi,
this should be the last major bit of the TriCore integer instructions. The
floating point ones are a whole
different story. These patches depend on my other TriCore patches
(https://patchwork.ozlabs.org/patch/438866/)
and add the promised m
Am 05.03.2015 um 12:10 schrieb Alexander Graf:
>
>
> On 05.03.15 12:02, Thomas Huth wrote:
>> Currently, our s390-ccw.img sits at the fix address 126 MiB in memory.
>> This has two big disadvantages: 1) We can not start guests with less
>> than 128 MiB RAM and 2) if the guest uses a really huge r
On 05.03.15 13:43, Christian Borntraeger wrote:
> Am 05.03.2015 um 12:10 schrieb Alexander Graf:
>>
>>
>> On 05.03.15 12:02, Thomas Huth wrote:
>>> Currently, our s390-ccw.img sits at the fix address 126 MiB in memory.
>>> This has two big disadvantages: 1) We can not start guests with less
>>> t
Am 04.03.2015 um 23:48 hat Stefan Hajnoczi geschrieben:
> Since commit c25f53b06eba1575d5d0e92a0132455c97825b83 ("raw: Probe
> required direct I/O alignment") QEMU has failed to launch if image files
> produce I/O errors.
>
> Previously, QEMU would launch successfully and the guest would see the
>
Am 05.03.2015 um 05:37 hat John Snow geschrieben:
> It has been proposed that the block layer be split up into smaller,
> more manageable portions to help speed up the review and merging of
> block layer patches.
>
> As part of this process, I propose that I take over the IDE, ATA, ATAPI
> and FD
On 05.03.15 12:56, Nikunj A Dadhania wrote:
> Signed-off-by: Nikunj A Dadhania
> Reviewed-by: Igor Mammedov
> ---
> hw/ppc/spapr.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 23cde20..c71ee4b 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/s
On 05.03.15 02:56, Alexey Kardashevskiy wrote:
> At the moment when running in KVM mode, QEMU registers "host" class to
> match the current CPU PVR value. It also registers another CPU class
> with a CPU family name os if we run QEMU on POWER7 machine, "host" and
> "POWER7" classes are created, t
Just for the record, I've tested it using the virt-test reproducer and
indeed the problem is fixed with this patchset. I'm sorry for the delay!
Thanks :)
On Mon, Feb 23, 2015 at 9:56 AM, Alexander Graf wrote:
After the vmdesc self-describing JSON blob landed upstream, some
people
noticed the
From: "Dr. David Alan Gilbert"
Hi,
I'm getting COLO running on a couple of our machines here
and wanted to see what was actually going on, so I merged
in my recent rolling-stats code:
http://lists.gnu.org/archive/html/qemu-devel/2015-03/msg00648.html
with the following patch, and now I get on
On Thu, Mar 05, 2015 at 01:32:02AM +0100, Andreas Färber wrote:
> Am 04.03.2015 um 03:13 schrieb Eduardo Habkost:
> > The APIC ID compatibility code is required only for PC, and now that
> > x86_cpu_initfn() doesn't use x86_cpu_apic_id_from_index() anymore, that
> > code can be moved to pc.c.
> >
From: "Dr. David Alan Gilbert"
Record:
Checkpoint lifetime (ms)
Pause time due to checkpoint (ms)
Checkpoint size (bytes)
Signed-off-by: Dr. David Alan Gilbert
---
hmp.c | 12
include/migration/migration.h | 3 +++
migration/colo.c | 15
On Tue, Mar 03, 2015 at 11:13:41PM -0300, Eduardo Habkost wrote:
> The existing apic_id = cpu_index code has no visible effect: the PC code
> already initializes the APIC ID according to the topology on
> pc_new_cpu(), and linux-user memcpy()s the CPU state (including
> cpuid_apic_id) on cpu_copy()
Am 20.02.2015 um 14:53 hat Alberto Garcia geschrieben:
> This adds a new 'top' parameter to stream_start(), that specifies the
> block device where the data will be written. The image is changed to
> read-write mode during the streaming and back to read-only afterwards.
>
> This also unblocks the
On 05/03/2015 14:43, Eduardo Habkost wrote:
> On Tue, Mar 03, 2015 at 11:13:41PM -0300, Eduardo Habkost wrote:
>> The existing apic_id = cpu_index code has no visible effect: the PC code
>> already initializes the APIC ID according to the topology on
>> pc_new_cpu(), and linux-user memcpy()s the
Am 20.02.2015 um 14:53 hat Alberto Garcia geschrieben:
> This adds the 'top' parameter to the 'block-stream' QMP command and
> checks that its value is valid before passing it to stream_start().
>
> Signed-off-by: Alberto Garcia
> --- a/qapi/block-core.json
> +++ b/qapi/block-core.json
> @@ -101
Thanks for your reply and Happy Lantern Festival!
I am afraid you misunderstood what I mean, maybe I didn't express
clearly :-) My patch works in such case:
Firstly vm has two disks:
[root@fox-host vmimg]# virsh domblklist win7
Target Source
hdb /hom
Alexander Graf writes:
> On 05.03.15 12:56, Nikunj A Dadhania wrote:
>> Signed-off-by: Nikunj A Dadhania
>> Reviewed-by: Igor Mammedov
>> ---
>> hw/ppc/spapr.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
>> index 23cde20..c71ee4b 100644
>> ---
On Wed, 4 Mar 2015 20:12:31 +0100
"Michael S. Tsirkin" wrote:
> On Wed, Mar 04, 2015 at 05:33:42PM +0100, Igor Mammedov wrote:
> > On Wed, 4 Mar 2015 16:31:39 +0100
> > "Michael S. Tsirkin" wrote:
> >
> > > On Wed, Mar 04, 2015 at 04:14:44PM +0100, Igor Mammedov wrote:
> > > > On Wed, 4 Mar 201
Quoting David Gibson (2015-03-04 22:30:40)
> On Wed, Mar 04, 2015 at 07:37:08AM -0600, Michael Roth wrote:
> > Quoting Michael Roth (2015-03-03 23:50:34)
> > > Quoting David Gibson (2015-03-02 23:33:39)
> > > > On Mon, Mar 02, 2015 at 10:40:16PM -0600, Michael Roth wrote:
> > > > > Quoting David Gi
Add encoding for ACPI DefOr Opcode.
Signed-off-by: Marcel Apfelbaum
---
hw/acpi/aml-build.c | 10 ++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 876cada..a31f88e 100644
--- a/hw/acpi/aml-build
Notes:
- Sorry for the late submission, I was waiting for dynamic ACPI series to get
merged
in order to submit - my bad.
- The prev version (v2) was wrongfully tagged by me as RFC, it was actually
ready but not
rebased. V3 only rebases with no actual functionality changed.
- This series
Add encoding for ACPI DefAdd Opcode.
Signed-off-by: Marcel Apfelbaum
---
hw/acpi/aml-build.c | 10 ++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index a31f88e..38b82a4 100644
--- a/hw/acpi/aml-buil
Add encoding for ACPI DefWhile Opcode.
Signed-off-by: Marcel Apfelbaum
---
hw/acpi/aml-build.c | 8
include/hw/acpi/aml-build.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 86b2ddc..eb53d90 100644
--- a/hw/acpi/aml-build.c
Add encoding for ACPI DefIndex Opcode.
Signed-off-by: Marcel Apfelbaum
---
hw/acpi/aml-build.c | 10 ++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 611c949..0b3fcda 100644
--- a/hw/acpi/aml-bu
Add encoding for ACPI DefIncrement Opcode.
Signed-off-by: Marcel Apfelbaum
---
hw/acpi/aml-build.c | 8
include/hw/acpi/aml-build.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 45c1eb1..86b2ddc 100644
--- a/hw/acpi/aml-bui
On Wed, 4 Mar 2015 16:19:25 -0300
Eduardo Habkost wrote:
> On Tue, Mar 03, 2015 at 11:55:24AM +0100, Michael Mueller wrote:
> > On Mon, 02 Mar 2015 17:57:01 +0100
> > Andreas Färber wrote:
> >
> > > Am 02.03.2015 um 17:43 schrieb Michael Mueller:
> > > > On Mon, 02 Mar 2015 14:57:21 +0100
> > >
From: Marcel Apfelbaum
Refactoring it as a method of PCIBusClass will allow
different implementations for subclasses.
Removed the assumption that the root bus does not
have a parent device because is specific only
to the default class implementation.
Signed-off-by: Marcel Apfelbaum
---
hw/pci
Add encoding for ACPI DefShiftRight Opcode.
Signed-off-by: Marcel Apfelbaum
---
hw/acpi/aml-build.c | 10 ++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index ac27b40..45c1eb1 100644
--- a/hw/acpi/a
Add encoding for ACPI DefLLess Opcode.
Signed-off-by: Marcel Apfelbaum
---
hw/acpi/aml-build.c | 9 +
include/hw/acpi/aml-build.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 38b82a4..611c949 100644
--- a/hw/acpi/aml-build
From: Marcel Apfelbaum
Instead of assuming it has only one bus, it
enumerates all the host bridges until it finds
the one with bus number corresponding with the
config register.
Signed-off-by: Marcel Apfelbaum
---
hw/pci-host/piix.c | 57 +-
Add encoding for ACPI DefShiftLeft Opcode.
Signed-off-by: Marcel Apfelbaum
---
hw/acpi/aml-build.c | 10 ++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 0b3fcda..ac27b40 100644
--- a/hw/acpi/am
This refactoring moves all the code needed (recursively)
to register TYPE_PCI_BUS type to a new file hw/pci/pci_bus.c .
This allows to properly add new functionality to the pci bus class.
Signed-off-by: Marcel Apfelbaum
---
arch_init.c | 1 +
hw/alpha/typhoon.c | 1 +
hw/m
The bios does not index the pxb slot number when
it computes the IRQ because it resides on bus 0
and not on the current bus.
However Qemu routes the irq through bus 0 and adds
the pxb slot to the IRQ computation.
Synchronize between bios and Qemu by canceling
pxb's effect.
Signed-off-by: Marcel A
Signed-off-by: Marcel Apfelbaum
---
hw/i386/acpi-build.c | 78
1 file changed, 78 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index e5709e8..f0401d2 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -66
From: Marcel Apfelbaum
Use the newer pci_bus_num to correctly get the root bus number.
Signed-off-by: Marcel Apfelbaum
---
hw/pci/pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index e386f2c..53598bd 100644
--- a/hw/pci/pci.c
+++ b/hw/pc
Markus Armbruster writes:
> Nikunj A Dadhania writes:
>
>> Markus Armbruster writes:
>>
>>> Nikunj A Dadhania writes:
>>>
Current DEFAULT_RAM_SIZE(128MB) enforced by QEMU would not work for
all machines. Introduce a default_ram_size as part of MachineClass.
The below patche
From: Marcel Apfelbaum
This is a marker interface used to differentiate the
"default" host bridge on a system with multiple host bridges.
This differentiation is required only for pc machines for now
by the ACPI subsystem.
Signed-off-by: Marcel Apfelbaum
---
hw/i386/acpi-build.c | 9 +
From: Marcel Apfelbaum
The bios looks for 'etc/extra-pci-roots' to decide if
is going to scan further buses after bus 0 tree.
Signed-off-by: Marcel Apfelbaum
---
hw/i386/pc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index ae3ef0a..71d2f5b 1
If the machine has several root busses, we need to add them to
acpi in order to be properly detected by guests.
Signed-off-by: Marcel Apfelbaum
---
hw/i386/acpi-build.c | 32
1 file changed, 32 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build
also causes problems with java.
** Summary changed:
- qemu-arm-static bug in signal handling avoids using mono
+ qemu-arm-static bug in signal handling causes mono to hang
** Summary changed:
- qemu-arm-static bug in signal handling causes mono to hang
+ qemu-arm-static bug in signal handling c
On Thu, Mar 05, 2015 at 03:04:25PM +0100, Kevin Wolf wrote:
> The bs parameter is now only used for the following things:
>
> 1. As the default for top
Right.
> 2. For error handling: Any errors are reported for bs, even though
>they are actually for top. Is this correct behaviour? It looks
Marcel Apfelbaum writes:
> On 03/05/2015 01:56 PM, Nikunj A Dadhania wrote:
>> Machines types can have different requirement for default ram
>> size. Introduce a member in the machine class and set the current
>> default_ram_size to 128MB.
>>
>> For QEMUMachine types override the value during the
Hi Peter,
Thank you for your response.
You are correct, I'm implementing fully emulated GIC-500.
I assume that you are correct and indeed I have a bug in the implementation, I
think it is related to timing somehow as by adding debug printouts the system
is more likely to boot.
I'll prepare a RF
2015-03-05 12:57+0800, Dongsheng Song:
> On Wed, Mar 4, 2015 at 10:30 PM, Gerd Hoffmann wrote:
> > +/* round up to the nearest power of 2 (0 if overflow) */
> > +uint64_t pow2ceil(uint64_t value)
> > +{
> > +uint8_t nlz = clz64(value);
> > +
> > +if (is_power_of_2(value)) {
> > +re
Rename the function so that the reason for its existence is clearer: it
does x86-specific initialization of TCG structures.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 2 +-
target-i386/cpu.h | 2 +-
target-i386/translate.c | 2 +-
3 files changed, 3 insertions(+), 3 delet
Machines types can have different requirement for default ram
size. Introduce a member in the machine class and set the current
default_ram_size to 128MB.
For QEMUMachine types override the value during the registration of
the machine and for MachineClass introduce the generic class init
setting t
2015-03-05 10:52+0100, Markus Armbruster:
> Gerd Hoffmann writes:
>
> > From: Radim Krčmář
> >
> > We already have pow2floor, mirror it and use instead of a function with
> > similar results (same in used domain), to clarify our intent.
> >
> > Signed-off-by: Radim Krčmář
> > Signed-off-by: Ger
If multiple root busses are used, root bus 0 cannot use all the
pci holes ranges. Remove the IO/mem ranges used by the other
primary busses.
Signed-off-by: Marcel Apfelbaum
---
hw/i386/acpi-build.c | 84
1 file changed, 72 insertions(+), 12 de
To allow new code to ask the CPU classes for CPU model information and
allow QOM properties to be queried by qmp_device_list_properties(), we
need to be able to safely instantiate a X86CPU object without any
side-effects.
cpu_exec_init() has lots of side-effects on global QEMU state, move it
to re
On Thu, Mar 05, 2015 at 03:09:58PM +0100, Kevin Wolf wrote:
> > { 'command': 'block-stream',
> > - 'data': { 'device': 'str', '*base': 'str', '*backing-file': 'str',
> > -'*speed': 'int', '*on-error': 'BlockdevOnError' } }
> > + 'data': { 'device': 'str', '*base': 'str', '*top': 'st
From: Marcel Apfelbaum
Signed-off-by: Marcel Apfelbaum
---
hw/pci/pci.c | 8
include/hw/pci/pci_host.h | 4
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 53598bd..f0cf752 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@
From: Marcel Apfelbaum
PXB is a "light-weight" host bridge whose purpose is to enable
the main host bridge to support multiple PCI root buses.
As oposed to PCI-2-PCI bridge's secondary bus, PXB's bus
is a primary bus and can be associated with a NUMA node
(different from the main host bridge) al
Save the IO/mem/bus numbers ranges assigned to the extra root busses
to be removed from the root bus 0 range.
Signed-off-by: Marcel Apfelbaum
---
hw/i386/acpi-build.c | 149 +++
1 file changed, 149 insertions(+)
diff --git a/hw/i386/acpi-build.c b
On Thu, Mar 05, 2015 at 04:15:52PM +0100, Kevin Wolf wrote:
> > > 3. As the BDS that owns the job
> > >
> > > My question is whether we can't simply call stream_start()
> > > with an intermediate node as bs instead of introducing a new
> > > parameter. I'm not completely sure about the consequenc
On Thu, Mar 05, 2015 at 03:56:03PM +0100, Michael Mueller wrote:
> On Wed, 4 Mar 2015 16:19:25 -0300
> Eduardo Habkost wrote:
>
> > On Tue, Mar 03, 2015 at 11:55:24AM +0100, Michael Mueller wrote:
> > > On Mon, 02 Mar 2015 17:57:01 +0100
> > > Andreas Färber wrote:
> > >
> > > > Am 02.03.2015 u
To allow new code to ask the CPU classes for CPU model information and
allow QOM properties to be queried by qmp_device_list_properties(), we
need to be able to safely instantiate a X86CPU object without any
side-effects.
This series moves some code from x86_cpu_initfn() to x86_cpu_realizefn(), so
The pxb can be attach to and existing numa node by specifying
numa_node option that equals the desired numa nodeid.
Signed-off-by: Marcel Apfelbaum
---
hw/i386/acpi-build.c| 12
hw/pci-bridge/pci_expander_bridge.c | 17 +
2 files changed, 29 insertion
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