Peter Crosthwaite <peter.crosthwa...@xilinx.com> writes:
> In preparation for support for Cortex a53. Use "axx" to describe the
> shareable features. Some of the CP15 registers (such as ACTLR) are
> specific to implementation, but we currently just RAZ them so continue
> with that as the policy for all cortex A processors under a shared
> definition.
>
> The cache sizes and geometeries, the L1 I-cache policy and the physical
> address range differ between A53 and A57 so those particulars are left
> as A57 specific. The rest are moved to the generalisation.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
> ---
> target-arm/cpu64.c | 32 +++++++++++++++++++-------------
> 1 file changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 823c739..5cf3121 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -38,22 +38,22 @@ static inline void unset_feature(CPUARMState *env, int
> feature)
> }
>
> #ifndef CONFIG_USER_ONLY
> -static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +static uint64_t axx_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> /* Number of processors is in [25:24]; otherwise we RAZ */
> return (smp_cpus - 1) << 24;
> }
> #endif
>
> -static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
> +static const ARMCPRegInfo cortexaxx_cp_reginfo[] = {
> #ifndef CONFIG_USER_ONLY
> { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
> - .access = PL1_RW, .readfn = a57_l2ctlr_read,
> + .access = PL1_RW, .readfn = axx_l2ctlr_read,
> .writefn = arm_cp_write_ignore },
> { .name = "L2CTLR",
> .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
> - .access = PL1_RW, .readfn = a57_l2ctlr_read,
> + .access = PL1_RW, .readfn = axx_l2ctlr_read,
> .writefn = arm_cp_write_ignore },
> #endif
> { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
> @@ -92,10 +92,8 @@ static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> -static void aarch64_a57_initfn(Object *obj)
> +static void aarch64_axx_initfn(ARMCPU *cpu)
> {
> - ARMCPU *cpu = ARM_CPU(obj);
> -
> set_feature(&cpu->env, ARM_FEATURE_V8);
> set_feature(&cpu->env, ARM_FEATURE_VFP4);
> set_feature(&cpu->env, ARM_FEATURE_NEON);
> @@ -107,13 +105,10 @@ static void aarch64_a57_initfn(Object *obj)
> set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
> set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> set_feature(&cpu->env, ARM_FEATURE_CRC);
> - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
> - cpu->midr = 0x411fd070;
> cpu->reset_fpsid = 0x41034070;
> cpu->mvfr0 = 0x10110222;
> cpu->mvfr1 = 0x12111111;
> cpu->mvfr2 = 0x00000043;
> - cpu->ctr = 0x8444c004;
> cpu->reset_sctlr = 0x00c50838;
> cpu->id_pfr0 = 0x00000131;
> cpu->id_pfr1 = 0x00011011;
> @@ -132,14 +127,25 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->id_aa64pfr0 = 0x00002222;
> cpu->id_aa64dfr0 = 0x10305106;
> cpu->id_aa64isar0 = 0x00011120;
> - cpu->id_aa64mmfr0 = 0x00001124;
> cpu->dbgdidr = 0x3516d000;
> cpu->clidr = 0x0a200023;
> + cpu->dcz_blocksize = 4; /* 64 bytes */
> + define_arm_cp_regs(cpu, cortexaxx_cp_reginfo);
> +}
> +
> +static void aarch64_a57_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + aarch64_axx_initfn(cpu);
> +
> + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
> + cpu->midr = 0x411fd070;
> + cpu->ctr = 0x8444c004; /* L1Ip = PIPT */
> + cpu->id_aa64mmfr0 = 0x00001124; /* 44 bit physical addr */
> cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
> cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
> cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
> - cpu->dcz_blocksize = 4; /* 64 bytes */
> - define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
> }
>
> #ifdef CONFIG_USER_ONLY
--
Alex Bennée
